| 367457 |
07-Nov-2020 |
dim |
MFC r344855 (by jhb):
Drop "All rights reserved" from my copyright statements.
Reviewed by: rgrimes
Differential Revision: https://reviews.freebsd.org/D19485 |
| 358591 |
03-Mar-2020 |
dim |
MFC r358407:
Merge r358406 from the clang1000-import branch:
Fix the following -Werror warning from clang 10.0.0:
sys/arm/arm/identcpu-v6.c:227:5: error: misleading indentation; statement is not part of the previous 'if' [-Werror,-Wmisleading-indentation]
if (val & CPUV7_CT_CTYPE_RA)
^
sys/arm/arm/identcpu-v6.c:225:4: note: previous statement is here
if (val & CPUV7_CT_CTYPE_WB)
^
This was due to an accidentally inserted tab before the if statement. |
| 356064 |
24-Dec-2019 |
loos |
MFC r320001 by zbb:
Fix typo in "Marvell" string
Change Marwell to Marvell
Pointed out by: Ravi Pokala <rpokala@mac.com>
Sponsored by: Rubicon Communications, LLC (Netgate) |
| 355346 |
03-Dec-2019 |
kevans |
MFC rarm: correct kernelstack allocation size
This appears to be a copy-pasto from previous lines that propagated to v6
over the years. Indeed, nothing references kernelstack beyond
USPACE_SVC_STACK_TOP and it would be odd if anything did. |
| 346561 |
22-Apr-2019 |
ian |
MFC r346312:
Only set up the interrupts that will actually be used in arm generic_timer.
The code previously set up interrupt handlers for all the interrupt
resources available, including for timers that are not in use. That could
lead to interrupt storms. For example, if boot firmware enabled the virtual
timer but the kernel is using the physical timer, it could get flooded with
interrupts on the virtual timer which it cannot shut off. By only setting
up an interrupt handler for the hardware that will actually be used, any
interrupts from other timer units will remain masked in the interrupt
controller.
Differential Revision: https://reviews.freebsd.org/D19871 |
| 346551 |
22-Apr-2019 |
ian |
MFC r342850:
Add a missing \n to a bootverbose printf. |
| 344905 |
08-Mar-2019 |
jhb |
MFC 340020: Don't enter DDB for fatal traps before panic by default.
Add a new 'debugger_on_trap' knob separate from 'debugger_on_panic'
and make the calls to kdb_trap() in MD fatal trap handlers prior to
calling panic() conditional on this new knob instead of
'debugger_on_panic'. Disable the new knob by default. Developers who
wish to recover from a fatal fault by adjusting saved register state
and retrying the faulting instruction can still do so by enabling the
new knob. However, for the more common case this makes the user
experience for panics due to a fatal fault match the user experience
for other panics, e.g. 'c' in DDB will generate a crash dump and
reboot the system rather than being stuck in an infinite loop of fatal
fault messages and DDB prompts. |
| 344619 |
27-Feb-2019 |
kevans |
MFC r336262: Fix machdep_boot.c
A last minute change made this no longer compile. Pass the right arg
and eliminate now-unused variables from the code. |
| 344383 |
20-Feb-2019 |
kevans |
MFC r336283: Fix build after r344378
Eliminate an unused var warning-error; the var is used only when parsing
linux-style boot args, so wrap it in the appropriate ifdef. |
| 344378 |
20-Feb-2019 |
kevans |
MFC r336244, r336246-r336247: Standardize boot arg parsing
r336244:
Create helper functions for parsing boot args.
boot_parse_arg to parse a single arg
boot_parse_cmdline to parse a command line string
boot_parse_args to parse all the args in a vector
boot_howto_to_env Convert howto bits to env vars
boot_env_to_howto Return howto mask mased on what's set in the environment.
All these routines return an int that's the bitmask of the args
translated to RB_* flags. As a special case, the 'S' flag sets the
comconsole_speed env var. Any arg that looks like a=b will set the env
key 'a' to value 'b'. If =b is omitted, 'a' is set to '1'. This
should help us reduce the number of redundant copies of these routines
in the tree. It should also give a more uniform experience between
platforms.
Also, invent a new flag RB_PROBE that's set when 'P' is parsed. On
x86 + BIOS, this means 'probe for the keyboard, and if it's not there
set both RB_MULTIPLE and RB_SERIAL (which means show the output on
both video and serial consoles, but make serial primary). Others it
may be some similar concept of probing, but it's loader dependent
what, exactly, it means.
These routines are suitable for /boot/loader and/or the kernel,
though they may not be suitable for the tightly hand-rolled-for-space
environments like boot2.
r336246:
Eliminate boot loader copies of boot arg parsing.
Eliminate 4 of the copies of the arg parsing in /boot/laoder
by using boot_parse_cmdline.
r336247:
Transition to boot_env_to_howto and boot_howto_to_env in the boot
loader. |
| 341717 |
08-Dec-2018 |
kib |
MFC r341374:
Correct the tunable name in the message.
PR: 231577 |
| 341491 |
04-Dec-2018 |
markj |
MFC r341442, r341443:
Plug memory disclosures via ptrace(2). |
| 341166 |
28-Nov-2018 |
vangyzen |
MFC r340995
Prevent kernel stack disclosure in signal delivery
On arm64 and riscv platforms, sendsig() failed to zero the signal
frame before copying it out to userspace. Zero it.
On arm, I believe all the contents of the frame were initialized,
so there was no disclosure. However, explicitly zero the whole frame
because that fact could inadvertently change in the future,
it's more clear to the reader, and I could be wrong in the first place.
Security: similar to FreeBSD-EN-18:12.mem and CVE-2018-17155
Sponsored by: Dell EMC Isilon |
| 338867 |
21-Sep-2018 |
markj |
MFC r338211:
Prepare the kernel linker to handle PC-relative ifunc relocations. |
| 338694 |
15-Sep-2018 |
markj |
MFC r338537, r338539:
Bump MAX_HWCNT and MAX_EXCNT. |
| 338484 |
05-Sep-2018 |
kib |
MFC r338370:
Remove {max/min}_offset() macros, use vm_map_{max/min}() inlines. |
| 335556 |
22-Jun-2018 |
avg |
MFC r333667: followup to r332730/r332752: set kdb_why to "trap" for fatal traps
This change updates arm, arm64 and mips achitectures. Additionally, it
removes redundant checks for kdb_active where it already results in
kdb_reenter() and adds kdb_reenter() calls where they were missing.
Some architectures check the return value of kdb_trap(), but some don't.
I haven't changed any of that.
Some trap handling routines have a return code. I am not sure if I
provided correct ones for returns after kdb_reenter(). kdb_reenter
should never return unless kdb_jmpbufp is NULL for some reason. |
| 331988 |
04-Apr-2018 |
mmel |
MFC r328467:
Implement mitigation for Spectre version 2 attacks on ARMv7. |
| 331968 |
04-Apr-2018 |
mmel |
MFC r319896,r320054:
r319896:
Implement tunable CPU quirks. These quirks are intended for optimizing CPU
performance, not for applying errata workarounds. Nobody can expect that
CPU with unfixed errata is stable enough to execute the kernel until quirks
are applied.
r320054:
Manually load tunable CPU quirks. These are needed too early, far before
SYSINIT is processed. |
| 331893 |
02-Apr-2018 |
gonzo |
MFC r306263, r306268
r306263 by andrew:
Move cpu_reset to be a platform method to allow multiple implementations.
Reviewed by: mmel
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D8010
r306268 by andrew:
Also implement platform_cpu_reset on bcm2836 |
| 331891 |
02-Apr-2018 |
gonzo |
MFC r304488, r304623
r304488 by manu:
Keep boot parameters in ARM trampoline code
Currently boot parameters (r0 - r3) are forgotten in ARM trampoline code.
This patch save them at startup and restore them before jumping into kernel
_start() routine.
This is usefull when booting with Linux ABI and/or custom bootloader.
Submitted by: Grégory Soutadé <soutade@gmail.com>
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D7395
r304623 by manu:
Fix building for ARM kernel that have FLASHADDR, PHYSADDR and LOADERRAMADDR defined.
Pointy Hat: myself
Reported by: bz |
| 331890 |
02-Apr-2018 |
gonzo |
MFC r305094, r305096-r305097
r305094 by cognet:
Garbage collect bits forgotten in r295267.
r305096 by cognet:
Some old arm ports don't load the kernel at the beginning of the memory,
because the bootloader, ie redboot, won't let them do so, and so used the
memory before the kernel for early memory allocation, such as pagetables,
stacks, etc...
Make a bit of an effort to try to get that memory mapped.
r305097 by cognet:
Nuke obio_bs_tag, it was used before it was initialized, and
arm_base_bs_tag is the same, anyway. |
| 331722 |
29-Mar-2018 |
eadler |
Revert r330897:
This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.
Revert with prejudice.
This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.
Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.
Requested by: gjb (re) |
| 331643 |
27-Mar-2018 |
dim |
MFC r314568 (by emaste):
kern_sig.c: ANSIfy and remove archaic register keyword
Sponsored by: The FreeBSD Foundation
MFC r318389 (by emaste):
Remove register keyword from sys/ and ANSIfy prototypes
A long long time ago the register keyword told the compiler to store
the corresponding variable in a CPU register, but it is not relevant
for any compiler used in the FreeBSD world today.
ANSIfy related prototypes while here.
Reviewed by: cem, jhb
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D10193 |
| 331524 |
25-Mar-2018 |
ian |
MFC r329989, r330044
r329989:
Add support for booting into kdb on arm platforms when the RB_KDB is set
(using "boot -d" at the loader propmt or setting boot_ddb in loader.conf).
Submitted by: Thomas Skibo <thomasskibo@yahoo.com>
Differential Revision: https://reviews.freebsd.org/D14428
r330044:
Add a hw.model sysctl oid for armv6/7 which reports the CPU model, similar
to what other arches (all except riscv and armv4/5) do.
Submitted by: Hyun Hwang <hyun@caffeinated.codes>
Differential Revision: https://reviews.freebsd.org/D14465 |
| 331520 |
25-Mar-2018 |
ian |
MFC r330050:
Initialize all members of vm_page::md_page for armv4/5 systems. This fixes
a hang in SI_SUB_KMEM sysinit, and is apparently required after r323290.
Inspired by the commit message for r323676.
Reported by: andreast@ |
| 331017 |
15-Mar-2018 |
kevans |
MFC r317055,r317056 (glebius): Include sys/vmmeter.h as included
r317055: All these files need sys/vmmeter.h, but now they got it implicitly
included via sys/pcpu.h.
r317056: Typo! |
| 330897 |
14-Mar-2018 |
eadler |
Partial merge of the SPDX changes
These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.
No objections from: pfg |
| 329280 |
14-Feb-2018 |
gonzo |
MFC r320387:
[arm] Use correct index value when checking range validity
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D9145 |
| 329263 |
14-Feb-2018 |
skra |
MFC r325321:
Take into account race conditions in case of accessed or modified bit
emulation in fast path of data/prefetch abort common routine. Process these
bits only if related page table entries are consistent with provided abort
info. In case of inconsistency, do nothing and let processor to signal new
abort if still needed. |
| 328967 |
07-Feb-2018 |
mmel |
MFC r324821:
Fix spelling. |
| 328386 |
25-Jan-2018 |
pkelsey |
MFC r316648:
Corrected misspelled versions of rendezvous.
The MFC maintains smp_no_rendevous_barrier() as a symbol alias of
smp_no_rendezvous_barrier().
__FreeBSD_version bumped to indicate presence of the new name
smp_no_rendezvous_barrier().
Reviewed by: gnn, jhb (email), kib
Differential Revision: https://reviews.freebsd.org/D10313 |
| 327667 |
07-Jan-2018 |
ian |
MFC r327222:
Add a new ARM kernel option, LOCORE_MAP_MB, to control the size of the
kernel VA mapping in the temporary page tables set up by locore-v6.S.
The number used to be hard-coded to 64MB, which is still the default if
the kernel option is not specified. However, 64MB is insufficient for
using a large mdroot filesystem. The hard-coded number can't be safely
increased because too large a number may run into memory-mapped IO space
on some SoCs that must not be mapped as ordinary memory. |
| 327658 |
07-Jan-2018 |
ian |
MFC r327367:
Make kernel option KERNVIRTADDR optional, remove it from std.<platform>
files that can use the default value.
It used to be required that the low-order bits of KERNVIRTADDR matched
the low-order bits of the physical load address for all arm platforms.
That hasn't been a requirement for armv6 platforms since FreeBSD 10.
There is no longer any relationship between load addr and KERNVIRTADDR
except that both must be aligned to a 2 MiB boundary.
This change makes the default KERNVIRTADDR value 0xc0000000, and removes the
options from all the platforms that can use the default value. The default
is now defined in vmparam.h, and that file is now included in a few new
places that reference KERNVIRTADDR, since it may not come in via the
forced-include of opt_global.h on the compile command line. |
| 327656 |
06-Jan-2018 |
ian |
MFC r327048-r327050
r327048:
Restore the ability to use EARLY_PRINTF support during most of initarm().
The real kernel page tables are set up much earlier in initarm() now than
they were when early printf support was first added, and they end up undoing
the mapping made in locore.S for early printf support. This re-adds the
mapping after switching to the new/real kernel page tables, making early
printf work again right after switching to them.
r327049:
Allow pmap_kremove() to remove 1MB section mappings as well as 4K pages.
This will allow it to undo temporary device mappings such as those made
with pmap_preboot_map_attr().
Reviewed by: cognet
r327050:
If a temporary mapping is made to support EARLY_PRINTF, undo that mapping
after cninit() runs, otherwise we leave a bogus device-memory mapping in
userspace VA in the kernel pmap forever.
Pointed out by: cognet |
| 326313 |
28-Nov-2017 |
andrew |
MFC r326137:
Ensure we check the program state set in the trap frame on arm and arm64.
This value may be set by userspace so we need to check it before using it.
If this is not done correctly on exception return the kernel may continue
in kernel mode with all registers set to a userspace controlled value. Fix
this by moving the check into set_mcontext, and also add the missing
sanitisation from the arm64 set_regs.
Discussed with: security-officer@
Sponsored by: DARPA, AFRL |
| 325837 |
15-Nov-2017 |
jhb |
MFC 323584: Add a NT_ARM_VFP ELF core note to hold VFP registers for each thread.
The core note matches the format and layout of NT_ARM_VFP on Linux.
Debuggers use the AT_HWCAP flags to determine how many VFP registers
are actually used and their format. |
| 325831 |
14-Nov-2017 |
jhb |
MFC 323581,323582,323583: Add ptrace operations for VFP registers.
323581:
Only mess with VFP state on the CPU for curthread for get/set_vfpcontext.
Future changes will use these functions to fetch and store VFP state for
threads other than curthread.
323582:
Add ptrace operations to fetch and store VFP registers.
323583:
Export get/set_vfpcontext from machdep.c.
Should have been part of the previous commit to add ptrace operations
for VFP registers. |
| 325810 |
14-Nov-2017 |
jhb |
MFC 323580,323933,323934,324814,324817: Enable AT_HWCAP on arm.
I reused the SV_HWCAP stub to cover the sv_hwcap2 field as well.
323580:
Add AT_HWCAP flags for VFP settings for FreeBSD/arm.
These flags match the meaning and value of flags in Linux, though
Linux has many more flags.
323933:
Correct HWCAP_VFP3* values to match Linux.
323934:
Detect NEON and set HWCAP_NEON if present.
324814:
Add AT_HWCAP2 ELF auxiliary vector.
- allocate value for new AT_HWCAP2 auxiliary vector on all platforms.
- expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly
same way as for AT_HWCAP.
324817:
Fullify implementation of AT_HWCAP and AT_HWCAP2 for ARMv6,7.
This makes elf_aux_info(3) useable for ARM ports.
Tested by: mmel |
| 325307 |
02-Nov-2017 |
mmel |
MFC r324660:
Save VFP state in getcontext(3) on ARM. This is a last followup of r315974,
which fixes userland part of VFP save/restore problems described in PR
217611. |
| 325238 |
31-Oct-2017 |
markj |
MFC r324920:
Fix the VM_NRESERVLEVEL == 0 build. |
| 324400 |
07-Oct-2017 |
alc |
MFC r305685
Various changes to pmap_ts_referenced()
Move PMAP_TS_REFERENCED_MAX out of the various pmap implementations and
into vm/pmap.h, and describe what its purpose is. Eliminate the archaic
"XXX" comment about its value. I don't believe that its exact value, e.g.,
5 versus 6, matters.
Update the arm64 and riscv pmap implementations of pmap_ts_referenced()
to opportunistically update the page's dirty field.
On amd64, use the PDE value already cached in a local variable rather than
dereferencing a pointer again and again. |
| 323424 |
11-Sep-2017 |
ian |
MFC r321686:
Add inline functions to convert between sbintime_t and decimal time units.
Use them in some existing code that is vulnerable to roundoff errors. |
| 321343 |
21-Jul-2017 |
kib |
MFC r319873:
Move struct syscall_args syscall arguments parameters container into
struct thread. |
| 321049 |
16-Jul-2017 |
emaste |
MFC r320056: arm: set appropriate section flags for .init_pagetable
The arm kernel linker scripts place the .init_pagetable section in .bss,
but .init_pagetable had no section flags set, and so did not match the
expected flags for .bss.
GNU ld silently ignores this case, but lld reports an error:
ld: error: incompatible section flags for .bss
>>> locore.o:(.init_pagetable): 0x0
>>> output section .bss: 0x3
PR: 220055
Sponsored by: The FreeBSD Foundation |
| 319915 |
13-Jun-2017 |
emaste |
MFC r317428 (cognet): fix arm64 MSI
In arm_gicv2m_alloc_msi(), if we found a suitable irq range, leave the loop
before we increase irq again, or we'd end up choosing an irq, and then
really using the next one, even if it's not available.
Also in the inner loop, correct the end check so that we check every irq,
even the last one.
This makes the msk(4) adapter able to use MSI on Softiron Overdrive 1000.
PR: 219956
Approved by: re (gjb) |
| 318976 |
27-May-2017 |
hselasky |
MFC r318353:
Avoid use of contiguous memory allocations in busdma when possible.
This patch improves the boundary checks in busdma to allow more cases
using the regular page based kernel memory allocator. Especially in
the case of having a non-zero boundary in the parent DMA tag. For
example AMD64 based platforms set the PCI DMA tag boundary to
PCI_DMA_BOUNDARY, 4GB, which before this patch caused contiguous
memory allocations to be preferred when allocating more than PAGE_SIZE
bytes. Even if the required alignment was less than PAGE_SIZE bytes.
This patch also fixes the nsegments check for using kmem_alloc_attr()
when the maximum segment size is less than PAGE_SIZE bytes.
Updated some comments describing the code in question.
Differential Revision: https://reviews.freebsd.org/D10645
Reviewed by: kib, jhb, gallatin, scottl
Sponsored by: Mellanox Technologies |
| 318742 |
23-May-2017 |
mmel |
MFC r318021,r318251:
r318021:
Introduce pmap_remap_vm_attr(), it allows to remap one VM memattr class to
another.
r318251:
Clarify usage rules for pmap_remap_vm_attr(). Not a functional change. |
| 317976 |
08-May-2017 |
gonzo |
MFC r310791:
[qemu] Fix VERSATILEPB kernel boot in QEMU broken by r300968
QEMU does not implement hardware debug registers so when
dbg_monitor_is_enabled is called kernel receives "invalid instruction"
exception. QEMU implements only DIDR register and on read returns all
zeroes to indicate that it doesn't support other registers. Real
hardware has Version bits set. |
| 317188 |
20-Apr-2017 |
skra |
MFC r308569,r308570:
r308569:
Always call PHYS_TO_VM_PAGE() in is_managed(). Fast road for addresses
under first_page cannot be taken as this variable is connected only to
vm_page_array segment. There could be more segments in system like the ones
for various fictitious page ranges. These can be situated under
vm_page_array segment and so, they could be skipped before this fix.
However, as far as I know, there is no report associated with it.
r308570:
The return type of is_managed() was changed from boolean_t to bool type in
r308569. Now, propagate this change further for consistency sake. |
| 317005 |
16-Apr-2017 |
mmel |
MFC r315900,r315973,r315974:
r315900:
Cleanup structures related to VFP and/or mcontext_t. - in mcontext_t,
rename newer used 'union __vfp' to equaly sized 'mc_spare'.
Space allocated by 'union __vfp' is too small and cannot hold full VFP
context.
- move structures defined in fp.h to more appropriate headers. - remove
all unused VFP structures.
r315973:
Save VFP state on fork(). Update the copy of VFP state in PCB before it is
cloned for new process.
r315974:
Preserve VFP state across signal delivery. |
| 317004 |
16-Apr-2017 |
mmel |
MFC r303261,r315059:
r303261:
Add more UEFI/e820 memory types from latest specifications.
r315059:
Split overbloated machep.c to multiple files and do basic cleanup of these
fragments. |
| 317003 |
16-Apr-2017 |
mmel |
MFC r306704,r308406:
r306704:
ARM: Remove next bunch of unused cpu_functions from ARMv6.
r308406:
Only include sys/boot.h if LINUX_BOOT_ABI is defined |
| 317002 |
16-Apr-2017 |
mmel |
MFC r306631,r306640,r306641,r306650,r306656:
r306631:
Use C99 designated initializers to create the armv6 cpu_functions structs.
This will help with a later cleanup of what functions we implement.
r306640:
Only define the CF_* macros on ARMv4/v5. They are unused on armv6.
r306641:
Remove the parts of cpu_functions from armv6 that are unused on that
architecture.
r306650:
Add the Cortex-A{53,57,72} ID register values. These can all run 32-bit
code so could run a 32-bit kernel.
r306656:
Use the cortex functions when booting on one of the Cortex-A ARMv8 CPUs.
This list is incomplete, however we don't have the ID values for the
missing Cortex-A32 or A35. |
| 314530 |
02-Mar-2017 |
ian |
MFC r312292, r313573:
Stop including sys/types.h from arm's machine/atomic.h, fix the places
where atomic.h was being included without ensuring that types.h (via
param.h) was included first, as required by atomic(9).
Remove arm's cpuconf.h, and references to it, after moving a few lines from
it into pmap-v4.h where they are used. Other than those few lines of
support for different MMU types, nothing in cpuconf.h has been used in our
code for quite a while.
The file existed to set up a variety of symbols to describe the
architecture. Over the past few years we have converted all of our source
to use the new architecture symbols standardized by ARM Inc, and predefined
by both clang and gcc. |
| 314526 |
01-Mar-2017 |
ian |
MFC r312251:
Remove a bit of armv6 support that didn't get deleted when this file was
split from trap.c into trap-v4.c and trap-v6.c. |
| 314525 |
01-Mar-2017 |
ian |
MFC r306901:
ARM: Split identify_arm_cpu() into ARMv4 and ARMv6 variant.
On ARMv6, be more verbose about supported CPU features and/or
optional instructions. |
| 314506 |
01-Mar-2017 |
ian |
MFC r306262, r306267, r310021: (needed to avoid conflicts on later merges)
Remove bus_dma_get_range and bus_dma_get_range_nb on armv6. We only need
this on a few earlier arm SoCs.
Restrict where we need to define fdt_fixup_table to just PowerPC and
Marvell.
Add the missing void to function signatures in much of the arm code. |
| 314296 |
26-Feb-2017 |
kib |
MFC r313933, r313939, r313966:
Microoptimize pmap_protect_pde() on amd64, i386 and
pmap_protect_pte1() on armv6. |
| 313766 |
15-Feb-2017 |
jah |
MFC r312610, r312792
r312610:
Like r310481 for i386, move the objects used to create temporary
mappings for armv6 pmap zero and copy operations to the MD PCPU region.
Change sysmap initialization to only allocate KVA pages for CPUs that
are actually present.
While here, collapse CMAP3 into CMAP2 (their use was mutually exclusive
anyway) and "recover" some space in PCPU padding that has always been
available due to 64-byte cacheline padding.
r312792:
Further cleanup of per-CPU armv6 pmap data:
- Replace pcpu_find(curcpu) with get_pcpu(), which is much more direct.
- Remove armv4 pcpu fields which I added in r286296 but never needed
to use.
- armv6 pc_qmap_addr was leftover from the old armv6 pmap
implementation. Rename it and put it to use in the new one. |
| 312394 |
18-Jan-2017 |
jhb |
MFC 307332,312086: Drop support for using mmap() with /dev/kmem.
307332:
Drop support for using mmap() with /dev/kmem.
Using the device pager with /dev/kmem is not stable since KVA mappings
are transient, but the device pager caches the PA associated with a
given offset forever. Interestingly, mips' implementation of
memmap() already refused requests for /dev/kmem.
Note that kvm_read/kvm_write do not use mmap, but use read and write on
/dev/kmem, so this should not affect libkvm users.
312086:
Trim a few comments on platforms that did not implement mmap of /dev/kmem.
After r307332, no platforms implement mmap for /dev/kmem, so the lack of
it for these platforms is no longer unique. |
| 308382 |
06-Nov-2016 |
gonzo |
MFC r306899, r307059, r307151
r306899:
Fix release MSI method for ARM GIC
r307059:
INTRNG - fix MSI/MSIX release path
Use isrc in attached MSI data structure instead of using map's
isrc directly. map's isrc is set to NULL on IRQ deactivation
which happens prior to pci_release_msi so MSI_RELEASE_MSI
receives array of NULLs
Reviewed by: mmel
Differential Revision: https://reviews.freebsd.org/D8206
r307151:
INTRNG: Propagate IRQ activation error to API consumer
Keep resource state consistent with INTRNG state - if intr_activate_irq
fails - deactivate resource and propagate error to calling function
Reviewed by: mmel |
| 308333 |
05-Nov-2016 |
mmel |
MFC r304459,r305527:
r304459:
INTRNG: Rework handling with resources. Partially revert r301453.
- Read interrupt properties at bus enumeration time and store
it into global mapping table.
- At bus_activate_resource() time, given mapping entry is resolved and
connected to real interrupt source. A copy of mapping entry is attached
to given resource.
- At bus_setup_intr() time, mapping entry stored in resource is used
for delivery of requested interrupt configuration.
- For MSI/MSIX interrupts, mapping entry is created within
pci_alloc_msi()/pci_alloc_msix() call.
- For legacy PCI interrupts, mapping entry must be created within
pcib_route_interrupt() by pcib driver itself.
r305527:
Fix MIPS INTRNG (both FDT and non-FDT) behaviour broken by r304459 |
| 307345 |
15-Oct-2016 |
mmel |
MFC r306759:
ARM: Remove ARMv4 #defines from busdma_machdep-v6.c, it's ARMv6 specific
file. Consistently use BUSDMA_DCACHE_ALIGN for cache line alignment. |
| 307344 |
15-Oct-2016 |
mmel |
MFC r306756:
ARM: SEV/WFE instructions are implemented starting from ARMv6K, use it
directly. |
| 307342 |
15-Oct-2016 |
mmel |
MFC r306755:
ARM: Add identifiers for ARM Cortex v8 and Marvell Sheeva v7 cores. Not a
functional change. |
| 307341 |
15-Oct-2016 |
mmel |
MFC r306754:
ARM: Remove unused variable. Not a functional change. |
| 307136 |
12-Oct-2016 |
ed |
MFC r306162:
Make it possible to safely use TPIDRURW from userspace.
On amd64, arm64 and i386, we have the possibility to switch between TLS
areas in userspace. The nice thing about this is that it makes it easier
to do light-weight threading, if we ever feel like doing that. On armv6,
let's go into the same direction by making it possible to safely use the
TPIDRURW register, which is intended for this purpose.
Clean up the ARMv6 code to remove md_tp entirely. Simply add a dedicated
field to the PCB to hold the value of TPIDRURW across context switches,
like we do for any other register. As userspace currently uses the
read-only TPIDRURO register, simply ensure that we keep both values in
sync where possible. The system calls for modifying the read-only
register will simply write the intended value into both registers, so
that it lazily ends up in the PCB during the next context switch.
Approved by: andrew
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D7951 |
| 306907 |
09-Oct-2016 |
jmcneill |
MFC r306658: Clear GT_CTRL_ENABLE to stop the timer. |
| 306558 |
01-Oct-2016 |
alc |
MFC r305213,305319,305398
As an optimization to the machine-independent layer, change the machine-
dependent pmap_ts_referenced() so that it updates the page's dirty field
if a modified bit is found while counting reference bits. This
opportunistic update can be performed at low cost and can eliminate the
need for some future calls to pmap_is_modified() by the machine-
independent layer.
Replace the number 4 in sparc64's pmap_ts_referenced() by
PMAP_TS_REFERENCED_MAX, like we've done elsewhere, e.g., amd64. |
| 306316 |
25-Sep-2016 |
kib |
MFC r305942:
Consolidate four efi_next_descriptor() definitions. |
| 305866 |
16-Sep-2016 |
kib |
MFC r304285:
Implement userspace gettimeofday(2) with HPET timecounter. |
| 305780 |
13-Sep-2016 |
markj |
MFC r305425:
Remove an unreachable return statement from ARM's minidumpsys(). |
| 302408 |
08-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.
Additional commits post-branch will follow.
Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation |
| 301961 |
16-Jun-2016 |
kib |
Update comments for the MD functions managing contexts for new
threads, to make it less confusing and using modern kernel terms.
Rename the functions to reflect current use of the functions, instead
of the historic KSE conventions:
cpu_set_fork_handler -> cpu_fork_kthread_handler (for kthreads)
cpu_set_upcall -> cpu_copy_thread (for forks)
cpu_set_upcall_kse -> cpu_set_upcall (for new threads creation)
Reviewed by: jhb (previous version)
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Approved by: re (hrs)
Differential revision: https://reviews.freebsd.org/D6731
|
| 301890 |
14-Jun-2016 |
andrew |
Move the arm call to intr_pic_init_secondary earlier in the secondary CPU
initialisation. This ensures it will complete before signalling to the boot
CPU it has booted. This fixes a race with the GIC where the arm_gic_map may
not be populated before it is used to bind interrupts leading to some
interrupts becoming bound to no CPUs.
Approved by: re (kib)
Sponsored by: ABT Systems Ltd
|
| 301700 |
08-Jun-2016 |
andrew |
Remove the ARMv4/ARMv5 userland atomic support from struct proc on armv6.
Nothing should use this on armv6 as we use the atomic instructions added in
ARMv6k.
Sponsored by: ABT Systems Ltd
|
| 301561 |
07-Jun-2016 |
andrew |
Start to clean MIDR values using the CPUID scheme. We don't need to know
the exact CPU we are running on to set the cpu functions. Relax the check
to ignore the CPU revision. Even so this may still be too specific.
Reviewed by: mmel
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D6504
|
| 301453 |
05-Jun-2016 |
skra |
INTRNG - change the way how an interrupt mapping data are provided
to the framework in OFW (FDT) case.
This is a follow-up to r301451.
Differential Revision: https://reviews.freebsd.org/D6634
|
| 301267 |
03-Jun-2016 |
skra |
Define irq variable only in the block where used.
|
| 301062 |
31-May-2016 |
andrew |
arm_gic_map is a mask not the CPUs ID, there is no need to shift it.
Pointy-hat to: andrew
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
|
| 301060 |
31-May-2016 |
andrew |
Bin interrupts to the correct CPU when we boot on a non-zero CPU.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
|
| 300969 |
29-May-2016 |
zbb |
Improve ARM debug_monitor for SMP machines
- Reset debug architecture and enable monitor for secondary
CPUs in init_secondary() rather than when configuring watchpoint, etc.
- Disable HW debugging capabilities when one of the CPU cores fails
to set up.
- Use dbg_capable() in a more atomic manner to avoid any mismatch
between CPUs.
Differential Revision: https://reviews.freebsd.org/D6009
|
| 300968 |
29-May-2016 |
zbb |
Fix debug_monitor code for older ARMs (ARM11)
- Enable monitor mode prior to accessing watchpoint
registers for v6, v6.1 architectures.
- Fix configuration scheme for v6, v6.1 and v7 Debug Archs
- Enable monitor unconditionally and for good instead
of enabling and disabling it (needed for single stepping
on on v6/v6.1)
Tested on RPI-B and Arndale
Differential Revision: https://reviews.freebsd.org/D6008
|
| 300951 |
29-May-2016 |
mmel |
ARM GIC: Allow to setup interrupt without configuration data.
In some cases, like for PCI devices, only interrupt numbers are enumerated
from HW. In this case, use INTR_foo_CONFORM as level and trigger values.
|
| 300701 |
26-May-2016 |
ian |
Disable alignment faults on armv6, adjust various alignment-related macros
to match the new state of affairs. The hardware we support has always been
able to do unaligned accesses, we've just never enabled it until now.
This brings FreeBSD into line with all the other major OSes, and should help
with the growing volume of 3rd-party software that assumes unaligned access
will just work on armv6 and armv7.
|
| 300694 |
25-May-2016 |
ian |
Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't
have ACLE support built in. The ACLE (ARM C Language Extensions) defines
a set of standardized symbols which indicate the architecture version and
features available. ACLE support is built in to modern compilers (both
clang and gcc), but absent from gcc prior to 4.4.
ARM (the company) provides the acle-compat.h header file to define the
right symbols for older versions of gcc. Basically, acle-compat.h does
for arm about the same thing cdefs.h does for freebsd: defines
standardized macros that work no matter which compiler you use. If ARM
hadn't provided this file we would have ended up with a big #ifdef __arm__
section in cdefs.h with our own compatibility shims.
Remove #include <machine/acle-compat.h> from the zillion other places (an
ever-growing list) that it appears. Since style(9) requires sys/types.h
or sys/param.h early in the include list, and both of those lead to
including cdefs.h, only a couple special cases still need to include
acle-compat.h directly.
Loves it: imp
|
| 300674 |
25-May-2016 |
skra |
Add more info about the issue fixed in r298460. Rephrase some sentences
and fix grammar.
No functional change.
Suggested by: alc
Reviewed by: alc
|
| 300534 |
23-May-2016 |
ian |
Oops, fix a paste-o commited in r300533.
|
| 300533 |
23-May-2016 |
ian |
Use the new(-ish) CP15_SCTLR macro to generate system control reg accesses
where possible. In the places that doesn't work (multi-line inline asm,
and places where the old armv4 cpufuncs mechanism is used), annotate the
accesses with a comment that includes SCTLR. Now a grep -i sctlr can find
all the system control register manipulations.
No functional changes.
|
| 300149 |
18-May-2016 |
andrew |
Return the struct intr_pic pointer from intr_pic_register. This will be
needed in later changes where we may not be able to lock the pic list lock
to perform a lookup, e.g. from within interrupt context.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
|
| 300051 |
17-May-2016 |
bz |
The GIC (v2 at least) has a bit in the TYPER register to indicate whether the GIC
supports the Security Extensions or not. This bit is not the same as the CPU one.
Currently we are not checking for either before trying to write to the special
registers. This can lead to problems on hardware or simulators that do not
provide the security extensions. Add the missing checks. Their interactions with
the CPU flag is not entirely clear to me but using a macro will make it easier
to quickly adjust the condition once the CPU bits are sorted as well.
Reviewed by: br
Sponsored by: DARPA/AFRL
Differential Revision: https://reviews.freebsd.org/D6397
|
| 299928 |
16-May-2016 |
andrew |
Introduce MSI and MSI-X support to intrng. This adds a new msi device
interface with 5 methods to mirror the 5 MSI/MSI-X methods in the pcib
interface. The pcib driver will need to perform a device specific lookup
to find the MSI controller and pass this to intrng as the xref. Intrng
will finally find the controller and have it handle the requested operation.
Obtained from: ABT Systems Ltd
MFH: yes
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5985
|
| 299851 |
15-May-2016 |
manu |
Allow arm generic_timer code to be included even if not present in the
SoC.
Reviewed by: andrew
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D6372
|
| 299383 |
10-May-2016 |
manu |
When PLATFORM_SMP is enabled, check if tunable hw.ncpu is set and valid
(>= 1 and <= real ncores) and set mp_ncpus to it.
Approved by: andrew (mentor)
Differential Revision: https://reviews.freebsd.org/D6151
|
| 299122 |
05-May-2016 |
jhb |
Fix <sys/_bitset.h> and <sys/_cpuset.h> to not require <sys/param.h>.
- Hardcode '8' instead of NBBY in _BITSET_BITS.
- Define a private version of 'howmany' for use in __bitset_words().
- While here, move a few more things out of _bitset.h and _cpuset.h to
bitset.h and cpuset.h, respectively. The only things left in
_bitset.h and _cpuset.h are the bits needed to define a bitset
structure.
Reviewed by: bde, kib (ish)
|
| 299117 |
05-May-2016 |
skra |
INTRNG - redefine struct intr_map_data to avoid headers pollution. Each
struct associated with some type defined in enum intr_map_data_type
must have struct intr_map_data on the top of its own definition now.
When such structs are used, correct type and size must be filled in.
There are three such structs defined in sys/intr.h now. Their
definitions should be moved to corresponding headers by follow-up
commits.
While this change was propagated to all INTRNG like PICs,
pic_map_intr() method implementations were corrected on some places.
For this specific method, it's ensured by a caller that the 'data'
argument passed to this method is never NULL. Also, the return error
values were standardized there.
|
| 299072 |
04-May-2016 |
bz |
The virtual timer is optional on ARM64. Properly handle that condition. [1]
In case we do not have an interrupt assignment for the virtual timer,
force the physical timer.
Also skip resource allocation for any timer we do not have an interrupt
assignment for.
In collaboration with: andrew
Submitted by: br ([1] from his gem5 arm64 work)
Sponsored by: DARPA/AFRL
Reviewed by: andrew
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D6203
|
| 299071 |
04-May-2016 |
bz |
The ARM generic timer keeps ticking even if disabled or it expired.
In case of updating it with a very low value it might expire again
after writing the tval but before updating ctrl. In that case we do
lose the status bit saying that the timer expired and we will consequently
not get an interrupt for it, leaving the timer in a "dead" state.
In order to solve this increase the minimum period with what the timer
can be loaded to something higher.
Found & analysed with: gem5
Debugged with: andrew
Sponsored by: DARPA/AFRL
Reviewed by: andrew
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D6202
|
| 299069 |
04-May-2016 |
pfg |
sys/arm: Minor spelling fixes.
Only affects comments: no functional change.
|
| 298854 |
30-Apr-2016 |
andrew |
Add a MULTIDELAY option to allow the ARM kernel to have multiple DELAY
implementations. Early in the boot the kernel will use an approximate,
however after the timer has been probed it will switch to a more accurate
implementation.
Reviewed by: manu
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5762
|
| 298740 |
28-Apr-2016 |
mmel |
ARM: Use kernel pmap as intermediate mapping in context switch.
On ARM, we can directly switch between translation tables only when
the size of the mapping for any given virtual address is the same in
the old and new translation tables. The load of new TTB and subsequent
TLB flush is not atomic operation. So speculative page table walk can
load TLB entry from new mapping while rest of TLB entries are still the
old ones. In worst case, this can lead to situation when TLB cache can
contain multiple matching TLB entries. One (from old mapping) L2 entry
for VA + 4k and one (from new mapping) L1 entry for VA.
Thus, we must switch to kernel pmap translation table as intermediate
mapping because all sizes of these (old pmap and kernel pmap) mappings
are same (or unmapped). The same is true for switch from kernel pmap
translation table to new pmap one.
|
| 298648 |
26-Apr-2016 |
bz |
Mark the unused period argument __unused.
Reviewed by: andrew
MFC after: 2 weeks
Sponsored by: DARPA/AFRL
|
| 298643 |
26-Apr-2016 |
pfg |
sys/arm: make use of the howmany() macro when available.
We have a howmany() macro in the <sys/param.h> header that is
convenient to re-use as it makes things easier to read.
|
| 298627 |
26-Apr-2016 |
br |
Move arm's devmap to some generic place, so it can be used
by other architectures.
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D6091
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
|
| 298460 |
22-Apr-2016 |
skra |
Fix duplicate TLB entries issue during section promotion/demotion.
Such situation is defined as UNPREDICTABLE by arm arm manual.
This patch fixes all explicit TLB fetches which could cause this issue
and speculative TLB fetches for sections mapped in user address space.
Speculative TLB fetches for sections mapped in kernel address space are
not fixed yet as the break-before-make approach must be implemented for
kernel mappings too. This means that promoted/demoted section will be
unmapped for a while. Either kernel stack the promotion/demotion is
being done on or L1 page table(s) which must be modified may be mapped
by this section. Thus the fix will not be so simple like for userland
mappings.
The issue was detectable only on Cortex-A8 platforms and only very
rarely. It was reported few times. First, it was by Mikael Urankar
in June 2015. He helped to identify the mechanism of this issue, but
we were not sure how to fix it correctly until now.
PR: 208381
Reported by: Mikael Urankar (mikael.urankar at gmail.com)
Reviewed by: kib
|
| 298457 |
22-Apr-2016 |
skra |
Don't use atomic operations for page table entries and handle access
and R/W emulation aborts under pmap lock.
There were two reasons for using of atomic operations:
(1) the pmap code is based on i386 one where they are used,
(2) there was an idea that access and R/W emulation aborts should be
handled as quick as possible, without pmap locking.
However, the atomic operations in i386 pmap code are used only because
page table entries may be modified by hardware. At the beginning, we
were not sure that it's the only reason. So even if arm hardware does
not modify them, we did not risk to not use them at that time. Further,
it turns out after some testing that using of pmap lock for access and
R/W emulation aborts does not bring any extra cost and there was no
measurable difference. Thus, we have decided finally to use pmap lock
for all operations on page table entries and so, there is no reason for
atomic operations on them. This makes the code cleaner and safer.
This decision introduce a question if it's safe to use pmap lock for
access and R/W emulation aborts. Anyhow, there may happen two cases in
general:
(A) Aborts while the pmap lock is locked already - this should not
happen as pmap lock is not recursive. However, under pmap lock only
internal kernel data should be accessed and such data should be mapped
with A bit set and NM bit cleared. If double abort happens, then
a mapping of data which has caused it must be fixed.
(B) Aborts while another lock(s) is/are locked - this already can
happen. There is no difference here if it's either access or R/W
emulation abort, or if it's some other abort.
Reviewed by: kib
|
| 298433 |
21-Apr-2016 |
pfg |
sys: use our roundup2/rounddown2() macros when param.h is available.
rounddown2 tends to produce longer lines than the original code
and when the code has a high indentation level it was not really
advantageous to do the replacement.
This tries to strike a balance between readability using the macros
and flexibility of having the expressions, so not everything is
converted.
|
| 298403 |
21-Apr-2016 |
andrew |
Make the GIC SGI global variables static, they are only ever used within
within this file.
Approved by: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
|
| 298352 |
20-Apr-2016 |
pfg |
Use our nitems() macro when param.h is available.
Replacements specific to arm, mips, pc98, powerpc and sparc64.
Discussed in: freebsd-current
|
| 298068 |
15-Apr-2016 |
andrew |
Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine
independent code that needs to know about INTRNG such as PCI drivers.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
|
| 298055 |
15-Apr-2016 |
pfg |
arm: for pointers replace 0 with NULL.
These are mostly cosmetical, no functional change.
Found with devel/coccinelle.
|
| 298054 |
15-Apr-2016 |
andrew |
Add a flag field to struct gic_irqsrc and use it to mark when we should
write to the End of Interrupt (EOI) register before handling the interrupt.
This should be a noop as it will be set for all edge triggered interrupts,
however this will not be the case for MSI interrupts. These are also edge
triggered, however we should not write to the EOI register until later in
arm_gic_pre_ithread.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
|
| 298051 |
15-Apr-2016 |
andrew |
Add initial GICv2m support to the arm GIC driver. This will be used to
support MSI and MSI-X interrupts, however intrng needs updates before this
can happen.
For now we just attach the driver until the MSI API is ready.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5950
|
| 297793 |
10-Apr-2016 |
pfg |
Cleanup unnecessary semicolons from the kernel.
Found with devel/coccinelle.
|
| 297682 |
07-Apr-2016 |
ian |
Fix a copyright glitch before it gets copy-pasted again. I think this must
have started as collateral damage in a global search-replace, then it got
copied around when I cloned a file to begin creating a new file.
|
| 297677 |
07-Apr-2016 |
skra |
Properly initialize isrc_cpu field of ISRC which is setup for an IPI.
|
| 297674 |
07-Apr-2016 |
skra |
Implement intr_isrc_init_on_cpu() and use it to replace very same
code implemented in every interrupt controller driver running SMP.
This function returns true, if provided ISRC should be enabled on
given cpu.
|
| 297561 |
04-Apr-2016 |
andrew |
Add a table to map from the FreeBSD CPUID space to the GIC CPUID space. On
many SoCs these two are the same, however there is no requirement for this
to be the case, e.g. on the ARM Juno we boot on what the GIC thinks of as
CPU 2, but FreeBSD numbers it CPU 0.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
|
| 297539 |
04-Apr-2016 |
skra |
Remove FDT specific parts from INTRNG. Change its interface to make it
universal.
(1) New struct intr_map_data is defined as a container for arbitrary
description of an interrupt used by a device. Typically, an interrupt
number and configuration relevant to an interrupt controller is encoded
in such description. However, any additional information may be encoded
too like a set of cpus on which an interrupt should be enabled or vendor
specific data needed for setup of an interrupt in controller. The struct
intr_map_data itself is meant to be opaque for INTRNG.
(2) An intr_map_irq() function is created which takes an interrupt
controller identification and struct intr_map_data as arguments and
returns global interrupt number which identifies an interrupt.
(3) A set of functions to be used by bus drivers is created as well as
a corresponding set of methods for interrupt controller drivers. These
sets take both struct resource and struct intr_map_data as one of the
arguments. There is a goal to keep struct intr_map_data in struct
resource, however, this way a final solution is not limited to that.
(4) Other small changes are done to reflect new situation.
This is only first step aiming to create stable interface for interrupt
controller drivers. Thus, some temporary solution is taken. Interrupt
descriptions for devices are stored in INTRNG and two specific mapping
function are created to be temporary used by bus drivers. That's why
the struct intr_map_data is not opaque for INTRNG now. This temporary
solution will be replaced by final one in next step.
Differential Revision: https://reviews.freebsd.org/D5730
|
| 297390 |
29-Mar-2016 |
andrew |
Read the CPU ID for the current CPU from the GIC. The GIC may have a
different ID space than the kernel. Because of this we need to read the
ID from the hardware. The hardware will provide this value to the CPU by
reading any of the first 8 Interrupt Processor Targets Registers.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5706
|
| 297292 |
26-Mar-2016 |
mmel |
ARM: Fix bug introduced in r297286.
- don't put command line without guard to kernel environment.
- kernel environment delivered from ubldr must have absolute precedence.
|
| 297286 |
26-Mar-2016 |
mmel |
ARM: Parse command line delivered by U-Boot:
- in atags
- in DT blob (by using 'fdt chosen' U-Boot command)
The command line must start with guard's string 'FreeBSD:' and can contain
list of comma separated kenv strings. Also, boot modifier strings from
boot.h are recognised and parsed into boothowto.
The command line must be passed from U-Boot by setting of bootargs variable:
'setenv bootargs FreeBSD:boot_single=1,vfs.root.mountfrom=ufs:/dev/ada0s1a'
followed by 'fdt chosen' (only for DT based boot)
|
| 297285 |
26-Mar-2016 |
mmel |
ARM: Fix ATAG handling in LINUX_BOOT_API:
- Don't convert atags address passed from U-Boot. It's real physical
address (and we have 1:1 mapping).
- Size of tags is encoded in words, not in bytes
|
| 297284 |
26-Mar-2016 |
mmel |
ARM: Teach LINUX_BOOT_ABI to recognize DT blob.
This allow us to boot FreeBSD kernel (using uImage encapsulation) directly
from U-boot using 'bootm' command or by Android fastboot loader.
For now, kernel uImage must be marked as Linux, but we can add support for
FreeBSD into U-Boot later.
|
| 297230 |
24-Mar-2016 |
skra |
Generalize IPI support for ARM intrng and use it for interrupt
controller IPI provider.
New struct intr_ipi is defined which keeps all info about an IPI:
its name, counter, send and dispatch methods. Generic intr_ipi_setup(),
intr_ipi_send() and intr_ipi_dispatch() functions are implemented.
An IPI provider must implement two functions:
(1) an intr_ipi_send_t function which is able to send an IPI,
(2) a setup function which initializes itself for an IPI and
calls intr_ipi_setup() with appropriate arguments.
Differential Revision: https://reviews.freebsd.org/D5700
|
| 296981 |
17-Mar-2016 |
andrew |
Make it an error to build an ARM kernel with COMPAT_FREEBSDn where n < 10.
We changed the ABI for ARM in 10, an removed support for the old ABI in 11,
as such binaries from these releases are unable to be run on a head kernel.
Reviewed by: bz, emast
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5652
|
| 296948 |
16-Mar-2016 |
emaste |
Remove armeb FreeBSD 6 compat shim
r296861 addressed a build failure due to undefined SYS_freebsd6_lseek
by adding a COMPAT_FREEBSD6 conditional, but we do not support FreeBSD 6
compatibility on armeb anyway so remove it completely.
Reviewed by: andrew, bz
Differential Revision: https://reviews.freebsd.org/D5643
|
| 296861 |
14-Mar-2016 |
bz |
Only check for SYS_freebsd6_lseek if the syscall code is defined.
Whether this is the right or best solution is unclear but it fixes the
build for now.
|
| 296824 |
14-Mar-2016 |
wma |
Fix GIC interrupt decoding in INTRNG code
Bug was already fixed in not-INTRNG code, it needs to be corrected
here as well. Source: https://reviews.freebsd.org/rS294422
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: cognet, wma
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D5029
|
| 296313 |
02-Mar-2016 |
andrew |
The cpu_reset_needs_v4_MMU_disable variable is only used in locore-v4.S,
only define it when building for ARMv5 or prior.
Sponsored by: ABT Systems Ltd
|
| 296265 |
01-Mar-2016 |
andrew |
Make the memory size returned from fdt_get_mem_regions a 64-bit type. This
is the physical memory size so may be larger than a u_long can hold, e.g.
on ARM with LPAE we could see an address space of up to 40 bits. On ARM
u_long is only 32 bits so the memory size will be truncated, possibly to
zero.
Reported by: bz
Sponsored by: ABT Systems Ltd
|
| 296258 |
01-Mar-2016 |
andrew |
Stop setting the memory size in the arm EFI and FDT code, we don't use it.
Sponsored by: ABT Systems Ltd
|
| 296250 |
01-Mar-2016 |
jhibbits |
Correct the memory rman ranges to be to BUS_SPACE_MAXADDR
Summary:
As part of the migration of rman_res_t to be typed to uintmax_t, memory ranges
must be clamped appropriately for the bus, to prevent completely bogus addresses
from being used.
This is extracted from D4544.
Reviewed By: cem
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D5134
|
| 296189 |
29-Feb-2016 |
wma |
Fix fdt_get_mem_regions() to work with 64-bit addresses
Use u_long instead of uint32_t variables to avoid overflow
in case of PA space bigger than 32-bit.
Obtained from: Semihalf
Submitted by: Michal Stanek <mst@semihalf.com>
Sponsored by: Annapurna Labs
Approved by: cognet (mentor)
Reviewed by: andrew, br, wma
Differential revision: https://reviews.freebsd.org/D5393
|
| 296158 |
28-Feb-2016 |
andrew |
Add SMP support to the ARM PLATFORM code. This will allow us to have
different methods to start the secondary cores in a kernel built for
multiple SoCs, e.g. with the Allwinner A20 and A31.
Sponsored by: ABT systems Ltd
Differential Revision: https://reviews.freebsd.org/D5466
|
| 296138 |
27-Feb-2016 |
skra |
Move IPI related parts back to (ARM) machine specific file now, when
the interrupt framework is also going to be used by another (MIPS)
architecture. IPI implementations may vary much across different
architectures.
An IPI implementation should still define INTR_IPI_COUNT and use
intr_ipi_setup_counters() to setup IPI counters which are inside of
intrcnt[] and intrnames[] arrays. Those are used for sysctl and ddb.
Then, intr_ipi_increment_count() should be used to increment obtained
counter.
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D5459
|
| 296100 |
26-Feb-2016 |
andrew |
Almost all copies of platform_mp_init_secondary just called
intr_pic_init_secondary. Replace them with a direct call. On BCM2836
and ARMADA XP we need to add this function, but it can be empty.
Reviewed by: ian, imp
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5460
|
| 296098 |
26-Feb-2016 |
andrew |
Remove platform_mp_probe as it's almost identical on most ARM SoCs, and
slightly wrong on the others. We should just check if mp_ncpus is set to
more than one CPU as we may wish to run on a single core even when SMP is
available.
Reviewed by: ian
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5458
|
| 296066 |
25-Feb-2016 |
andrew |
Remove platform_ipi_send, it's an unneeded as all implementations are
identical.
Sponsored by: ABT Systems Ltd
|
| 296064 |
25-Feb-2016 |
jmcneill |
Add Allwinner A20 HDMI support.
The HDMI driver will attach a framebuffer device when a display is
connected. If the EDID can be read and contains a preferred mode, it
will be used. Otherwise the framebuffer will default to 800x600.
In addition, if the EDID contains a CEA-861 extension block and the
"basic audio" flag is set, audio playback at 48kHz 16-bit stereo is
enabled on the controller.
Reviewed by: andrew
Approved by: gonzo (mentor)
Differential Revision: https://reviews.freebsd.org/D5383
|
| 295920 |
23-Feb-2016 |
skra |
Remove redundant __ARM_ARCH >= 6 check in armv6 specific files.
|
| 295887 |
22-Feb-2016 |
skra |
Remove armv6 specific part from armv4 specific file and update comment.
No functional change.
|
| 295882 |
22-Feb-2016 |
skra |
As <machine/vmparam.h> is included from <vm/vm_param.h>, there is no
need to include it explicitly when <vm/vm_param.h> is already included.
Suggested by: alc
Reviewed by: alc
Differential Revision: https://reviews.freebsd.org/D5379
|
| 295881 |
22-Feb-2016 |
skra |
As <machine/param.h> is included from <sys/param.h>, there is no need
to include it explicitly when <sys/param.h> is already included.
Reviewed by: alc, kib
Differential Revision: https://reviews.freebsd.org/D5378
|
| 295880 |
22-Feb-2016 |
skra |
As <machine/pmap.h> is included from <vm/pmap.h>, there is no need to
include it explicitly when <vm/pmap.h> is already included.
Reviewed by: alc, kib
Differential Revision: https://reviews.freebsd.org/D5373
|
| 295834 |
20-Feb-2016 |
skra |
Rename busdma_machdep.c to busdma_machdep-v4.c, pmap.c to pmap-v4.c
and trap.c to trap-v4.c to be plain and consistent with other armv4
specific files.
|
| 295804 |
19-Feb-2016 |
skra |
Remove not used static function pmap_kenter_attr().
|
| 295801 |
19-Feb-2016 |
skra |
Rename pte.h to pte-v4.h and start including directly either pte-v4.h
or pte-v6.h in files which needs it.
There are quite internal definitions in pte-v4.h and pte-v6.h headers
specific for corresponding pmap implementation. These headers should be
included only in very few files and an intention is to not hide for
which implementation such files are.
Further, sys/arm/arm/elf_trampoline.c is an example of file which
uses armv4 like pmap implementation for both armv4 and armv6 platforms.
This is another reason why pte.h which includes specific header
according to __ARM_ARCH is not created.
|
| 295755 |
18-Feb-2016 |
zbb |
Introduce bus_get_bus_tag() method
Provide bus_get_bus_tag() for sparc64, powerpc, arm, arm64 and mips
nexus and its children in order to return a platform specific default tag.
This is required to ensure generic correctness of the bus_space tag.
It is especially needed for arches where child bus tag does not match
the parent bus tag. This solves the problem with ppc architecture
where the PCI bus tag differs from parent bus tag which is big-endian.
This commit is a part of the following patch:
https://reviews.freebsd.org/D4879
Submitted by: Marcin Mazurek <mma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Annapurna Labs
Reviewed by: jhibbits, mmel
Differential Revision: https://reviews.freebsd.org/D4879
|
| 295751 |
18-Feb-2016 |
skra |
Remove redundant L2_ADDR_MASK definition and replace it by primary one.
|
| 295703 |
17-Feb-2016 |
skra |
Do not use PMAP_DOMAIN_KERNEL definition for __ARM_ARCH >= 6 as domains
are not utilized there. Only domain #0 is used and there is no reference
to it in the whole pmap-v6.c. Thus initialize domain access register in
locore-v6.c without reference too.
|
| 295696 |
17-Feb-2016 |
skra |
Remove unneeded vector_page_setprot() for __ARM_ARCH >= 6. A vector
page is always mapped in KVA space and so it's always writeable.
|
| 295694 |
17-Feb-2016 |
skra |
Remove pd_prot and pd_cache members from struct arm_devmap_entry.
The struct is used for definition of static device mappings which
should always have same protection and attributes.
|
| 295693 |
17-Feb-2016 |
skra |
Evaluate also VM_PROT_EXECUTE protection in pmap_preboot_map_attr().
Before this change all mappings done by this function were executable
as pte entries have NOT EXECUTABLE bit.
The function is used only for static device mappings at present. Thus
this is also a fix as DEVICE memory should not be mapped as executable.
|
| 295662 |
16-Feb-2016 |
andrew |
Allow callers of OF_decode_addr to get the size of the found mapping. This
will allow for code that uses the old fdt_get_range and fdt_regsize
functions to find a range, map it, access, then unmap to replace this, up
to and including the map, with a call to OF_decode_addr.
As this function should only be used in the early boot code the unmap is
mostly do document we no longer need the mapping as it's a no-op, at least
on arm.
Reviewed by: jhibbits
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5258
|
| 295633 |
15-Feb-2016 |
andrew |
Set sc->clkfreq removed in r295470
Reported by: Jared McNeill <jmcneill@invisible.ca>
Pointy-hat to: andrew
|
| 295628 |
15-Feb-2016 |
andrew |
Remove an unused static inline function.
Sponsored by: ABT Systems Ltd
|
| 295470 |
10-Feb-2016 |
andrew |
Use OF_getencprop to read a property, it already handles the endian
conversion so we don't need to pass the data through fdt32_to_cpu.
|
| 295451 |
09-Feb-2016 |
glebius |
Include sys/_task.h into uma_int.h, so that taskqueue.h isn't a
requirement for uma_int.h.
Suggested by: jhb
|
| 295319 |
05-Feb-2016 |
mmel |
ARM: Use new ARMv6 naming conventions for cache and TLB functions
in all but ARMv4 specific files.
Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address
in L2 cache functions if ARM_L2_PIPT is defined.
|
| 295317 |
05-Feb-2016 |
skra |
Follow up r295257 and replace bad reference to TEX in defines,
variables and functions. This stuff is named properly now.
Thus, the VM_MEMATTR_xxx is an index to PTE2 attribute table.
Pointy hat to: skra
|
| 295316 |
05-Feb-2016 |
skra |
Follow up r295257 and convert also pt_memattr. This did not break
anything as both VM_MEMATTR_WB_WA and PTE2_ATTR_WB_WA are zero.
Correct also type of pmap_dcache_wb_pou() last argument.
|
| 295315 |
05-Feb-2016 |
mmel |
ARM: Introduce new cpu-v4.h header and move all ARMv4 specific code
from cpu-v6.h to it.
Remove unneeded cpu-v6.h includes.
|
| 295267 |
04-Feb-2016 |
mmel |
Replace broken implementation of fuswintr() and suswintr() by functions
which return -1 as well as on tier 1 archs. Remove block_userspace_access
used only in these implementations.
(1) These functions may be called in interrupt context and pcb_onfault
can be already set in this time. Thus, prior pcb_onfault must be saved
and restored afterwards.
(2) The check that an abort came either from nested interrupt or while
in critical section or holding not sleepable lock must be avoided for
this case.
These functions are called only for profiling reason, so there will be
only small gain by making the code more complex.
|
| 295259 |
04-Feb-2016 |
mmel |
ARM: For ARMv6/v7, code in locore.S initializes SCTLR and ACTRL registers.
Don't duplicate this initialization in cpu_setup().
|
| 295257 |
04-Feb-2016 |
skra |
Make VM_MEMATTR_xxx definitions independent on pmap internals
for __ARM_ARCH >= 6.
It's TEX class number now, so it still has some meaning.
|
| 295256 |
04-Feb-2016 |
mmel |
ARM: Set UNAL_ENABLE bit in SCTLR CP15 register. This bit is RAO/SBOP
for ARMv7. For ARMv6, it controls ARMv5 compatible alignment support.
This bit have no effect until unaligned access is enabled.
|
| 295255 |
04-Feb-2016 |
skra |
Small rearrangement of abort_handler().
(1) Move cnt.v_trap increment to the beginning. There is cnt.v_vm_faults
counter in vm_fault(), so a number of hardware emulation aborts may be
get roughly as difference.
(2) Move kdb_reenter() up to not be ignored if pmap_fault() has failed.
(3) Update comments.
|
| 295254 |
04-Feb-2016 |
mmel |
ARM: RPI-B kernel was broken by r294740. Make it functional again.
|
| 295252 |
04-Feb-2016 |
mmel |
ARM: Don't use ugly (and hidden) global variable, control register is
readable at any time.
|
| 295251 |
04-Feb-2016 |
br |
Fix build.
|
| 295235 |
04-Feb-2016 |
mmel |
ARM: Remove unused symbols from genassym.c.
|
| 295213 |
03-Feb-2016 |
mmel |
ARM: Consistently use cpu_setttb() instead of setttb().
Remove unused #define for drain_writebuf.
|
| 295207 |
03-Feb-2016 |
mmel |
ARM: Replace only once used cpu_icache_sync_all() by ranged equivalent.
Remove it from cpu_functions table.
|
| 295206 |
03-Feb-2016 |
skra |
Partly revert r295168 and define PTE_DEVICE in pmap-v6.h header again.
It turned out that devmap.c is not only file in which PTE_DEVICE
is used and simultaneously, built for both armv4 and armv6 platforms.
When I tried to build all arm kernels before r295168 commit, it was
hid by some other local changes in my tree. I hope that this is just
temporary workaround before VM_MEMATTR_DEVICE could be used instead of
PTE_DEVICE outside of pmap code for __ARM_ARCH < 6.
|
| 295200 |
03-Feb-2016 |
mmel |
ARM: Remove support for xscale i80219 and i80321 CPUs. We haven't single
supported config/board with these CPUs.
|
| 295198 |
03-Feb-2016 |
mmel |
ARM: acle-compat.h is arm specific header, don't include it for aarch64. This
fixes aarch64 buildkernel.
|
| 295168 |
02-Feb-2016 |
skra |
Use pmap_preboot_map_attr() directly in arm_devmap_bootstrap()
instead of hiding behind pmap_map_chunk(). It's not longer needed
after old pmap-v6 code was removed.
For compatibility with __ARM_ARCH < 6, define PTE_DEVICE in devmap.c
file. Certainly, it would be nice if VM_MEMATTR_DEVICE could be used
even for __ARM_ARCH < 6.
|
| 295166 |
02-Feb-2016 |
skra |
Make pmap_preboot_map_attr() vm subsystem compliant, so its arguments
do not depend on pmap internals. This is a preparation for hiding
internal pmap definitions as much as possible from the rest of system.
Simultaneously, the protection argument evaluation is fixed. Happily,
it did not effect the mappings. And it's the reason why it was not fixed
earlier.
|
| 295149 |
02-Feb-2016 |
mmel |
ARM: All remaining functions in cpufunc_asm_arm10.S are identical with
functions in cpufunc_asm_arm9.S. Use arm9 variants and remove
cpufunc_asm_arm10.S completly.
|
| 295145 |
02-Feb-2016 |
mmel |
ARM: Remove last unused function, cpu_flush_prefetchbuf(),
from cpu_functions table.
|
| 295141 |
02-Feb-2016 |
skra |
Fix setting of protection bits for page table entries in pmap_map(). This
function is only called from vm_page_startup() and vm_reserv_startup().
I.e. during vm subsystem initialization. As VM_PROT_WRITE is always
used in these calls, the typo did not have any effect. Likely, it's
the reason why it wasn't discovered so long.
|
| 295128 |
01-Feb-2016 |
skra |
Remove not needed <machine/pte.h> includes.
|
| 295123 |
01-Feb-2016 |
mmel |
ARM: Rename remaining instances of cpufunc_id() to cpu_ident(),
forgotten in r295096.
Remove tlb_flushI/tlb_flushI_SE functions forgotten in r295122.
|
| 295122 |
01-Feb-2016 |
mmel |
ARM: Remove never used cpu_tlb_flushI and cpu_tlb_flushI_SE() functions
and their implementations.
|
| 295097 |
31-Jan-2016 |
mmel |
ARM: Fix END() symbol for cpu_ident function. I forgot to rename it
in r295096.
|
| 295096 |
31-Jan-2016 |
mmel |
ARM: cpufunc_domains, cpufunc_faultstatus and cpufunc_faultaddress
functions are equal for all ARM variants. Remove them from cpu_functions
table.
|
| 295095 |
31-Jan-2016 |
mmel |
ARM: Next round of cpufunc.* cleaning. Nobody uses flush_brnchtgt* functions,
delete them.
|
| 295092 |
31-Jan-2016 |
mmel |
ARM: First round of cpufunc.* cleaning. All abort_fixup functions are
not currently used or defined. Delete them.
|
| 295090 |
31-Jan-2016 |
mmel |
ARM: Convert spaces to tabs, fix formatting.
Not a functional change.
|
| 295089 |
31-Jan-2016 |
mmel |
ARM: Next round of cleanup in swtch-v*.S.
- remove now useless #if __ARM_ARCH conditional
- use macro for accessing CP15 registers
- remove unused PCPU_SIZE
Pointed by: kib
|
| 295073 |
30-Jan-2016 |
mmel |
ARM: Remove TLB IPI.
We don't support SMP on ARMv6. All ARMv7 multicore cpus already uses
hardware broadcast for TLB and cache operations.
|
| 295071 |
30-Jan-2016 |
mmel |
ARM: Cleanup mp_machdep.c. SMP is supported only on ARMv6 and later.
|
| 295068 |
30-Jan-2016 |
mmel |
ARM: Don't misuse ARM_TP_ADDRESS as ARMv4 / ARMv6 selector.
|
| 295066 |
30-Jan-2016 |
mmel |
ARM: Split swtch.S into common, ARMv4 and ARMv6 parts. Cleanup them.
|
| 295049 |
29-Jan-2016 |
skra |
Retire pmap_pte_init_mmu_v6() which was used by old pmap-v6.
|
| 295042 |
29-Jan-2016 |
skra |
Use kernel_pmap directly instead of pmap_kernel(). The kernel_pmap is
already used for __ARM_ARCH >= 6 and so even for __ARM_ARCH < 6 on some
common places.
|
| 295037 |
29-Jan-2016 |
mmel |
ARM: After removal of old pmap-v6 code, rename pmap-v6-new.c to pmap-v6.c.
|
| 295036 |
29-Jan-2016 |
mmel |
ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, and
dual implementation is showstopper for major cleanup.
This patch only removes old code from tree. Cleanups will follow asap.
|
| 294987 |
28-Jan-2016 |
zbb |
SMP support for ARMv6/v7 HW watchpoints
Use per-CPU structure to store HW watchpoints registers state
for each CPU present in the system. Those registers will be restored
upon wake up from the STOP state if requested by the debug_monitor
code. The method is similar to the one introduced to AMD64.
We store all possible 16 registers for HW watchpoints
(maximum allowed by the architecture).
HW breakpoints are not maintained since they are used for single
stepping only.
Pointed out by: kib
Reviewed by: wma
No strong objections from: kib
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4338
|
| 294930 |
27-Jan-2016 |
jhb |
Convert ss_sp in stack_t and sigstack to void *.
POSIX requires these members to be of type void * rather than the
char * inherited from 4BSD. NetBSD and OpenBSD both changed their
fields to void * back in 1998. No new build failures were reported
via an exp-run.
PR: 206503 (exp-run)
Reviewed by: kib
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D5092
|
| 294883 |
27-Jan-2016 |
jhibbits |
Convert rman to use rman_res_t instead of u_long
Summary:
Migrate to using the semi-opaque type rman_res_t to specify rman resources. For
now, this is still compatible with u_long.
This is step one in migrating rman to use uintmax_t for resources instead of
u_long.
Going forward, this could feasibly be used to specify architecture-specific
definitions of resource ranges, rather than baking a specific integer type into
the API.
This change has been broken out to facilitate MFC'ing drivers back to 10 without
breaking ABI.
Reviewed By: jhb
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D5075
|
| 294822 |
26-Jan-2016 |
skra |
Make pmap_fault() return values vm subsystem compliant to
simplify their handling in abort_handler(). While here,
remove one extra initialization of pcb variable.
|
| 294791 |
26-Jan-2016 |
skra |
Don't do icache sync on kernel memory and keep in line with comment
in elf_cpu_load_file(). The only time when the sync is needed is after
kernel module is loaded and the relocation info is processed. And it's
done in elf_cpu_load_file().
|
| 294789 |
26-Jan-2016 |
skra |
Make code more compact and readable better in pmap_extract()
like functions. No functional change.
This is a follow up to r294722.
Suggested by: kib
|
| 294754 |
25-Jan-2016 |
andrew |
Allow us to be told about memory past the first 4GB point, but ignore it.
This allows, for example, UEFI pass a memory map with some ram in this
region, but for us to ignore it. This is the case when running under the
qemu virt machine type.
Sponsored by: ABT Systems Ltd
|
| 294740 |
25-Jan-2016 |
zbb |
Introduce support for HW watchpoints and single stepping for ARMv6/v7
Allows for using hardware watchpoints for 1, 2, 4, 8 byte long addresses.
The default configuration of watchpoint is RW but code allows to select
RO or WO and X.
Since debugging registers are per-CPU (CP14) the watchpoint is set on
the CPU that was lucky (or not) to enter DDB.
HW breakpoints are used to perform single step in KDB.
When HW breakpoint is enabled all watchpoints are temporary disabled
to avoid recursive abort on both watchpoint and breakpoint.
In case of branch, the breakpoint is set to both - next instruction
and possible branch address. This requires at least 2 breakpoints
supported in the CPU however this is a must for ARMv6/v7 CPUs.
Reviewed by: imp
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4037
|
| 294727 |
25-Jan-2016 |
skra |
Fix an occasional undefined instruction abort during module loading.
Even if data cache maintenance was done by IO code, the relocation
fixup process creates dirty cache entries that we must write back
before doing icache sync.
Reported by: Thiagarajan Venkatasubramanian <tvenkata at juniper.net>
Reviewed by: ian
|
| 294724 |
25-Jan-2016 |
skra |
Do not use blk_write_cont() and remove it. There si no need to call
blk_flush() between two writes by physical address when these are
PAGE_SIZE aligned.
Fix some style nits.
|
| 294723 |
25-Jan-2016 |
skra |
Make minidump more like its i386 original back as with new pmap dump
interface all used physical addresses are PAGE_SIZE aligned.
Add missing copyright.
This is a follow up to r294722.
|
| 294722 |
25-Jan-2016 |
skra |
Create new pmap dump interface for minidump and use it for existing
pmap implementations on ARM. This way minidump code can be used without
any platform specific modification.
Also, this is the last piece missing for ARM_NEW_PMAP.
Differential Revision: https://reviews.freebsd.org/D5023
|
| 294422 |
20-Jan-2016 |
zbb |
Fix GIC FDT interrupts decoding
Interrupt type in FDT was interpreted incorrectly.
Patch taken from freebsd-arm thread 'GIC - interrupts interpretation in
DTS/FDT':
https://lists.freebsd.org/pipermail/freebsd-arm/2015-August/012145.html
Reviewed by: ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4215
|
| 294238 |
18-Jan-2016 |
andrew |
Add extra checks to make sure the size is valid. We may get an integer
underflow when we have small blocks of memory at the start and end of the
32-bit address range.
While here, only insert mappings pointing at a non-zero amount of memory.
Sponsored by: ABT Systems Ltd
|
| 294098 |
15-Jan-2016 |
skra |
Add mmu format info into ARM vmcore.
Fix kvatop translation for 64K pages.
Reviewed by: jhb
Approved by: kib (mentor)
Differential Revision: https://reviews.freebsd.org/D4942
|
| 293830 |
13-Jan-2016 |
ian |
Fix the spelling of fueword* to eliminate compile warnings about mismatched
begin/end symbols when the warning level is turned up.
Submitted by: Steve Kiernan <stevek@juniper.net>
|
| 293771 |
12-Jan-2016 |
skra |
Fix local macro for early KVA allocation.
Only crashdumpmap allocation was affected which is used for temporary
mappings during panic dump.
Approved by: kib (mentor)
|
| 293613 |
09-Jan-2016 |
dchagin |
Implement vsyscall hack. Prior to 2.13 glibc uses vsyscall
instead of vdso. An upcoming linux_base-c6 needs it.
Differential Revision: https://reviews.freebsd.org/D1090
Reviewed by: kib, trasz
MFC after: 1 week
|
| 293316 |
07-Jan-2016 |
skra |
Print curpmap in "show pcpu" command.
Approved by: kib (mentor)
|
| 293104 |
03-Jan-2016 |
ian |
Store the pointer to the bootloader-provided env data in a static var
for use in debug printing.
|
| 293065 |
02-Jan-2016 |
ian |
Reword the comment to better describe what I found while researching the
problem that led to this temporary workaround (and also so I can properly
cite the PR in the commit this time).
In general this is intended to be a temporary workaround until we can figure
out why including any ram from the last megabyte of the physical address
space leads to a NULL pointer deref. Debugging that is made trickier by the
fact that I couldn't even get a backtrace in ddb.
PR: 201614
|
| 293063 |
02-Jan-2016 |
ian |
Work around problems that happen when there is ram at the end of the
physical address space.
|
| 293061 |
02-Jan-2016 |
ian |
Use 64-bit math when processing the lists of physical and excluded memory
to generate the phys_avail and dump_avail arrays.
This is a partial fix for the kernel side of the problem mentioned in the
PR. This part handles the cases where comparing start and end addresses of
a block would fail because 32-bit wrap caused the end address to come out
zero if the end of the region is the end of the address space (0xffffffff
with 32-bit vm_paddr_t, but now the code should also work right if we ever
support LPAE with 36-bit addresses).
More work is necessary to make systems with ram at the end of the physical
address space usable, but at least initially it's going to be more like a
workaround than a fix, so this non-hacky part is being committed first.
PR: 201614
|
| 293045 |
02-Jan-2016 |
ian |
Make the 'env' directive described in config(5) work on all architectures,
providing compiled-in static environment data that is used instead of any
data passed in from a boot loader.
Previously 'env' worked only on i386 and arm xscale systems, because it
required the MD startup code to examine the global envmode variable and
decide whether to use static_env or an environment obtained from the boot
loader, and set the global kern_envp accordingly. Most startup code wasn't
doing so. Making things even more complex, some mips startup code uses an
alternate scheme that involves calling init_static_kenv() to pass an empty
buffer and its size, then uses a series of kern_setenv() calls to populate
that buffer.
Now all MD startup code calls init_static_kenv(), and that routine provides
a single point where envmode is checked and the decision is made whether to
use the compiled-in static_kenv or the values provided by the MD code.
The routine also continues to serve its original purpose for mips; if a
non-zero buffer size is passed the routine installs the empty buffer ready
to accept kern_setenv() values. Now if the size is zero, the provided buffer
full of existing env data is installed. A NULL pointer can be passed if the
boot loader provides no env data; this allows the static env to be installed
if envmode is set to do so.
Most of the work here is a near-mechanical change to call the init function
instead of directly setting kern_envp. A notable exception is in xen/pv.c;
that code was originally installing a buffer full of preformatted env data
along with its non-zero size (like mips code does), which would have allowed
kern_setenv() calls to wipe out the preformatted data. Now it passes a zero
for the size so that the buffer of data it installs is treated as
non-writeable.
|
| 292891 |
29-Dec-2015 |
ian |
Bring some of the recent locore-v4.S improvements into locore-V6...
- Map all 4GB as VA=PA so that args passed in from a bootloader can
be accessed regardless of where they are.
- Figure out the kernel load address by directly masking the PC rather
then by doing pc-relative math on the _start symbol.
- For EARLY_PRINTF support, map device memory as uncacheable (no-op for
ARM_NEW_PMAP because all TEX types resolve to uncacheable).
|
| 292730 |
25-Dec-2015 |
kevlo |
Fix typo (s/harware/hardware/)
|
| 292555 |
21-Dec-2015 |
ian |
Implement OF_decode_addr() for arm. Move most of powerpc's implementation
into a new function that other platforms can share.
This creates a new ofw_reg_to_paddr() function (in a new ofw_subr.c file)
that contains most of the existing ppc implementation, mostly unchanged.
The ppc code now calls the new MI code from the MD code, then creates a
ppc-specific bus_space mapping from the results. The new arm implementation
does the same in an arm-specific way.
This also moves the declaration of OF_decode_addr() from ofw_machdep.h to
openfirm.h, except on sparc64 which uses a different function signature.
This will help all FDT platforms to set up early console access using
OF_decode_addr().
|
| 292523 |
20-Dec-2015 |
ian |
Allow armv4/5 kernels to be loaded on any 2MB boundary, like armv6/7.
This eliminates the reliance on PHYSADDR and KERNPHYSADDR compile-time
symbols (except when the rom-copy code is enabled) by using the current
PC and the assumption that the entry-point routine is in the first 1MB
section of the text segment.
Other cleanups done:
- Reduce the initarm() stack size back to 2K. It got increased to
4 * 2K when this file was supporting multicore armv6, but that
support is now in locore-v6.S.
- When building the temporary startup page tables, map the entire
4GB address space as VA=PA before mapping the kernel at its loaded
location. This allows access to boot parameters stored somewhere
in ram by the bootloader, regardless of where that may be.
- When building the page table entry for supporting EARLY_PRINTF, map
the section as uncached unbuffered, since it is presumably device
registers.
Note that this restores the ability to use loader(8)/ubldr on armv4/5
kernels. That was broken in r283035, the point at which ubldr started
loading an arm kernel at any 2MB boundary.
Also note that after this, there is no reason to set KERNVIRTADDR to
anything other than 0xc0000000, and no need for PHYSADDR or KERNPHYSADDR
symbols at all.
|
| 292426 |
18-Dec-2015 |
adrian |
[intrng] Migrate the intrng code from sys/arm/arm to sys/kern/subr_intr.c.
The ci20 port (by kan@) is going to reuse almost all of the intrng code
since the SoC in question looks suspiciously like someone took an ARM
SoC design and replaced the ARM core with a MIPS core.
* migrate out the code;
* rename ARM_ -> INTR_;
* rename arm_ -> intr_;
* move the interrupt flush routine from intr.c / intrng.c into
arm/machdep_intr.c - removing the code duplication and removing
the ARM specific bits from here.
Thanks to the Star Wars: The Force Awakens premiere line for allowing
me a couple hours of quiet time to finish the universe builds.
Tested:
* make universe
TODO:
* The structure definitions in subr_intr.c still includes machine/intr.h
which requires one duplicates all of the intrng definitions in
the platform code (which kan has done, and I think we don't have to.)
Instead I should break out the generic things (function declarations,
common intr structures, etc) into a separate header.
* Kan has requested I make the PIC based IPI stuff optional.
|
| 292334 |
16-Dec-2015 |
skra |
Adopt assert from amd64 in pmap_remove_pages().
Suggested by: kib
Approved by: kib (mentor)
|
| 292276 |
15-Dec-2015 |
skra |
Local TLB flush is sufficient in pmap_remove_pages().
(1) The pmap argument passed to the function must be current pmap only.
(2) The process must be single threaded as the function is called either
when a process is exiting or from exec_new_vmspace().
Remove pmap_tlb_flush_ng() which is not used anywhere now.
Approved by: kib (mentor)
|
| 292269 |
15-Dec-2015 |
skra |
Replace all postponed TLB flushes by immediate ones except the one
in pmap_remove_pages().
Some points were considered:
(1) There is no range TLB flush cp15 function.
(2) There is no target selection for hardware TLB flush broadcasting.
(3) Some memory ranges could be mapped sparsely.
(4) Some memory ranges could be quite large.
Tested by buildworld on RPi2 and Jetson TK1, i.e. 4 core platforms.
It turned out that the buildworld time is faster. On the other hand,
when the postponed TLB flush was also removed from pmap_remove_pages(),
the result was worse. But pmap_remove_pages() is called for removing
all user mapping from a process, thus it's quite expected.
Note that the postponed TLB flushes came here from i386 pmap where
hardware TLB flush broadcasting is not available.
Approved by: kib (mentor)
|
| 292264 |
15-Dec-2015 |
skra |
Flush intermediate TLB cache when L2 page table is unlinked.
This fixes an issue observed on Cortex A7 (RPi2) and on Cortex A15
(Jetson TK1) causing various memory corruptions. It turned out that
even L2 page table with no valid mapping might be a subject of such
caching.
Note that not all platforms have intermediate TLB caching implemented.
An open question is if this fix is sufficient for all platforms with
this feature.
Approved by: kib (mentor)
|
| 292260 |
15-Dec-2015 |
mmel |
ARM: Remove outdated katelib.h.
Approved by: kib (mentor)
|
| 291961 |
07-Dec-2015 |
markj |
Add helper functions proc_readmem() and proc_writemem().
These helper functions can be used to read in or write a buffer from or to
an arbitrary process' address space. Without them, this can only be done
using proc_rwmem(), which requires the caller to fill out a uio. This is
onerous and results in code duplication; the new functions provide a simpler
interface which is sufficient for most existing callers of proc_rwmem().
This change also adds a manual page for proc_rwmem() and the new functions.
Reviewed by: jhb, kib
Differential Revision: https://reviews.freebsd.org/D4245
|
| 291937 |
07-Dec-2015 |
kib |
Add support for usermode (vdso-like) gettimeofday(2) and
clock_gettime(2) on ARMv7 and ARMv8 systems which have architectural
generic timer hardware. It is similar how the RDTSC timer is used in
userspace on x86.
Fix a permission problem where generic timer access from EL0 (or
userspace on v7) was not properly initialized on APs.
For ARMv7, mark the stack non-executable. The shared page is added for
all arms (including ARMv8 64bit), and the signal trampoline code is
moved to the page.
Reviewed by: andrew
Discussed with: emaste, mmel
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D4209
|
| 291852 |
05-Dec-2015 |
andrew |
Move the check to see if we are tracing a function with the DTrace Function
Boundary Trace to assembly to reduce the overhead of these checks.
Submitted by: Howard Su <howard0su@gmail.com>
Relnotes: Yes
Differential Revision: https://reviews.freebsd.org/D4266
|
| 291649 |
02-Dec-2015 |
mmel |
ARM: Fix of detection of root interrupt controller.
This fixes detection of root interrupt controller for cases,
when interrupt parent is not defined at all or it's not defined directly
in controller node.
Approved by: kib (mentor)
|
| 291492 |
30-Nov-2015 |
mmel |
ARM: create new memory attribute for writethrough cacheable memory.
- add new TEX class for WT cacheable memory
- export new TEX class to kernel as VM_MEMATTR_WT attribute
- add new aliases VM_MEMATTR_WRITE_COMBINING and
VM_MEMATTR_WRITE_BACK, it's used in DRM code
Note:
Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs,
WT requests is treated as uncacheable.
Approved by: kib (mentor)
|
| 291425 |
28-Nov-2015 |
mmel |
ARM: Add support for new KRAIT 300 CPU revision.
Approved by: kib (mentor)
|
| 291424 |
28-Nov-2015 |
mmel |
ARM: Cumulative fixes for GIC
- fix detection of interrupt root controller
- allow (but warn) unsupported configuration bits
- dont send EOI for spurious interrupts
- print more informations for spurious interrupts
- use device_printf() where appropriate
Reviewed by: ian (earlier version)
Approved by: kib (mentor)
|
| 291420 |
28-Nov-2015 |
kib |
Remove sv_prepsyscall, sv_sigsize and sv_sigtbl members of the struct
sysent.
sv_prepsyscall is unused.
sv_sigsize and sv_sigtbl translate signal number from the FreeBSD
namespace into the ABI domain. It is only utilized on i386 for iBCS2
binaries. The issue with this approach is that signals for iBCS2 were
delivered with the FreeBSD signal frame layout, which does not follow
iBCS2. The same note is true for any other potential user if
sv_sigtbl. In other words, if ABI needs signal number translation, it
really needs custom sv_sendsig method instead.
Sponsored by: The FreeBSD Foundation
|
| 291258 |
24-Nov-2015 |
skra |
Flush all kernel mappings from TLB(s) in time when they are cleared.
Replace tlb_flush_local() by tlb_flush() as even not global mappings
could be fetched to TLB(s) on other cores by speculative table walk.
From OS point of view, it was not a problem as either such mappings
were not used anymore or they were flushed from TLB(s) when reused.
However, from hardware point of view, it was a problem. Not flushed
mappings could be a target for speculative reads or prefetches (which
might be quite aggresive on ARM cores). As speculative read can fill
cacheline, it can cause a real problem, when physical page is reused,
but mapped with different memory attributes.
Anyhow, it's good to have only valid mappings in TLB(s).
Approved by: kib (mentor)
|
| 291216 |
23-Nov-2015 |
andrew |
Use #ifdef to get the file compiling without errors
|
| 291210 |
23-Nov-2015 |
andrew |
Only enable the first interrupt for now, we don't correctly configure or
route interrupts to the needed cpu.
Sponsored by: ABT Systems Ltd
|
| 291193 |
23-Nov-2015 |
skra |
Revert r291142.
The not quite consistent logic for bounce pages allocation is utilizited
by re(4) interface which can hang now.
Approved by: kib (mentor)
|
| 291153 |
22-Nov-2015 |
markj |
Remove unneeded includes of opt_kdtrace.h.
As of r258541, KDTRACE_HOOKS is defined in opt_global.h, so opt_kdtrace.h
is not needed when defining SDT(9) probes.
|
| 291142 |
21-Nov-2015 |
skra |
Fix BUS_DMA_MIN_ALLOC_COMP flag logic. When bus_dmamap_t map is being
created for bus_dma_tag_t tag, bounce pages should be allocated
only if needed.
Before the fix, they were allocated always if BUS_DMA_COULD_BOUNCE flag
was set but BUS_DMA_MIN_ALLOC_COMP not. As bounce pages are never freed,
it could cause memory exhaustion when a lot of such tags together with
their maps were created.
Note that there could be more maps in one tag by current design.
However BUS_DMA_MIN_ALLOC_COMP flag is tag's flag. It's set after
bounce pages are allocated. Thus, they are allocated only for first
tag's map which needs them.
Approved by: kib (mentor)
|
| 291131 |
21-Nov-2015 |
andrew |
Limit arm_base_bs_tag to ARMv4 and ARMv5, we only used it in one place in
armv6 and that can use fdtbus_bs_tag.
|
| 291094 |
20-Nov-2015 |
skra |
Add usermode variable to KTR output. Fix style.
Approved by: kib (mentor)
|
| 291093 |
20-Nov-2015 |
skra |
Fix style and argument count for KTR.
Approved by: kib (mentor)
|
| 291018 |
18-Nov-2015 |
mmel |
ARM: Fix dma_dcache_sync() for early allocated memory.
Drivers can request DMA to buffers that are not in memory represented
in the vm page arrays. Because of this, store KVA of already mapped
buffer to synclist and use it in dma_dcache_sync().
Reviewed by: jah
Approved by: kib (mentor)
Differential Revision: https://reviews.freebsd.org/D4120
|
| 290974 |
17-Nov-2015 |
andrew |
Make pl310_print_config static, it's not called out of pl310.c
Sponsored by: ABT Systems Ltd
|
| 290831 |
14-Nov-2015 |
gonzo |
Somewhat improve HDMI event API
- Pass device_t for HDMI framer as an argument for event hook
- Use #define for event values, instead of opaque (and unused) 0
|
| 290815 |
14-Nov-2015 |
gonzo |
hdmi_if.m will be reused by iMX6 IPU code so move it to arm/arm
|
| 290655 |
10-Nov-2015 |
skra |
Fix pmap_fault(). It turned out that alignment abort may have higher
priority than both translation and permission ones.
Approved by: kib (mentor)
|
| 290647 |
10-Nov-2015 |
mmel |
ARM: Improve robustness of locore_v6.S and fix errors.
- boot page table is not allocated in data section, so must be
cleared before use
- map only one section (1 MB) for SOCDEV mapping (*)
- DSB must be used for ensuring of finishing TLB operations
- Invalidate BTB when appropriate
PR: 198360
Reported by: Daisuke Aoyama <aoyama at peach.ne.jp> (*)
Approved by: kib (mentor)
|
| 290614 |
09-Nov-2015 |
bz |
Now that the PMU implementation is independent of HWPMC
as of r288992 use it to manage the CCNT.
Use the CNNT for get_cyclecount() instead of binuptime() when device pmu
is compiled in; if it fails to attach, fall back to the former method.
Enable by default for the BeagleBoneBlack configuration.
Optained from: Cambridge/L41
Sponsored by: DARPA/AFRL
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D3837
|
| 290541 |
08-Nov-2015 |
skra |
Make usermode variable the bool type. It's already used that way.
Suggested by: kib
Approved by: kib (mentor)
|
| 290472 |
06-Nov-2015 |
skra |
Set correct code for signal in abort_align() routine.
Remove superfluous printf() and both unnecessary and obsolete comments.
Approved by: kib (mentor)
|
| 290369 |
04-Nov-2015 |
skra |
Fix comment about unpriviledged instructions. Now, it matches with
current state after r289372.
While here, do some style and comment cleanups. No functional changes.
Approved by: kib (mentor)
|
| 290349 |
04-Nov-2015 |
gonzo |
Revert r290243, it's vaid "illegal instruction" case
DEX bit is set to 1 and exception raised whenever vectorized operation is
attempted on the VFP implementation that does not support it (i.e. on Cortex A7)
|
| 290309 |
02-Nov-2015 |
ian |
Eliminate the last dregs of the old global arm_root_dma_tag.
In the old days, device drivers passed NULL for the parent tag when creating
a new tag, and on arm platforms that resulted in a global tag representing
overall platform constraints being substituted in the busdma code. Now all
drivers use bus_get_dma_tag() and if there is a need to represent overall
platform constraints they will be inherited from a tag supplied by nexus or
some bus driver in the hierarchy.
The only arm platforms still relying on the old global-tag scheme were some
xscale boards with special PCI-bus constraints. This change provides those
constraints through a tag supplied by the xscale PCI bus driver, and
eliminates the few remaining references to the old global var.
Reviewed by: cognet
|
| 290273 |
02-Nov-2015 |
zbb |
Add support for branch instruction on armv7 with ptrace single step
Previous code supported only "continuous" code without any kind of
branch instructions. To change that, new function was implemented
which parses current instruction and returns an addres where
the jump might happen (alternative addr).
mdthread structure was extended to support two breakpoints
(one directly below current instruction and the second placed
at the alternative location).
One of them must trigger regardless the instruction has or has not been
executed due to condition field.
Upon cleanup, both software breakpoints are removed.
This implementation parses only the most common instructions
that are present in the code (like 99.99% of all), but there
is a chance there are some left, not covered by the parsing routine.
Parsing is done only for 32-bit instruction, no Thumb nor Thumb-2
support is provided.
Reviewed by: kib
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4021
|
| 290243 |
01-Nov-2015 |
gonzo |
Treat synchronous VFP exception just like aynchronous: as an FP exception,
not as illegal instruction
|
| 290167 |
29-Oct-2015 |
gonzo |
Fix LEAVE_HYP macro: spsr is not guaranteed to contain valid value at this
point, e.g. on RaspberryPi 2 when control is passed from loader to kernel
it contains garbage. So we use cpsr as a base for new cpsr value: if we
have reached this point it means current value is OK
Reviewed by: andrew
|
| 290120 |
28-Oct-2015 |
jah |
Retire pmap_dmap_iscurrent(). It is only a wrapper around pmap_is_current(), and is no longer called.
|
| 289893 |
24-Oct-2015 |
ian |
Define a couple macros to access cacheline size/mask in an arch-dependent
way. This code should now work for all arm versions v4 thru v7.
|
| 289887 |
24-Oct-2015 |
ian |
Rename dcache_dma_preread() to dcache_inv_poc_dma() to make it clear that it
is a dcache invalidate to point of coherency just like dcache_inv_poc(), but
a slightly different version specific to dma operations. Elaborate the
comment about how and why it's different.
|
| 289865 |
24-Oct-2015 |
ian |
A few more whitespace, style, and comment cleanups. No functional changes.
|
| 289864 |
24-Oct-2015 |
ian |
Bring in all the new(-ish) statistics code from armv6.
|
| 289862 |
24-Oct-2015 |
ian |
Change the preallocation of a busdma segment mapping array from per-tag to
per-map. The per-tag scheme is not safe, and a mutex can't be used to
protect it because the mapping routines can't sleep. Code brought in
from armv6 implementation.
|
| 289858 |
23-Oct-2015 |
ian |
Instead of all memory allocations using M_DEVBUF, use new categories
M_BUSDMA for allocations of metadata (tags, maps, segment tracking lists),
and M_BOUNCE for bounce pages.
|
| 289857 |
23-Oct-2015 |
ian |
Instead of all memory allocations using M_DEVBUF, use new categories
M_BUSDMA for allocations of metadata (tags, maps, segment tracking lists),
and M_BOUNCE for bounce pages.
|
| 289854 |
23-Oct-2015 |
ian |
Catch up to r232356: change the boundary constraint type to bus_addr_t.
This code lived in the projects/armv6 branch when that change got applied
to all the other arches.
|
| 289851 |
23-Oct-2015 |
ian |
Whitespace and style nits, no functional changes.
The goal is to make these two files cosmetically alike so that the actual
implementation differences are visible. The only changes which aren't
spaces<->tabs and rewrapping and reindenting lines are a couple fields
shuffled around in the tag and map structs so that everything is in the same
order in both versions (which should amount to no functional change).
|
| 289825 |
23-Oct-2015 |
jah |
Remove unclear comment about address truncation in busdma. Add (hopefully much clearer) comment at declaration of PHYS_TO_VM_PAGE().
Noted by: avg
|
| 289759 |
22-Oct-2015 |
jah |
Use pmap_quick* functions in armv6 busdma, for bounce buffers and cache maintenance. This makes it safe to sync buffers that have no VA mapping associated with the busdma map, but may have other mappings, possibly on different CPUs. This also makes it safe to sync unmapped bounce buffers in non-sleepable thread contexts.
Similar to r286787 for x86, this treats userspace buffers the same as unmapped buffers and no longer borrows the UVA for sync operations.
Submitted by: Svatopluk Kraus <onwahe@gmail.com> (earlier revision)
Tested by: Svatopluk Kraus
Differential Revision: https://reviews.freebsd.org/D3869
|
| 289698 |
21-Oct-2015 |
ian |
Move arm_gic_bind() out of the #ifdef SMP block to fix compile errors in
the not-SMP case. This is safe because arm_irq_next_cpu() will return
the cpuid of the current/only core in the not-SMP case.
Submitted by: Bartosz Szczepanek @ semihalf
|
| 289675 |
21-Oct-2015 |
jah |
Use pmap_quick* for out-of-context bounce buffers and (limited) cache maintenance of unmapped buffers in armv5 busdma.
Tested by: Mattia Rossi <mattia.rossi.mailinglists@gmail.com>
Differential Revision: https://reviews.freebsd.org/D3522
|
| 289631 |
20-Oct-2015 |
ian |
Uncomment some rather important code that was commented out for benchmarking.
Normally this routine is supposed to loop until the PIC returns a "no more
interrupts pending" indication. I had commented that out to do just one
interrupt per invokation to do some timing tests.
Spotted by: Svata Kraus
Pointy Hat: ian
|
| 289619 |
20-Oct-2015 |
ian |
Follow the advice of the misplaced comment and don't access the map struct
after freeing it. Remove the comment whose uselessness has been revealed.
|
| 289602 |
19-Oct-2015 |
ian |
Set the correct values in the arm aux control register, based on chip type.
The bits in the aux control register vary based on the processor type. In
the past we've always just set the 'smp' and "broadcast tlb/cache ops' bits,
which worked fine for the first few SoCs we supported. Now that we support
most of the cortex-a series processors, it's important to get the right bits
set based on the processor type.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
|
| 289548 |
18-Oct-2015 |
ian |
Only decode fdt data which belongs to the GIC controller.
The interrupts-extended property is a list of controller-specific
interrupt tuples for more than one controller. The decode routine of
every PIC gets called in the pre-INTRNG code (nexus doesn't know which
device instance belongs to which fdt node), so the GIC code has to
check each FDT node it is asked to decode to ensure it is the owner.
Because in the pre-INTRNG world there can only be one instance of a GIC,
it's safe to cache the results of a positive lookup in a static variable
to avoid the expensive lookups on subsequent calls.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
Differential Revision: https://reviews.freebsd.org/D2345
|
| 289529 |
18-Oct-2015 |
ian |
Import ARM_INTRNG, the "next generation" interrupt architecture for arm
and armv6 architecures. The primary enhancement over the old design is
support for hierarchical interrupt controllers (such as a gpio driver
which can receive interrupts from a root PIC and act as a PIC itself for
clients interested in handling a change of gpio pin state as an
interrupt). The new code also provides an infrastructure for mapping
interrupts described in metadata in the form of a "controller reference
plus interrupt number" tuple into the simple "0-n" flat numeric space
understood by rman and the bus resource mechanisms.
Use of the new code is enabled by setting the ARM_INTRNG option, and by
making a few simple changes to the platform's support code. In addition
each existing PIC driver needs changes to be ready for INTRNG; this commit
contains the changes for the arm/gic driver, which most armv6 SoCs use, but
it does not enable the new code yet on any platform.
This project has been many years in the making, starting as a GSoC project
by Jakub Klama (jceel@) in 2012. That didn't get committed right away and
the source base evolved out from under it to some degree. In 2014 I rebased
the diffs to then -current and did some enhancements in the area of mapping
interrupt numbers and storing associated fdt data, then the project went
cold again for a while. Eventually Svata Kraus took that work in progress
and did another big round of work on it, removing most of the remaining
rough edges. Finally I took that and made one more pass through it, mostly
disabling the "INTR_SOLO" feature for now, pending further design
discussions on how to most efficiently dispatch a pending interrupt through
more than one layer of PIC. The current code with the INTR_SOLO feature
disabled uses approximate 100 extra cpu cycles for each cascaded PIC the
interrupt has to be passed to, so what's left to do is about efficiency, not
correct operation.
Differential Revision: https://reviews.freebsd.org/D2047
|
| 289522 |
18-Oct-2015 |
ian |
Rename arm_init_secondary_ic() -> arm_pic_init_secondary(). The latter is
the name the function will have when the new ARM_INTRNG code is integrated,
and doing this rename first will make it easier to toggle the new interrupt
handling code on/off with a config option for debugging.
|
| 289372 |
15-Oct-2015 |
kib |
ARM userspace accessors, e.g. {s,f}uword(9), copy{in,out}(9),
casuword(9) and others, use LDRT and STRT instructions to access
memory with the privileges of userspace. If the *RT instruction
faults on the kernel address, then additional checks must be done to
not confuse the VM system with invalid kernel-mode faults.
Put ARM on line with other FreeBSD architectures and disallow usermode
buffers which intersect with the kernel address space in advance,
before any accesses are performed. In other words, vm_fault(9) is no
longer called when e.g. suword(9) stores to invalid (i.e. not
userspace) address.
Also, switch ARM to use fueword(9) and casueword(9).
Note: there is a pending patch in D3617, which adds the special
processing for faults from LDRT and STRT. The addition of the
processing is useful for potential other uses of the instructions and
for completeness, but standard userspace accessors are better served
by not allowing such faults beforehand.
Reviewed by: andrew
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3816
MFC after: 2 weeks
|
| 288983 |
07-Oct-2015 |
kib |
A follow-up to r288492. In fact, revert the mentioned commit for
pre-VFPv3 processors, since they do require software support code to
handle denormals. For VFPv3 and later, enable flush-to-zero if
hardware does not claim full denormals arithmetic support by VMVFR1_FZ
field in mvfr1 register.
The end result is that we do use correct fpu environment on Cortexes
with VFPv3, while ARM11 (e.g. rpi) is in non-compliant flush-to-zero
mode. At least CPUs without complete hardware implementation of
IEEE 754 do not cause unhandled floating point exception on underflow,
as it was before r288492.
Noted by: ian
Tested by: gjb
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
|
| 288662 |
04-Oct-2015 |
rwatson |
Add missing stack unwind information to several assembly functions on
ARMv6/7:
- Define _SAVE() macro to allow unwind data to be conditionally defined for
ARM assembly code in the kernel.
- Use _SAVE() to provide unwind information for bcopy_page(), and two (of
many) instances of copyin() and copyout().
Reviewed by: andrew, imp
MFC after: 3 days
Sponsored by: University of Cambridge
|
| 288492 |
02-Oct-2015 |
kib |
Do not set 'flush to zero' VFPSCR_FZ bit by default. The correct
implementation of IEEE 754 arithmetic depends on denormals operating
correctly. Both perl test suite and paranoia tripped over the
setting.
Reported by: Stefan Parvu <sparvu@kronometrix.org>
Discussed with: andrew
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
|
| 288256 |
26-Sep-2015 |
alc |
Exploit r288122 to address a cosmetic issue. Since PV chunk pages don't
belong to a vm object, they can't be paged out. Since they can't be paged
out, they are never enqueued in a paging queue. Nonetheless, passing
PQ_INACTIVE to vm_page_unwire() creates the appearance that these pages
are being enqueued in the inactive queue. As of r288122, we can avoid
this false impression by passing PQ_NONE.
Submitted by: kmacy (an earlier version)
Differential Revision: https://reviews.freebsd.org/D1674
|
| 288125 |
22-Sep-2015 |
andrew |
Add support for __atomic_FOO_fetch on arm prior to armv6. These return the
new value where the existing functions return the old value.
MFC after: 1 Week
|
| 288000 |
20-Sep-2015 |
kib |
Add support for weak symbols to the kernel linkers. It means that
linkers no longer raise an error when undefined weak symbols are
found, but relocate as if the symbol value was 0. Note that we do not
repeat the mistake of userspace dynamic linker of making the symbol
lookup prefer non-weak symbol definition over the weak one, if both
are available. In fact, kernel linker uses the first definition
found, and ignores duplicates.
Signature of the elf_lookup() and elf_obj_lookup() functions changed
to split result/error code and the symbol address returned.
Otherwise, it is impossible to return zero address as the symbol
value, to MD relocation code. This explains the mechanical changes in
elf_machdep.c sources.
The powerpc64 R_PPC_JMP_SLOT handler did not checked error from the
lookup() call, the patch leaves the code as is (untested).
Reported by: glebius
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
|
| 287645 |
11-Sep-2015 |
markj |
Add stack_save_td_running(), a function to trace the kernel stack of a
running thread.
It is currently implemented only on amd64 and i386; on these
architectures, it is implemented by raising an NMI on the CPU on which
the target thread is currently running. Unlike stack_save_td(), it may
fail, for example if the thread is running in user mode.
This change also modifies the kern.proc.kstack sysctl to use this function,
so that stacks of running threads are shown in the output of "procstat -kk".
This is handy for debugging threads that are stuck in a busy loop.
Reviewed by: bdrewery, jhb, kib
Sponsored by: EMC / Isilon Storage Division
Differential Revision: https://reviews.freebsd.org/D3256
|
| 287625 |
10-Sep-2015 |
kib |
Do not hold the process around the vm_fault() call from the trap()s.
The only operation which is prevented by the hold is the kernel stack
swapout for the faulted thread, which should be fine to allow.
Remove useless checks for NULL curproc or curproc->p_vmspace from the
trap_pfault() wrappers on x86 and powerpc.
Reviewed by: alc (previous version)
Sponsored by: The FreeBSD Foundation
MFC after: 2 weeks
|
| 287322 |
31-Aug-2015 |
andrew |
Clean up the style of the LEAVE_HYP macro.
|
| 287127 |
25-Aug-2015 |
zbb |
Leave hypervisor mode upon startup on ARMv7
If ARMv7 boots in HYP mode, switch to SVC32.
Reviewed by: ian
Submitted by: Wojciech Macek <wma@semihalf.com>
Jakub Palider <jpa@semihalf.com>
Obtained from: Semihalf
Sponsored by: Annapurna Labs
Differential Revision: https://reviews.freebsd.org/D1810
|
| 287000 |
21-Aug-2015 |
royger |
preload_search_info: make sure mod is set
Add a check to preload_search_info to make sure mod is set. Most of the
callers of preload_search_info don't check that the mod parameter is
set, which can cause page faults. While at it, remove some now unnecessary
checks before calling preload_search_info.
Sponsored by: Citrix Systems R&D
Reviewed by: kib
Differential Revision: https://reviews.freebsd.org/D3440
|
| 286969 |
20-Aug-2015 |
ian |
Remove code left over from the armv4 days. On armv4, cache maintenance
operations always had to be aligned and sized to cache lines. On armv6
and later, cache maintenance operates on a cache line if any part of
the line is referenced in the operation, so we don't need extra code to
align the edges of the sync range.
|
| 286968 |
20-Aug-2015 |
ian |
Minor comment and style fixes, no functional change.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
|
| 286851 |
17-Aug-2015 |
jah |
Some cleanups to make the style of pmap_quick_enter_page() and pmap_quick_remove_page() in arm/pmap-v6-new.c more consistent with the rest of the file.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
Approved by: kib (mentor)
|
| 286726 |
13-Aug-2015 |
marcel |
Instead of having separate do_sync functions for ARM_ARCH 6 vs.
ARM_ARCH >= 7, use the dmb() macro defined in machine/atomic.h
Submitted by: Steve Kiernan <stevek@juniper.net>
Reviewed by: imp@
Differential Revision: https://reviews.freebsd.org/D3355
|
| 286725 |
13-Aug-2015 |
marcel |
The Broadcom BCM56060 chip has a Cortex-A9R4 core.
Submitted by: Steve Kiernan <stevek@juniper.net>
Reviewed by: imp@
Differential Revision: https://reviews.freebsd.org/D3357
|
| 286584 |
10-Aug-2015 |
kib |
Make kstack_pages a tunable on arm, x86, and powepc. On i386, the
initial thread stack is not adjusted by the tunable, the stack is
allocated too early to get access to the kernel environment. See
TD0_KSTACK_PAGES for the thread0 stack sizing on i386.
The tunable was tested on x86 only. From the visual inspection, it
seems that it might work on arm and powerpc. The arm
USPACE_SVC_STACK_TOP and powerpc USPACE macros seems to be already
incorrect for the threads with non-default kstack size. I only
changed the macros to use variable instead of constant, since I cannot
test.
On arm64, mips and sparc64, some static data structures are sized by
KSTACK_PAGES, so the tunable is disabled.
Sponsored by: The FreeBSD Foundation
MFC after: 2 week
|
| 286296 |
04-Aug-2015 |
jah |
Add two new pmap functions:
vm_offset_t pmap_quick_enter_page(vm_page_t m)
void pmap_quick_remove_page(vm_offset_t kva)
These will create and destroy a temporary, CPU-local KVA mapping of a specified page.
Guarantees:
--Will not sleep and will not fail.
--Safe to call under a non-sleepable lock or from an ithread
Restrictions:
--Not guaranteed to be safe to call from an interrupt filter or under a spin mutex on all platforms
--Current implementation does not guarantee more than one page of mapping space across all platforms. MI code should not make nested calls to pmap_quick_enter_page.
--MI code should not perform locking while holding onto a mapping created by pmap_quick_enter_page
The idea is to use this in busdma, for bounce buffer copies as well as virtually-indexed cache maintenance on mips and arm.
NOTE: the non-i386, non-amd64 implementations of these functions still need review and testing.
Reviewed by: kib
Approved by: kib (mentor)
Differential Revision: http://reviews.freebsd.org/D3013
|
| 286040 |
29-Jul-2015 |
sbruno |
Remove dead functions pmap_pvdump and pads.
Differential Revision: D3206
Submitted by: kevin.bowling@kev009.com
Reviewed by: alc
|
| 285627 |
16-Jul-2015 |
zbb |
Fix KSTACK_PAGES issue when the default value was changed in KERNCONF
If KSTACK_PAGES was changed to anything alse than the default,
the value from param.h was taken instead in some places and
the value from KENRCONF in some others. This resulted in
inconsistency which caused corruption in SMP envorinment.
Ensure all places where KSTACK_PAGES are used the opt_kstack_pages.h
is included.
The file opt_kstack_pages.h could not be included in param.h
because was breaking the toolchain compilation.
Reviewed by: kib
Obtained from: Semihalf
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3094
|
| 285389 |
11-Jul-2015 |
andrew |
Always send a SIGSEGV on a map failure. Use the code to tell the reason
for the signal.
Sponsored by: ABT Systems Ltd
|
| 284871 |
26-Jun-2015 |
andrew |
pc_curpmap is only in the armv6 pcpu data.
|
| 284771 |
24-Jun-2015 |
ian |
Fix a misplaced #endif (maybe a mismerge?). Emitting the symbol for CURPMAP
is not dependent on whether VFP (hardware floating point) is enabled.
|
| 284452 |
16-Jun-2015 |
andrew |
Write to the PRRR (Primary Region Remap Register) rather than reading from
it during the early boot.
Found By: Patrick Wildt <patrick@bitrig.org>
Sponsored by: ABT Systems Ltd
|
| 284449 |
16-Jun-2015 |
bz |
Trying to unbreak arm.LINT by properly putting the conditional include
for dtrace further down in the include list where it belongs.
Reviewed by: andrew
|
| 284273 |
11-Jun-2015 |
andrew |
Add basic support for ACPI. It splits out the nexus driver to two new
drivers, one for fdt, one for acpi. It then uses this to decide if it will
use fdt or acpi.
The GICv2 (interrupt controller) and Generic Timer drivers have been
updated to handle both cases.
As this is early code we still need FDT to find the kernel console, and
some parts are still missing, including PCI support.
Differential Revision: https://reviews.freebsd.org/D2463
Reviewed by: jhb, jkim, emaste
Obtained from: ABT Systems Ltd
Relnotes: Yes
Sponsored by: The FreeBSD Foundation
|
| 284264 |
11-Jun-2015 |
andrew |
Fix the spelling of __ARM_ARCH >= 6 in sys/arm/arm.
|
| 284214 |
10-Jun-2015 |
mjg |
Generalised support for copy-on-write structures shared by threads.
Thread credentials are maintained as follows: each thread has a pointer to
creds and a reference on them. The pointer is compared with proc's creds on
userspace<->kernel boundary and updated if needed.
This patch introduces a counter which can be compared instead, so that more
structures can use this scheme without adding more comparisons on the boundary.
|
| 284181 |
09-Jun-2015 |
alc |
Account for superpage mappings that are created by pmap_copy().
|
| 284115 |
07-Jun-2015 |
andrew |
Stop checking for ARM_TP_ADDRESS when we mean to check if building for
ARMv6 or later.
|
| 284109 |
07-Jun-2015 |
andrew |
Remove pc_cpu, it was duplicating pc_cpuid so was unneeded.
|
| 283947 |
03-Jun-2015 |
ian |
Better handling of userland sysarch() requests to flush icache.
On armv6, cache maintenance can trigger page faults. Add handling so that
these turn into SIGSEGV that kills the process rather than panics that kill
the kernel.
Differential Revision: https://reviews.freebsd.org/D2035
Submitted by: Michal Meloun <meloun@miracle.cz>
|
| 283888 |
01-Jun-2015 |
andrew |
Remove __ARM_EABI__ from sys/arm/arm, building for oabi is unsupported.
|
| 283887 |
01-Jun-2015 |
andrew |
Clear the C bit of the saved program state register when also clearing the
return value. We use this bit to signal when a syscall has failed, and
without this getcontext/setcontext may fail.
MFC after: 1 week
|
| 283839 |
31-May-2015 |
andrew |
Set the return value correctly on copy failure in copystr.
MFC after: 1 week
|
| 283479 |
24-May-2015 |
dchagin |
The kernel sends signals to the processes via ABI specific sv_sendsig method.
Native ABI do not need signal conversion, only emulators may want this. Usually
emulators implements its own sv_sendsig method. For now only ibcs2 emulator does
not have own sv_sendsig implementation and depends on native sendsig() method.
So, remove any extra attempts to convert signal numbers from native sendsig()
methods except from i386 where ibsc2 is living.
|
| 283426 |
24-May-2015 |
andrew |
Add support for getting the memory map from EFI if it has been pased in
by loader.efi.
|
| 283382 |
24-May-2015 |
dchagin |
In preparation for switching linuxulator to the use the native 1:1
threads add a hook for cleaning thread resources before the thread die.
Differential Revision: https://reviews.freebsd.org/D1038
|
| 283366 |
24-May-2015 |
andrew |
Remove trailing whitespace from sys/arm/arm
|
| 283365 |
24-May-2015 |
andrew |
Add more cp15_ functions, and use them in cpufunc.c where possible.
|
| 283337 |
23-May-2015 |
andrew |
Fix a lock up where we enter swapper() with interrupts disabled.
In smp_rendezvous_cpus we expect to wait for all cpus to enter
smp_rendezvous_action. If we call this holding a proc lock swapper may
attempt to also lock it, however as interrupts are disabled the cpu never
handles the ipi. Because smp_rendezvous_action waits for all signaled
cpus before contining it may get caught waiting for the cpu running swapper
as the proc mutex will be unlocked after smp_rendezvous_cpus finishes.
The fix is to enable interrupts in the configure stage as we should be
doing.
MFC after: 1 week
|
| 283331 |
23-May-2015 |
andrew |
Use the wait-for-event instruction to put the core we have just enabled
to sleep while it waits to start scheduling. The boot core can then use
the send-event instruction to wake the cores when they should enter the
scheduler.
MFC after: 1 week
|
| 283248 |
21-May-2015 |
pfg |
ddb: finish converting boolean values.
The replacement started at r283088 was necessarily incomplete without
replacing boolean_t with bool. This also involved cleaning some type
mismatches and ansifying old C function declarations.
Pointed out by: bde
Discussed with: bde, ian, jhb
|
| 283126 |
19-May-2015 |
imp |
Improve comment about unmapped I/O and fix typos.
Submitted by: Matteo Riondato
MFC After: 2 days
|
| 283112 |
19-May-2015 |
br |
Add Performance Monitoring Counters support for AArch64.
Family-common and CPU-specific counters implemented.
Supported CPUs: ARM Cortex A53/57/72.
Reviewed by: andrew, bz, emaste, gnn, jhb
Sponsored by: ARM Limited
Differential Revision: https://reviews.freebsd.org/D2555
|
| 283033 |
17-May-2015 |
ian |
Do not set preload_addr_relocate for ARM. Apparently there was a time
when loader(8) passed physical addresses in loader metadata for arm, but
that is no longer true; all metadata has already been adjusted to vitual
addresses by loader.
I can't track down the exact revision in loader where a change from physical
to virtual metadata addresses happened. The code involved is very twisty
and complicated. I suspect the change was an unintended consequence of the
r247301, r247413, r248118 series of changes I made a couple years ago.
|
| 283014 |
16-May-2015 |
imp |
Don't allow unmapped I/O. The pmap isn't quite up to the task. Add a
comment to this effect and switch the default. My old AT91SAM9G20
now boots, fsck's the SD card and runs w/o an issue for the first
time since a 9.1-ish stable build I did a few years ago.
Problems with unmapped I/O:
o un-page-aligned I/O requests to devices fail (notably fsck
and newfs).
o write-back caching was totally broken. write-through caching
needed to be enabled.
o Even page-aligned I/O requests sometimes failed for reasons
not thoroughly investigated.
Suggested by: ian@
MFC after: 2 days
|
| 282983 |
15-May-2015 |
ian |
Retrieve the cache parms in the proper arch-specific way.
Submitted by: Michal Meloun <meloun@miracle.cz>
|
| 282934 |
15-May-2015 |
ganbold |
It appears to be armv7_sleep is a duplication of armv7_cpu_sleep.
For consistency with the naming conventions used by the other
implementations kill armv7_sleep and keep armv7_cpu_sleep.
Differential Revision: https://reviews.freebsd.org/D2537
Submitted by: John Wehle
Reviewed by: ian@, andrew@
|
| 282830 |
13-May-2015 |
ganbold |
Delete cpu_do_powersave which is set but never used/tested
serving no useful purpose.
Differential Revision: https://reviews.freebsd.org/D2516
Submitted by: John Wehle
Reviewed by: ian@
|
| 282829 |
13-May-2015 |
loos |
Fix the vmstat -i output on ARM.
The consumers of hw.intrnames expect a NULL byte at end of the string
containing the interrupt names.
On ARM all the interrupt name slots are initialized and this leave no room
for the terminating NULL byte, which makes vmstat read beyond the end of
intrnames.
PR: 199891
Tested on: RPi 2 and BeagleBone Black
|
| 282780 |
11-May-2015 |
alc |
Retire pmap_lazyfix(). This function only existed in the new armv6 pmap
because the i386 pmap on which the new armv6 pmap is based had it, and in
r281707 pmap_lazyfix() was removed from the i386 pmap.
Discussed with: kib
Submitted by: Michal Meloun (via Svatopluk Kraus)
|
| 282779 |
11-May-2015 |
andrew |
Add the kernel support for Thumb-2. It is only supported on ARMv7 as the
main ARMv6 target, the Raspberry Pi, doesn't support Thumb-2.
This as been tested with a Thumb-2 userland, however building one is
currently unsupported as there are known toolchain issues breaking some
binaries. Further work will also be needed to decide on the method of
selecting which instruction set to build for, and to benchmark both to
find how building everything as Thumb-2 will affect performance.
Relnotes: yes
|
| 282763 |
11-May-2015 |
andrew |
Move to use __ARM_ARCH in more places in the kernel.
|
| 282762 |
11-May-2015 |
andrew |
Use the ACLE spelling of _ARM_ARCH_6: "__ARM_ARCH >= 6"
|
| 282547 |
06-May-2015 |
zbb |
Add new CP15 operations and DB_SHOW_COMMAND to print CP15 registers
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: imp, Michal Meloun <meloun@miracle.cz>
Obtained from: Semihalf
|
| 282483 |
05-May-2015 |
andrew |
Update the comment on what CPUs this driver supports.
|
| 282418 |
04-May-2015 |
ian |
On an icache sync by address/len, round the length up if the operation spans
a cacheline boundary.
PR: 199740
Submitted by: Juergen Weiss <weiss@uni-mainz.de>
|
| 282352 |
02-May-2015 |
loos |
Remove an unused variable.
|
| 282334 |
02-May-2015 |
imp |
Remove support for being compiled under OABI. We don't support that
any more, so this is just dead code.
Differential Revision: https://reviews.freebsd.org/D2419
|
| 282151 |
28-Apr-2015 |
andrew |
Fix pmap_dcache_wb_pou in the new armv6 pmap to correctly achieve icache
consistency from ptrace.
PR: 199739
Submitted by: Jurgen Weiss <weiss at uni-mainz.de> (original version)
Submitted by: Svatopluk Kraus <onwahe at gmail.com>
|
| 282120 |
28-Apr-2015 |
hselasky |
The add_bounce_page() function can be called when loading physical
pages which pass a NULL virtual address. If the BUS_DMA_KEEP_PG_OFFSET
flag is set, use the physical address to compute the page offset
instead. The physical address should always be valid when adding
bounce pages and should contain the same page offset like the virtual
address.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
MFC after: 1 week
Reviewed by: jhb@
|
| 282025 |
26-Apr-2015 |
andrew |
Cleanup a little more:
- Remove whitespace at the end of lines
- Use a tab after instructions, not spaces
|
| 282024 |
26-Apr-2015 |
andrew |
Fix the style of locore-v4.S and locore-v6.S to help find any common code.
|
| 282023 |
26-Apr-2015 |
andrew |
Remove the armv6 code from locore-v4.S, it's not needed there.
|
| 282019 |
26-Apr-2015 |
andrew |
Use ARMv7 style unaligned access on ARMv6. We set this bit in locore, but
it was missing from here.
|
| 281648 |
17-Apr-2015 |
andrew |
Remove support for reading the syscall code in OABI. This is unneeded now
we can only build for EABI.
|
| 281647 |
17-Apr-2015 |
andrew |
Use cp15_ifar_get to get the instruction fault address. When using Thumb-2
the instruction may be over two pages so the program counter could point
to the wrong page.
|
| 281493 |
13-Apr-2015 |
andrew |
Update the arm devmap code to also work with arm64.
There are a few differences between the two. On arm we need to provide a
list of addresses we may be mapping before we have initialised the virtual
memory subsystem, however on arm64 we allocate a small (2MiB for a 4k
granule) range to be used for such purposes.
Differential Revision: https://reviews.freebsd.org/D2249
Sponsored by: The FreeBSD Foundation
|
| 281369 |
10-Apr-2015 |
ian |
Add a pmap_kremove_device() to undo mappings made with pmap_kenter_device().
Previously we used pmap_kremove(), but with ARM_NEW_PMAP it does the remove
in a way that isn't SMP-coherent (which is appropriate in some circumstances
such as mapping/unmapping sf buffers). With matching enter/remove routines
for device mappings, each low-level implementation can do the right thing.
Reviewed by: Svatopluk Kraus <onwahe@gmail.com>
|
| 281089 |
04-Apr-2015 |
andrew |
Don't include unneeded files in the arm machine/fdt.h. While here, remove
it from more files.
|
| 281072 |
04-Apr-2015 |
andrew |
Add support for arm64 to the existing arm generic timer driver:
- Add macros to handle the differences in accessing these registers on arm
and arm64.
- Use the fdt data to detect if we are on an ARMv7 or ARMv8.
- Use the virtual timer by default on arm64, we may not have access to
the physical timer.
Differential Revision: https://reviews.freebsd.org/D2208
Reviewed by: emaste
Sponsored by: The FreeBSD Foundation
|
| 280987 |
02-Apr-2015 |
andrew |
Stop including machine/fdt.h, it's not needed.
Sponsored by: The FreeBSD Foundation
|
| 280986 |
02-Apr-2015 |
andrew |
We may not be using gcc to compile this.
Sponsored by: The FreeBSD Foundation
|
| 280985 |
02-Apr-2015 |
andrew |
Add the generic timer registers to sysreg.h and cpu-v6.h, and use the
access functions in the generic timer driver.
Differential Revision: https://reviews.freebsd.org/D2198
Sponsored by: The FreeBSD Foundation
|
| 280979 |
02-Apr-2015 |
gonzo |
- Make interrupt resource optional: some upstream FDT blobs (e.g. TI's) do
not have interupt property in pl310 node. Interrupt is used only to
detect cache activity when L2 cache is disabled, it's not vital for
normal operations.
- Fix intrhook allocation/initialization
|
| 280905 |
31-Mar-2015 |
ganbold |
Add necessary changes to support various Amlogic SoC devices
specially aml8726-m6 and aml8726-m8b SoC based devices.
aml8726-m6 SoC exist in devices such as Visson ATV-102.
Hardkernel ODROID-C1 board has aml8726-m8b SoC.
The following support is included:
Basic machdep code
SMP
Interrupt controller
Clock control driver (aka gate)
Pinctrl
Timer
Real time clock
UART
GPIO
I2C
SD controller
SDXC controller
USB
Watchdog
Random number generator
PLL / Clock frequency measurement
Frame buffer
Submitted by: John Wehle
Approved by: stas (mentor)
|
| 280868 |
30-Mar-2015 |
andrew |
Restore setting cpufuncs on arm1176, it was removed by accident with the
arm1136 code.
Reviewed by: ian
|
| 280847 |
30-Mar-2015 |
andrew |
Remove support for CPU_XSCALE_80200. None of our configs support it, and
there wasn;t an option to enable it.
While here remove a check for CPU_ARM10 being defined as it has also been
removed.
|
| 280842 |
30-Mar-2015 |
andrew |
Remove support for CPU_FA626TE. It's unused by any of our kernel configs.
|
| 280833 |
29-Mar-2015 |
andrew |
arm11_sleep is no longer needed, remove it.
|
| 280824 |
29-Mar-2015 |
andrew |
Remove arm1136 support. We don't have any configs that use it, and I don't
expect us to add support for any more arm11 SoCs.
|
| 280823 |
29-Mar-2015 |
andrew |
Remove the bootconfig parsing. We never used it and always passed either an
empty string or NULL to the setup functions that called into it.
|
| 280817 |
29-Mar-2015 |
andrew |
Remove ARM9_CACHE_WRITE_THROUGH, none of our configs define it.
|
| 280815 |
29-Mar-2015 |
andrew |
Remove the unused armv5 cpufunc code.
|
| 280813 |
29-Mar-2015 |
andrew |
Remove unused cpufunc arm11 and armv6 code. While here only define the
remaining functions in the context we use them in.
|
| 280811 |
29-Mar-2015 |
andrew |
Remove unused arm10_* functions. The remaining functions are only used in
mv configs.
|
| 280809 |
29-Mar-2015 |
andrew |
Remove support for CPU_ARM10. No kernel configs could possibly use this as
it's not an available option. Along with this we will never support this
cpu type as very few arm10 chips were made.
|
| 280712 |
26-Mar-2015 |
ian |
New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it.
This is pretty much a complete rewrite based on the existing i386 code. The
patches have been circulating for a couple years and have been looked at by
plenty of people, but I'm not putting anybody on the hook as having reviewed
this in any formal sense except myself.
After this has gotten wider testing from the user community, ARM_NEW_PMAP
will become the default and various dregs of the old pmap code will be
removed.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>
|
| 280402 |
23-Mar-2015 |
ian |
Do not save/restore the TLS pointer on context switch for armv6. The
pointer cannot be changed directly by userland code on armv6 (it can be on
armv4), so there's no need to save/restore.
Submitted by: Michal Meloun
|
| 280324 |
21-Mar-2015 |
cognet |
When waiting on PTE allocation, another thread could free the l2_dtable while
we're not looking at it.
Fix this by increasing l2->l2_occupancy before we try to alloc (and decrease
it if the allocation failed, or if another thread did a similar allocation).
Submitted by: Kohji Okuno <okuno.kohji@jp.panasonic.com>
MFC after: 1 week
|
| 279811 |
09-Mar-2015 |
ian |
Add minimum cache line sizes to struct cpuinfo, use them in the new cache
maintenance routines. Also add a routine to invalidate the branch cache.
Submitted by: Michal Meloun
|
| 279810 |
09-Mar-2015 |
ian |
Clean data cache before instruction cache in armv7_icache_sync_range().
Also ensure dsb precedes isb in all icache maintenance routines (first
do a data sync, then stall the instruction stream until it finishes).
Submitted by: Michal Meloun
|
| 279702 |
06-Mar-2015 |
ian |
Update a comment that had drifted out of date with the last changes.
|
| 279667 |
05-Mar-2015 |
andrew |
Add the MD parts of dtrace needed to use fbt on ARM. For this we need to
emulate the instructions used in function entry and exit.
For function entry ARM will use a push instruction to push up to 16
registers to the stack. While we don't expect all 16 to be used we need to
handle any combination the compiler may generate, even if it doesn't make
sense (e.g. pushing the program counter).
On function return we will either have a pop or branch instruction. The
former is similar to the push instruction, but with care to make sure we
update the stack pointer and program counter correctly in the cases they
are either in the list of registers or not. For branch we need to take the
24-bit offset, sign-extend it, and add that number of 4-byte words to the
program counter. Care needs to be taken as, due to historical reasons, the
address the branch is relative to is not the current instruction, but 8
bytes later.
This allows us to use the following probes on ARM boards:
dtrace -n 'fbt::malloc:entry { stack() }'
and
dtrace -n 'fbt::free:return { stack() }'
Differential Revision: https://reviews.freebsd.org/D2007
Reviewed by: gnn, rpaulo
Sponsored by: ABT Systems Ltd
|
| 279312 |
26-Feb-2015 |
dim |
Fix a number of -Wcast-qual warnings under sys/arm. No functional
change.
Submitted by: andrew
MFC after: 3 days
|
| 279235 |
24-Feb-2015 |
zbb |
Fix endianness on FDT read in ARM GIC
Submitted by: Jakub Palider <jpa@semihalf.com>
Reviewed by: ian, nwhitehorn
Obtained from: Semihalf
|
| 279215 |
23-Feb-2015 |
ian |
There is no reason to do i+dcache writeback and invalidate when changing
the translation table (this may be left over from armv5 days). It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.
Submitted by: Michal Meloun
|
| 278996 |
19-Feb-2015 |
andrew |
Allow the ARM unwinder to work through modules. This will be used to add
support for unwinding from dtrace.
Tested by: gnn (with dtrace)
Sponsored by: ABT Systems Ltd
|
| 278895 |
17-Feb-2015 |
andrew |
Pull the ARM ddb unwind code out to a new file. This will allow it to be
used by other places that expect to unwind the stack, e.g. dtrace and
stack(9).
As I have written most of this code I'm changing the license to the
standard FreeBSD license. I have received approval from the other
developers who have changed any of the affected code.
Approved by: ian, imp, rpaulo, eadler (all license change)
|
| 278770 |
14-Feb-2015 |
ian |
Add logic for handling new-style ARM cpu ID info.
Submitted by: Michal Meloun <meloun@miracle.cz>
|
| 278578 |
11-Feb-2015 |
andrew |
Remove the non-EABI code from the DDB stack unwinder, we only support the
ARM EABI now.
|
| 278529 |
10-Feb-2015 |
gnn |
Initial version of DTrace on ARM32.
Submitted by: Howard Su based on work by Oleksandr Tymoshenko
Reviewed by: ian, andrew, rpaulo, markj
|
| 278518 |
10-Feb-2015 |
zbb |
Resolve cache line size from CP15
Switch the cache line size during invalidations/flushes
to be read from CP15 cache type register.
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: ian, imp
Obtained from: Semihalf
|
| 278031 |
01-Feb-2015 |
ian |
Remove a stale comment. The logic that deleted the map before other
resources was removed long ago, but the comment stuck somehow.
|
| 278001 |
31-Jan-2015 |
kib |
Do not qualify the mcontext_t *mcp argument for set_mcontext(9) as
const. On x86, even after the machine context is supposedly read into
the struct ucontext, lazy FPU state save code might only mark the FPU
data as hardware-owned. Later, set_fpcontext() needs to fetch the
state from hardware, modifying the *mcp.
The set_mcontext(9) is called from sigreturn(2) and setcontext(2)
implementations and old create_thread(2) interface, which throw the
*mcp out after the set_mcontext() call.
Reported by: dim
Discussed with: jhb
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
|
| 277835 |
28-Jan-2015 |
br |
Add ARMv7 performance monitoring counters.
Differential Revision: https://reviews.freebsd.org/D1687
Reviewed by: rpaulo
Sponsored by: DARPA, AFRL
|
| 277745 |
26-Jan-2015 |
br |
Add a generic way for hooking PMC interrupt.
|
| 277743 |
26-Jan-2015 |
kib |
Ensure that _tmppt KVA is used exclusively by providing exclusive sx
lock around the mapping and uiomove(). Before r277643, it was
partially protected by Giant (but potential sleeping in fault from
uiomove() would still allow other thread to reuse the mapping).
Noted by: ian
Reviewed by: alc, ian
Sponsored by: The FreeBSD Foundation
MFC after: 3 weeks
|
| 277643 |
24-Jan-2015 |
kib |
Remove Giant from /dev/mem and /dev/kmem. It is definitely not needed
for i386, and from the code inspection, nothing in the
arm/mips/sparc64 implementations depends on it.
Discussed with: imp, nwhitehorn
Sponsored by: The FreeBSD Foundation
MFC after: 3 weeks
|
| 277532 |
22-Jan-2015 |
ian |
Add the Maxmem global and set it to the highest physical page number plus 1.
|
| 277523 |
22-Jan-2015 |
gonzo |
Add last_fault_code used in pmap-v6.c if kernel is compiled with "option DEBUG"
|
| 277516 |
21-Jan-2015 |
ian |
Move the __aligned() declaration to where it will actually do something.
|
| 277512 |
21-Jan-2015 |
ian |
Micro-optimize the new arm inline bus_space implementation by grouping all
the data the inline functions access together at the start of the bus_space
struct. The start-of part isn't so important, it's the grouping-together
that's the point: now all the most-accessed data should be in one cache line.
Suggested by: cognet
|
| 277473 |
21-Jan-2015 |
ian |
The versatile platform had two copies of a bus_space that are essentially
duplicates of the standard arm base bus_space, so just use it.
|
| 277472 |
21-Jan-2015 |
ian |
Rename bus_space-v6.c to bus_space_base.c, because it's not v6-specific
and now some v5 Marvell systems are using it. Only define fdt_bus_tag
if option FDT is defined.
|
| 277470 |
21-Jan-2015 |
ian |
Move bs_unimplemented() to bus_space_generic.c so it can be shared.
|
| 277467 |
21-Jan-2015 |
ian |
For some reason, all the arm bus_space functions that work with uint16
values have armv4 in the name. There's nothing armv4-special about them,
so just use the same sort of names as all the other functions.
|
| 277466 |
21-Jan-2015 |
ian |
Use arm/bus_space-v6.c for all armv6 systems, the essentially identical
files for lpc and xilinx aren't needed. Also, fix a couple paste-os.
|
| 277465 |
21-Jan-2015 |
ian |
Use the explicit member initializer style to init the bus_space struct.
Fill in some formerly NULL members where the implementation function
exists. Add a dummy function that panics and use it as a placeholder
for thigns that are still unimplemented. Remove a few unused includes.
|
| 277460 |
21-Jan-2015 |
ian |
Revise the arm bus_space implementation to avoid dereferencing the tag on
every operation to retrieve the bs_cookie value almost nothing actually uses.
The bus_space struct contains a private data pointer (poorly named bs_cookie,
now renamed to bs_privdata) which is used only by a few old armv4 xscale
implementations. The bus_space functions were all defined to take this
value as the first parameter instead of the bus_space_tag_t, requiring all
the inline macro and function expansions to dereference the tag to pass it
to another function, which never uses it. Now all the functions take the tag
as the first parameter and retrieve the privdata if they need it.
Also fix a couple bus_space_unmap() implementations that were calling
kva_free() instead of pmap_unmapdev().
Discussed with: cognet
|
| 277454 |
20-Jan-2015 |
ian |
Add inline implementations of arm bus_space_read/write_N().
Reviewed by: cognet
|
| 277416 |
20-Jan-2015 |
andrew |
Remove the SMP code from locore-v4. These will never use the SMP code as
there is no multi-core hardware prior to ARMv6.
Sponsored by: The FreeBSD Foundation
|
| 277305 |
17-Jan-2015 |
ian |
Minor cleanups, comment changes. No need to load 3 values when setting up
the stack for secondary cores, the other two values are only used for zeroing
bss on the primary core. No need to store the size of the stack at the
top of the stack (seems to be a leftover instruction from some cut-n-paste).
|
| 277156 |
14-Jan-2015 |
ganbold |
Correct cpu type, it was rather Cortex A12 R0.
Approved by: stas (mentor)
|
| 277116 |
13-Jan-2015 |
ganbold |
Add CPU ID for ARM Cortex A17.
Approved by: stas (mentor)
|
| 276984 |
11-Jan-2015 |
andrew |
Rename gic_init_secondary to arm_init_secondary_ic to help with the merge
of the arm_intrng project branch.
|
| 276963 |
11-Jan-2015 |
andrew |
Rework the GIC driver to ease the import of the arm_intrng branch. The
common code has been pulled out to static functions.
|
| 276772 |
07-Jan-2015 |
markj |
Factor out duplicated code from dumpsys() on each architecture into generic
code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly
identical and simply redefine a number of constants and helper subroutines;
a generic implementation will make it easier to implement features around
kernel core dumps. This change does not alter any minidump code and should
have no functional impact.
PR: 193873
Differential Revision: https://reviews.freebsd.org/D904
Submitted by: Conrad Meyer <conrad.meyer@isilon.com>
Reviewed by: jhibbits (earlier version)
Sponsored by: EMC / Isilon Storage Division
|
| 276638 |
03-Jan-2015 |
ian |
Add a new trap-v6.c which has support for all armv7 exceptions. This
mostly paves the way for the new pmap code, and shouldn't result in any
noticible behavior differences.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
|
| 276596 |
02-Jan-2015 |
ian |
Fix alignment directives in arm asm code after clang 3.5 import.
The ancient gas we've been using interprets .align 0 as align to the
minimum required alignment for the current section. Clang's integrated
assembler interprets it as align to a byte boundary. Fortunately both
assemblers interpret a non-zero value as align to 2^N so just make sure
we have appropriate non-zero values everywhere.
|
| 276519 |
01-Jan-2015 |
ian |
Define a WFI macro that expands to the right form of wait-for-interrupt
depending on the architecture.
|
| 276518 |
01-Jan-2015 |
ian |
Rework the vpf support code so that it compiles with clang 3.4, 3.5, and gcc.
Michal Meloun did most of the hard work in figuring out what would work with
which compiler, I just reformated things a bit before committing.
|
| 276470 |
31-Dec-2014 |
ian |
A couple small fixes to make clang 3.5 happy... Move END(sigcode) to the
end of the actual instruction sequence for the function but before some
misc data in the text segment. This eliminates a strange "size must be
constant" error from the integrated assembler. Also, the build_pagetables
function was missing an END(), but really the problem is that it shouldn't
have an ASENTRY() because it's not a function that needs to be a global
symbol with unwind info and all, it's just a little private subroutine
used in very early kernel init.
|
| 276445 |
31-Dec-2014 |
ian |
Change the order of operations for the initial cache setup. Turning off
the cache before clean/invalidate ensured that no new lines can come into
the cache or migrate between levels during the operation, but may not be
safe on some chips. Instead, if the cache was enabled on entry, do the
wbinv while it's still enabled, and then disable it and do a separate
invalidate pass. After the intitial writeback we know there are no
dirty lines left and no new dirty lines can be created as long as we
carefully avoid touching memory before turning the cache off. Add a
comment about that so no new code gets inserted between those points.
|
| 276444 |
31-Dec-2014 |
ian |
Fix a paste-o.
Submitted by: Michal Meloun <meloun@miracle.cz>
|
| 276397 |
30-Dec-2014 |
ian |
Add a new locore.S that #includes the right (v4 or v6) implementation.
The kernel build machinery really wants the entry point to be in a file
named locore.S so doing this avoids a bunch of changes to the build system
for relatively little benefit.
|
| 276396 |
30-Dec-2014 |
ian |
Rename locore.S to locore-v4.S and add a new locore-v6.S for starting up
armv6/7 systems. We need to use some new armv6/7 features at startup
and splitting the implemenations to separate files will be more maintainable
than adding even more #ifdef sections to locore.S.
Because of the standardized interfaces to cache and MMU operations in armv7,
we can tolerate the kernel being entered with caches enabled. This allows
running u-boot and loader(8) with caches enabled, and the performance
improvement can be dramatic (boot times can be cut from over a minute
to under 30 seconds). The new implementation also has more robust cache
and mmu sequences for launching AP cores, and it paves the way for
upcoming changes to the pmap code which will use the TEX remap feature.
Changes in mp_machdep.c work with the new behavior in locore-v6 mp_entry,
and also reuse the original boot-time page tables to get transitioned
from physical to virtual addressing before installing the normal tables.
Submitted by Svatopluk Kraus and Michal Meloun with some changes by me.
|
| 276395 |
30-Dec-2014 |
ian |
Export MAXCPU to the assembler code, needing by upcoming changes to locore.S.
|
| 276394 |
30-Dec-2014 |
ian |
Add armv6 implementations of these cache operations to avoid duplicating
the #ifdef stuff at multiple points the functions are called from. Also
rework the armv7 implementations so that the invalidate operations work
from outermost to innermost cache level, and the writeback works from
inner to outer levels.
|
| 276350 |
28-Dec-2014 |
ian |
Update comments (r4 is not used anywhere), use non-profiling entry macros.
|
| 276336 |
28-Dec-2014 |
ian |
Add cache maintenance functions which will be used by startup code to
initially set up the MMU. Some day they may also be useful as part of
suspend/resume handling, when we get better at power management.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
|
| 276333 |
28-Dec-2014 |
ian |
Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7 (and also present on some armv6 chips including
the arm1176 used on rpi). The information is parsed into a global cpuinfo
structure, which will be used by (upcoming) new cache and tlb maintenance
code to handle cpu-specific variations of the maintence sequences.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
|
| 276206 |
25-Dec-2014 |
ian |
For data and instruction prefetch aborts, call the same handler in the C
code, passing a 0/1 flag that indicates which type of abort it was. This
sets the stage for unifying the handling of page faults in a single routine.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
|
| 276197 |
25-Dec-2014 |
ian |
Oops, I fumbled a semicolon on the style changes; recover it.
|
| 276196 |
25-Dec-2014 |
ian |
Change the style of the DO_AST macro to match the others in this file --
semicolons between the code and comments instead of after the comments,
and line continuations in the arbitrary but now consistant column 76.
No functional changes.
|
| 276191 |
24-Dec-2014 |
ian |
Display the correct value for cache Level of Coherency. Like the other
levels being displayed here, its value needs a +1 adjustment.
|
| 276190 |
24-Dec-2014 |
ian |
Cleanup up ARM *frame structures...
- Eliminate unused irqframe
- Eliminate unused saframe
- Instead of splitting r4-sp storage between the stack and switchframe,
just put all the registers in switchframe and eliminate the un_32 struct.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>
|
| 276187 |
24-Dec-2014 |
ian |
Eliminate unnecessary references to pte.h internals by using the standard
pmap_kenter_temporary() to map pages while dumping.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>
|
| 276180 |
24-Dec-2014 |
andrew |
Rename pic_ipi_get to pic_ipi_read for intrng.
|
| 276033 |
21-Dec-2014 |
andrew |
Fix the unwinder to get past functions with no stack but may cause an
exception. In this case no registers will be updated but the link register
will be copied to the program counter to be used to find the calling
function. In this case the program counter may be updated and we should
continue with the trace.
|
| 276032 |
21-Dec-2014 |
andrew |
Pull out the fdt mapping code into intr.c. The arm_intrng branch also
defines this function allowing the mapping method to change when we move
to it.
|
| 276028 |
21-Dec-2014 |
andrew |
Further reduce the diff between the arm_intrng gic driver and the version
in head.
|
| 276015 |
21-Dec-2014 |
andrew |
Reduce the diff to the arm_intrng project branch by having the read/write
macros take the softc they are accessing.
|
| 275639 |
09-Dec-2014 |
andrew |
Include sys/kernel.h to pick up the definition of hz. subr_syscall.c uses
it after r275616.
X-MFC with: r275616
|
| 275564 |
06-Dec-2014 |
andrew |
Use the unified syntax when generating assembly for clang. The clang 3.5
integrated assembler only accepts it.
MFC after: 1 week
Sponsored by: ABT Systems Ltd
|
| 275523 |
05-Dec-2014 |
andrew |
Switch to an armv6k cpu, without this clang 3.5 complains "bx lr" is
unsupported as it needs a newer cpu.
MFC after: 1 week
Sponsored by: ABT Systems Ltd
|
| 275522 |
05-Dec-2014 |
andrew |
Place the literal pool after a RET otherwise clang 3.5 tries to put it too
far away from a ldr psuedo instruction. With this clang will place the
literal value here where it's close enough to be loaded.
MFC after: 1 week
Sponsored by: ABT Systems Ltd
|
| 275521 |
05-Dec-2014 |
andrew |
Set the alignment to 4-bytes after a string as clang 3.5 can switch to
thumb mode if this is incorrect.
MFC after: 1 week
Sponsored by: ABT Systems Ltd
|
| 275520 |
05-Dec-2014 |
andrew |
Use the unified syntax in a few more assembly files
MFC after: 1 week
Sponsored by: ABT Systems Ltd
|
| 275418 |
02-Dec-2014 |
andrew |
Switch to unified syntax so these can be built with clang 3.5.
MFC after: 1 week
Sponsored by: ABT Systems Ltd
|
| 275417 |
02-Dec-2014 |
andrew |
Use the APSR_nzcv format of mrc. The clang integrated assembler doesn't
support the old usage of r15.
Sponsored by: ABT Systems Ltd
|
| 275416 |
02-Dec-2014 |
andrew |
Fix the name of the coprocessor to include the "p" prefix, the clang
integrated assembler expects this.
MFC after: 1 Week
Sponsored by: ABT Systems Ltd
|
| 275322 |
30-Nov-2014 |
andrew |
Correctly a few incorrect uses of ENTRY/EENTRY and END/EEND
Sponsored by: ABT Systems Ltd
|
| 275321 |
30-Nov-2014 |
andrew |
Remove extra labels, ENTRY_NP already provides them.
Sponsored by: ABT Systems Ltd
|
| 275208 |
28-Nov-2014 |
andrew |
Some device tree configurations place the generic timer under the root
of the tree and not under simplebus. Update the driver to handle this.
Submitted by: Julien Grall <julien.grall AT linaro.org>
MFC after: 1 week
|
| 275207 |
28-Nov-2014 |
andrew |
We don't use the hypervisor interrupt, make it optional in the device tree.
Submitted by: Julien Grall <julien.grall AT linaro.org>
MFC after: 1 week
|
| 274839 |
22-Nov-2014 |
ian |
When doing a PREREAD sync of an mbuf-type dma buffer, do a writeback of
the first cacheline if the buffer start address is not on a cacheline
boundary. Normally a buffer which is not cacheline-aligned is bounced,
but a special rule applies for mbufs, which are always misaligned due to
the header. We know the cpu will not write to the header while dma is in
progress (so we've been told anyway), but it may have written to the
header shortly before starting a read, so we need to flush that write out
to memory before invalidating the whole buffer.
In collaboration with Mical Meloun and Svata Kraus.
|
| 274668 |
18-Nov-2014 |
imp |
opt_global.h is included automatically in the build. No need to
explicitly include it in these places.
Sponsored by: Netflix
|
| 274605 |
16-Nov-2014 |
ian |
No functional changes. Remove a couple outdated or inane comments and
add new comment blocks describing why the cache maintenance sequences are
done in the order they are for each case.
|
| 274604 |
16-Nov-2014 |
ian |
Correct the sequence of busdma sync ops involved with PRE/POSTREAD syncs.
We used to invalidate the cache for PREREAD alone, or writeback+invalidate
for PREREAD with PREWRITE, then treat POSTREAD as a no-op. Prefetching on
modern systems can lead to parts of a DMA buffer getting pulled into the
caches while DMA is in progress (due to access of "nearby" data), so it's
mandatory to invalidate during the POSTREAD sync even if a PREREAD
invalidate also happened.
In the PREREAD case the invalidate is done to ensure that there are no
dirty cache lines that might get automatically evicted during the DMA,
corrupting the buffer. In a PREREAD+PREWRITE case the writeback which is
required for PREWRITE handling is suffficient to avoid corruption caused
by eviction and no invalidate need be done until POSTREAD time.
Submitted by: Michal Meloun <meloun@miracle.cz>
|
| 274603 |
16-Nov-2014 |
ian |
Do the cache invalidate sequence from the outermost to innermost, required
for correct operation.
Submitted by: Michal Meloun <meloun@miracle.cz>
|
| 274602 |
16-Nov-2014 |
ian |
Do not do a cache invalidate on a PREREAD sync that is also a PREWRITE sync.
The PREWRITE handling does a writeback of any dirty cachelines, so there's
no danger of an eviction during the DMA corrupting the buffer. There will
be an invalidate done during POSTREAD, so doing it before the read too is
wasted time.
|
| 274596 |
16-Nov-2014 |
ian |
Indent a couple lines properly and expand a comment. No functional changes.
|
| 274545 |
15-Nov-2014 |
ian |
Whitespace and comment tweaks, no functional changes.
|
| 274538 |
15-Nov-2014 |
ian |
When doing busdma sync ops for BUSDMA_COHERENT memory, there is no need
for cache maintenance operations, but ensure that all prior writes have
reached memory when doing a PREWRITE sync.
Submitted by: Michal Meloun <meloun@miracle.cz>
|
| 274536 |
15-Nov-2014 |
ian |
Use the standard powerof2() macro from param.h instead of a local one.
Pointed out by: jhb@
|
| 274484 |
13-Nov-2014 |
zbb |
Fix typo in ARM GIC device_printf()
Obtained from: Semihalf
Sponsored by: The FreeBSD Foundation
|
| 274191 |
06-Nov-2014 |
ian |
Strengthen the sanity checking of busdma tag parameters.
It turns out an alignment of zero can lead to an endless loop in the
vm reservations code, so specifically disallow that. The manpage says
hardware which can do dma at any address should use a value of one, which
hints at the forbiddeness of zero without exactly saying it. Several
other conditions which could lead to insanity in working with the tag are
also checked now.
Every existing call to bus_dma_tag_create() (about 680 of them) was
eyeballed for violations of these things, and two alignment=0 glitches
were fixed. It's possible something was missed, but overall this
shouldn't lead to any arm users suddenly experiencing failures.
|
| 273908 |
31-Oct-2014 |
kevlo |
Fix usage of kern_getenv().
|
| 273703 |
26-Oct-2014 |
ian |
Remove the ARM_DEVICE_MULTIPASS option and make its effect be the default.
Multipass device attachment was tested on many arm platforms by users and
only success was reported on the arm@ mailing list. This is just the
long-delayed followup of making it the default.
Multipass attachment is necessary when using vendor-supplied FDT data,
because our devices may need to be attached in a different order than they
are described in the FDT data.
|
| 273701 |
26-Oct-2014 |
alc |
By the time that pmap_init() runs, vm_phys_segs[] has been initialized. Obtaining
the end of memory address from vm_phys_segs[] is a little easier than obtaining it
from phys_avail[].
Discussed with: Svatopluk Kraus
|
| 273599 |
24-Oct-2014 |
loos |
Fix a bug where DMA maps created with bus_dmamap_create() won't increment
the map count and without being able to keep track of the current map
allocation, bus_dma_tag_destroy() will fail to proceed and will return
EBUSY even after all the maps have been correctly destroyed with
bus_dmamap_destroy().
Found while testing the detach method of a NIC.
Tested on: BBB (am335x)
Reviewed by: cognet, ian
MFC after: 1 week
|
| 273590 |
24-Oct-2014 |
ian |
Accept the documented FDT compatible string for the PL310 cache controller
as well as the non-standard string we've been using for a couple years.
|
| 273377 |
21-Oct-2014 |
hselasky |
Fix multiple incorrect SYSCTL arguments in the kernel:
- Wrong integer type was specified.
- Wrong or missing "access" specifier. The "access" specifier
sometimes included the SYSCTL type, which it should not, except for
procedural SYSCTL nodes.
- Logical OR where binary OR was expected.
- Properly assert the "access" argument passed to all SYSCTL macros,
using the CTASSERT macro. This applies to both static- and dynamically
created SYSCTLs.
- Properly assert the the data type for both static and dynamic
SYSCTLs. In the case of static SYSCTLs we only assert that the data
pointed to by the SYSCTL data pointer has the correct size, hence
there is no easy way to assert types in the C language outside a
C-function.
- Rewrote some code which doesn't pass a constant "access" specifier
when creating dynamic SYSCTL nodes, which is now a requirement.
- Updated "EXAMPLES" section in SYSCTL manual page.
MFC after: 3 days
Sponsored by: Mellanox Technologies
|
| 273288 |
19-Oct-2014 |
andrew |
Allow the armv6 kernel to be build with PHYSADDR undefined. The kernel
will now find the virtual to physical mapping for libkvm to use at
runtime. This makes PHYSADDR redundant, however keep it around to give
everyone a chance to update their libkvm.
MFC after: 1 week
|
| 273284 |
19-Oct-2014 |
andrew |
Allow libkvm to get the kernel va to pa delta without the need for
physaddr. This should allow for a kernel where PHYSADDR and KERNPHYSADDR
are both undefined.
For now libkvm will use the old method of reading physaddr and kernaddr
to allow it to work with old kernels. This could be removed in the future
when enough time has passed.
Differential Revision: https://reviews.freebsd.org/D939
MFC after: 1 week
|
| 273251 |
18-Oct-2014 |
andrew |
Add an elf not so kgdb detects the kernel as a FreeBSD elf file. The
ELFNOTE macro is based on one from the FreeBSD/ARM Xen tree [1].
Obtained from: Julien Grall <julien.grall AT linaro.org> [1]
|
| 273174 |
16-Oct-2014 |
davide |
Follow up to r225617. In order to maximize the re-usability of kernel code
in userland rename in-kernel getenv()/setenv() to kern_setenv()/kern_getenv().
This fixes a namespace collision with libc symbols.
Submitted by: kmacy
Tested by: make universe
|
| 273157 |
16-Oct-2014 |
rpaulo |
Remove the "Unable to unwind further" message from DDB.
The ARM version of DDB is supposedly reliable enough making this
message benign.
|
| 272766 |
08-Oct-2014 |
markj |
Pass up the error status of minidumpsys() to its callers.
PR: 193761
Submitted by: Conrad Meyer <conrad.meyer@isilon.com>
Sponsored by: EMC / Isilon Storage Division
|
| 272356 |
01-Oct-2014 |
andrew |
Split you the syscall handling to a separate file.
|
| 272333 |
30-Sep-2014 |
ian |
When building the lists of available memory, actually honor the exclusion
flags, like the comment says it does.
Pointy hat: ian
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
|
| 272209 |
27-Sep-2014 |
andrew |
Add machine/sysreg.h to simplify accessing the system control coprocessor
registers and use it in the ARMv7 CPU functions.
The sysreg.h file has been checked by hand, however it may contain errors
with the comments on when a register was first introduced. The ARMv7 cpu
functions have been checked by compiling both the previous and this version
and comparing the md5 of the object files.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>
Submitted by: Michal Meloun <meloun at miracle.cz>
Reviewed by: ian, rpaulo
Differential Revision: https://reviews.freebsd.org/D795
|
| 272098 |
25-Sep-2014 |
royger |
ddb: allow specifying the exact address of the symtab and strtab
When the FreeBSD kernel is loaded from Xen the symtab and strtab are
not loaded the same way as the native boot loader. This patch adds
three new global variables to ddb that can be used to specify the
exact position and size of those tables, so they can be directly used
as parameters to db_add_symbol_table. A new helper is introduced, so callers
that used to set ksym_start and ksym_end can use this helper to set the new
variables.
It also adds support for loading them from the Xen PVH port, that was
previously missing those tables.
Sponsored by: Citrix Systems R&D
Reviewed by: kib
ddb/db_main.c:
- Add three new global variables: ksymtab, kstrtab, ksymtab_size that
can be used to specify the position and size of the symtab and
strtab.
- Use those new variables in db_init in order to call db_add_symbol_table.
- Move the logic in db_init to db_fetch_symtab in order to set ksymtab,
kstrtab, ksymtab_size from ksym_start and ksym_end.
ddb/ddb.h:
- Add prototype for db_fetch_ksymtab.
- Declate the extern variables ksymtab, kstrtab and ksymtab_size.
x86/xen/pv.c:
- Add support for finding the symtab and strtab when booted as a Xen
PVH guest. Since Xen loads the symtab and strtab as NetBSD expects
to find them we have to adapt and use the same method.
amd64/amd64/machdep.c:
arm/arm/machdep.c:
i386/i386/machdep.c:
mips/mips/machdep.c:
pc98/pc98/machdep.c:
powerpc/aim/machdep.c:
powerpc/booke/machdep.c:
sparc64/sparc64/machdep.c:
- Use the newly introduced db_fetch_ksymtab in order to set ksymtab,
kstrtab and ksymtab_size.
|
| 271906 |
20-Sep-2014 |
ian |
Make the ARM MPCore Timer driver work with published standard FDT bindings.
We've always considered the mpcore timers to be a single monolithic device
and we defined our own fdt binding for it with our own compat string. The
published bindings treat the timers as two separate devices, a global
timer and a "timer-watchdog" device for the per-cpu private timers. Thus
our binding has two tuples in the regs property, one set of registers for
the global timer and one for the private timers. The published bindings
have two separate devices, each with a single set of registers. (Note that
we don't use the optional watchdog feature of the hardware.)
These changes add the compat strings for the published bindings. If our
own compat string appears, we expect to get two sets of memory resources.
For the published bindings, there's only one set of memory resources, and
only the private timers have an associated interrupt.
The other major change is that there can no longer be a single global var
for the softc pointer because now there may be multiple devices at
runtime. Since the global timer is used only as a timecounter and the
private timers only as eventtimers, and there will only be one of each,
those are now the pointers which are global, and the priv fields of those
structures backlink to the device softc.
|
| 271630 |
15-Sep-2014 |
ian |
The private peripheral interrupts start at offset 16, not 0. Also, use
names rather than inline mystery constants for these offsets.
Pointed out by: andrew
|
| 271601 |
14-Sep-2014 |
ian |
Add a common routine for parsing FDT data describing an ARM GIC interrupt.
In the fdt data we've written for ourselves, the interrupt properties
for GIC interrupts have just been a bare interrupt number. In standard
data that conforms to the published bindings, GIC interrupt properties
contain 3-tuples that describe the interrupt as shared vs private, the
interrupt number within the shared/private address space, and configuration
info such as level vs edge triggered.
The new gic_decode_fdt() function parses both types of data, based on the
#interrupt-cells property. Previously, each platform implemented a decode
routine and put a pointer to it into fdt_pic_table. Now they can just
list this function in their table instead if they use arm/gic.c.
|
| 271595 |
14-Sep-2014 |
ian |
Add compat strings for all the flavors of GIC this driver should support.
Also allow the driver to attach to ofwbus as well as simplebus, some FDT
data puts the root interrupt controller on the root bus.
|
| 271594 |
14-Sep-2014 |
ian |
Fix an undefined variable that was accidentally not causing an error.
The code had references to both intr_offset and intr_parent variable names
as referring to the parent interrupt node. The intr_parent variable
wasn't actually defined anywhere, but the only references to it were as
an argument to a macro that didn't use that argument in expansion, so
the undefined variable accidentally didn't cause an error.
The intr_parent name makes more sense in context, so change all occurrances
of intr_offset to intr_parent.
|
| 271484 |
12-Sep-2014 |
jhb |
- Don't let rman_reserve_resource() activate the resource in
nexus_alloc_resource() and don't set a bushandle.
nexus_activate_resource() will set a proper bushandle.
- Implement a proper nexus_release_resource().
- Fix ixppcib_activate_resource() to call rman_activate_resource()
before creating a mapping for the resource.
Tested by: jmg
|
| 271422 |
11-Sep-2014 |
andrew |
Rename pmap_kenter_temp to pmap_kenter_temporary to be consistent with the
other architectures with this function.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>
Submitted by: Michal Meloun <meloun at miracle.cz>
|
| 271398 |
10-Sep-2014 |
andrew |
Unify interrupts bit definition and usage. While here remove PSR_C_bit.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>,
Michal Meloun <meloun at miracle.cz>
Differential Revision: https://reviews.freebsd.org/D754
|
| 271240 |
07-Sep-2014 |
andrew |
When entering the kernel with the MMU off assume we are running from a
va == pa map.
I'm not sure the code would work if we are not running from the identity
map as the ARM core may attempt to read the next instruction from an
invalid memory location.
|
| 271235 |
07-Sep-2014 |
andrew |
Remove Lvirtaddr and Lphysaddr, these don't appear to be used.
|
| 271232 |
07-Sep-2014 |
andrew |
Generalise the va to pa code and use it when starting secondary cores
Reviewed by: ian@, rpaulo@
Differential Revision: https://reviews.freebsd.org/D736
|
| 271189 |
06-Sep-2014 |
andrew |
Allow us to use the virtual timer. It is currently disabled, but should
be usable as the default timer in place of the physical timer.
We are guaranteed to have access to the virtual timer, but when running
under a hypervisor may not have access to the physical.
Differential Revision: https://reviews.freebsd.org/D588
|
| 271181 |
05-Sep-2014 |
andrew |
Add the virtual timer irq to the list of interrupts we enable on secondary
cores.
|
| 270945 |
01-Sep-2014 |
ian |
Rename OF_xref_phandle() to OF_node_from_xref() and add a new function
that provides the inverse translation, OF_xref_from_node().
Discussed with: nwhitehorn
|
| 270862 |
30-Aug-2014 |
ian |
Fix the handling of MMU type in the AP entry code. The ARM_MMU_V6/V7
symbols are always #defined to 0 or 1, so use #if SYM not #if defined(SYM).
Also, it helps if you include the header file that defines the symbols.
|
| 270124 |
18-Aug-2014 |
imp |
/usr/libexec/ld.so.1 never was a thing on FreeBSD/arm. This was the
FreeBSD 3.x and 4.x run time linker. FreeBSD/arm's first release was
5.0. Retire this long-dead code.
|
| 270123 |
18-Aug-2014 |
imp |
Expand the elf brandelf infrastructure to give access to the whole ELF
header (Elf_Ehdr) to determine if a particular interpretor wants to
accept it or not. Use this mechanism to filter EABI arm on OABI arm
kernels, and vice versa. This method could also be used to implement
OABI on EABI arm kernels, if desired, or to allow a single mips kernel
to run o32, n32 and n64 binaries.
Differential Revision: https://reviews.freebsd.org/D609
|
| 269959 |
14-Aug-2014 |
imp |
Add support for multipass to Atmel, for both FDT and !FDT cases.
|
| 269956 |
14-Aug-2014 |
imp |
From https://sourceware.org/ml/newlib/2014/msg00113.html
By Richard Earnshaw at ARM
>
>GCC has for a number of years provides a set of pre-defined macros for
>use with determining the ISA and features of the target during
>pre-processing. However, the design was always somewhat cumbersome in
>that each new architecture revision created a new define and then
>removed the previous one. This meant that it was necessary to keep
>updating the support code simply to recognise a new architecture being
>added.
>
>The ACLE specification (ARM C Language Extentions)
>(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.swdev/index.html)
>provides a much more suitable interface and GCC has supported this
>since gcc-4.8.
>
>This patch makes use of the ACLE pre-defines to map to the internal
>feature definitions. To support older versions of GCC a compatibility
>header is provided that maps the traditional pre-defines onto the new
>ACLE ones.
Stop using __FreeBSD_ARCH_armv6__ and switch to __ARM_ARCH >= 6 in the
couple of places in tree. clang already implements ACLE. Add a define
that says we implement version 1.1, even though the implementation
isn't quite complete.
|
| 269767 |
09-Aug-2014 |
imp |
Per discussion on arm@, the compiler generates misaligned
relocations. Cope with memcpy when needed.
Submitted by: fabient@ (plus changes suggested by thread)
|
| 269728 |
08-Aug-2014 |
kib |
Change pmap_enter(9) interface to take flags parameter and superpage
mapping size (currently unused). The flags includes the fault access
bits, wired flag as PMAP_ENTER_WIRED, and a new flag
PMAP_ENTER_NOSLEEP to indicate that pmap should not sleep.
For powerpc aim both 32 and 64 bit, fix implementation to ensure that
the requested mapping is created when PMAP_ENTER_NOSLEEP is not
specified, in particular, wait for the available memory required to
proceed.
In collaboration with: alc
Tested by: nwhitehorn (ppc aim32 and booke)
Sponsored by: The FreeBSD Foundation and EMC / Isilon Storage Division
MFC after: 2 weeks
|
| 269646 |
06-Aug-2014 |
ian |
Use a SYSINIT to init the array of interrupt names on arm. This was
called from initarm() in arm/machdep.c, but many legacy arm platforms
have their own private initarm(), so a SYSINIT fixes everyone.
Reported by: jmg
|
| 269606 |
05-Aug-2014 |
ian |
Add an arm option, ARM_DEVICE_MULTIPASS, used to opt-in to multi-pass
device attachment on arm platforms. If this is defined, nexus attaches
early in BUS_PASS_BUS, and other busses and devices attach later, in the
pass number they are set up for. Without it defined, nexus attaches in
BUS_PASS_DEFAULT and thus so does everything else, which is status quo.
Arm platforms which use FDT data to enumerate devices have been relying
on devices being attached in the exact order they're listed in the dts
source file. That's one of things currently preventing us from using
vendor-supplied fdt data (because then we don't control the order of the
devices in the data). Multi-pass attachment can go a long way towards
solving that problem by ensuring things like clock and interrupt drivers
are attached before the more mundane devices that need them.
The long-term goal is to have all arm fdt-based platforms using multipass.
This option is a bridge to that, letting us enable it selectively as
platforms are converted and tested (the alternative being to just throw
a big switch and try to fight fires as they're reported).
|
| 269605 |
05-Aug-2014 |
ian |
Attach arm generic interrupt and timer drivers in the middle of
BUS_PASS_INTERRUPT and BUS_PASS_TIMER, respectively.
|
| 269598 |
05-Aug-2014 |
ian |
Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU.
Because that's earlier than interrupts are available, set up deferred
configuration of interrupts (which are used only for debugging).
|
| 269577 |
05-Aug-2014 |
glebius |
Merge all MD sf_buf allocators into one MI, residing in kern/subr_sfbuf.c
The MD allocators were very common, however there were some minor
differencies. These differencies were all consolidated in the MI allocator,
under ifdefs. The defines from machine/vmparam.h turn on features required
for a particular machine. For details look in the comment in sys/sf_buf.h.
As result no MD code left in sys/*/*/vm_machdep.c. Some arches still have
machine/sf_buf.h, which is usually quite small.
Tested by: glebius (i386), tuexen (arm32), kevlo (arm32)
Reviewed by: kib
Sponsored by: Netflix
Sponsored by: Nginx, Inc.
|
| 269485 |
03-Aug-2014 |
alc |
Retire pmap_change_wiring(). We have never used it to wire virtual pages.
We continue to use pmap_enter() for that. For unwiring virtual pages, we
now use pmap_unwire(), which unwires a range of virtual addresses instead
of a single virtual page.
Sponsored by: EMC / Isilon Storage Division
|
| 269390 |
01-Aug-2014 |
ian |
Fix unwind-info errors in our hand-written arm assembler code.
We have functions nested within functions, and places where we start a
function then never end it, we just jump to the middle of something else.
We tried to express this with nested ENTRY()/END() macros (which result
in .fnstart and .fnend directives), but it turns out there's no way to
express that nesting in ARM EHABI unwind info, and newer tools treat
multiple .fnstart directives without an intervening .fnend as an error.
These changes introduce two new macros, EENTRY() and EEND(). EENTRY()
creates a global label you can call/jump to just like ENTRY(), but it
doesn't emit a .fnstart. EEND() is a no-op that just documents the
conceptual endpoint that matches up with the same-named EENTRY().
This is based on patches submitted by Stepan Dyatkovskiy, but I made some
changes and added the EEND() stuff, so blame any problems on me.
Submitted by: Stepan Dyatkovskiy <stpworld@narod.ru>
|
| 269321 |
31-Jul-2014 |
ian |
Switch to using counter(9) for the new 64-bit stats kept by armv6 busdma.
|
| 269217 |
29-Jul-2014 |
ian |
Export some new busdma stats via sysctl for armv6. Added:
hw.busdma.tags_total: 46
hw.busdma.maps_total: 1302
hw.busdma.maps_dmamem: 851
hw.busdma.maps_coherent: 849
hw.busdma.maploads_total: 1568812
hw.busdma.maploads_bounced: 16750
hw.busdma.maploads_coherent: 920
hw.busdma.maploads_dmamem: 920
hw.busdma.maploads_mbuf: 1542766
hw.busdma.maploads_physmem: 0
|
| 269216 |
29-Jul-2014 |
ian |
A while back, the array of segments used for a load/mapping operation was
moved from the stack into the tag structure. In retrospect that was a bad
idea, because nothing protects that array from concurrent access by
multiple threads.
This change moves the array to the map structure (actually it's allocated
following the structure, but all in a single malloc() call).
This also establishes a "sane" limit of 4096 segments per map. This is
mostly to prevent trying to allocate all of memory if someone accidentally
uses a tag with nsegments set to BUS_SPACE_UNRESTRICTED. If there's ever
a genuine need for more than 4096, don't hesitate to increase this (or
maybe make it tunable).
Reviewed by: cognet
|
| 269215 |
29-Jul-2014 |
ian |
We never need bounce pages for memory we allocate. We cleverly allocate
memory the matches all the constraints of the dma tag so that bouncing
will never be required.
Reviewed by: cognet
|
| 269214 |
29-Jul-2014 |
ian |
Replace a bunch of double-indirection with a local pointer var (that is,
(*mapp)->something becomes map->something). No functional changes.
Reviewed by: cognet
|
| 269213 |
29-Jul-2014 |
ian |
Don't clear the DMAMAP_DMAMEM_ALLOC flag set a few lines earlier. Doh!
Reviewed by: cognet
|
| 269212 |
29-Jul-2014 |
ian |
Memory belonging to an mbuf, or allocated by bus_dmamem_alloc(), never
triggers a need to bounce due to cacheline alignment. These buffers
are always aligned to cacheline boundaries, and even when the DMA operation
starts at an offset within the buffer or doesn't extend to the end of the
buffer, it's safe to flush the complete cachelines that were only partially
involved in the DMA. This is because there's a very strict rule on these
types of buffers that there will not be concurrent access by the CPU and
one or more DMA transfers within the buffer.
Reviewed by: cognet
|
| 269211 |
29-Jul-2014 |
ian |
The run_filter() function doesn't just run dma tag exclusion filter
functions, it has evolved to make a variety of decisions about whether
the DMA needs to bounce, so rename it to must_bounce(). Rewrite it to
perform checks outside of the ancestor loop if they're based on information
that's wholly contained within the original tag. Now the loop only checks
exclusion zones in ancestor tags.
Also, add a new function, might_bounce() which does a fast inline check
of flags within the tag and map to quickly eliminate the need to call
the more expensive must_bounce() for each page in the DMA operation.
Within the mapping loops, use map->pagesneeded != 0 as a proxy for all
the various checks on whether bouncing might be required. If no pages
were reserved for bouncing during the checks before the mapping loop,
then there's no need to re-check any of the conditions that can lead
to bouncing -- all those checks already decided there would be no bouncing.
Reviewed by: cognet
|
| 269210 |
29-Jul-2014 |
ian |
Propagate any alignment restriction from the parent tag to a new tag,
keeping the more restrictive of the two values.
Reviewed by: cognet
|
| 269209 |
29-Jul-2014 |
ian |
Reformat some continuation lines. No functional changes.
Reviewed by: cognet
|
| 269208 |
29-Jul-2014 |
ian |
Correct the comparison logic when looking for intersections between
exclusion zones and phsyical memory. The phys_avail[i] entries are the
address of the first byte of ram in the region, and phys_avail[i+1]
entries are the address of the first byte of ram in the next region
(i.e., they're not included in the region that starts at phys_avail[i]).
Reviewed by: cognet
|
| 269207 |
29-Jul-2014 |
ian |
The exclusion_bounce() routine compares unchanging values in the tag with
unchanging values in the phys_avail array, so do the comparisons just once
at tag creation time and set a flag to remember the result.
Reviewed by: cognet
|
| 269206 |
29-Jul-2014 |
ian |
Rename _bus_dma_can_bounce(), add new inline routines.
DMA on arm can bounce for several reasons, and _bus_dma_can_bounce() only
checks for the lowaddr/highaddr exclusion ranges in the dma tag, so now
it's named exclusion_bounce(). The other reasons for bouncing are checked
by the new functions alignment_bounce() and cacheline_bounce().
Reviewed by: cognet
|
| 269136 |
26-Jul-2014 |
ian |
Pull in the armv4 "fast out" code for checking whether busdma can bounce
due to an excluded region of physical memory.
|
| 269135 |
26-Jul-2014 |
ian |
Remove completely bogus alignment check -- it's the physical address that
needs to be aligned, not the virtual, and it doesn't seem worth the cost
of a vtophys() call just to see if kmem_alloc_contig() works properly.
|
| 269105 |
26-Jul-2014 |
gavin |
Add error return to dumpsys(), and use it in doadump().
This commit does not add error returns to minidumpsys() or
textdump_dumpsys(); those can also be added later.
Submitted by: Conrad Meyer (EMC / Isilon storage division)
|
| 268776 |
16-Jul-2014 |
alc |
Implement pmap_unwire(). See r268327 for the motivation behind this change.
|
| 268693 |
15-Jul-2014 |
alc |
Actually set the "no execute" bit on 1 MB page mappings in pmap_protect().
Previously, the "no execute" bit was being set directly in the PTE, instead
of the local variable in which the new PTE value is being constructed. So,
when the local variable was finally assigned to the PTE, the "no execute"
bit setting was lost.
|
| 268655 |
15-Jul-2014 |
alc |
Eliminate repeated calculation of next_bucket in pmap_protect() and
pmap_remove(). Eliminate an unnecessary variable from pmap_remove() and
pmap_advise().
|
| 268623 |
14-Jul-2014 |
alc |
Eliminate dead code. There is no direct map. This code was cut-and-pasted
from amd64.
|
| 267992 |
28-Jun-2014 |
hselasky |
Pull in r267961 and r267973 again. Fix for issues reported will follow.
|
| 267985 |
27-Jun-2014 |
gjb |
Revert r267961, r267973:
These changes prevent sysctl(8) from returning proper output,
such as:
1) no output from sysctl(8)
2) erroneously returning ENOMEM with tools like truss(1)
or uname(1)
truss: can not get etype: Cannot allocate memory
|
| 267961 |
27-Jun-2014 |
hselasky |
Extend the meaning of the CTLFLAG_TUN flag to automatically check if
there is an environment variable which shall initialize the SYSCTL
during early boot. This works for all SYSCTL types both statically and
dynamically created ones, except for the SYSCTL NODE type and SYSCTLs
which belong to VNETs. A new flag, CTLFLAG_NOFETCH, has been added to
be used in the case a tunable sysctl has a custom initialisation
function allowing the sysctl to still be marked as a tunable. The
kernel SYSCTL API is mostly the same, with a few exceptions for some
special operations like iterating childrens of a static/extern SYSCTL
node. This operation should probably be made into a factored out
common macro, hence some device drivers use this. The reason for
changing the SYSCTL API was the need for a SYSCTL parent OID pointer
and not only the SYSCTL parent OID list pointer in order to quickly
generate the sysctl path. The motivation behind this patch is to avoid
parameter loading cludges inside the OFED driver subsystem. Instead of
adding special code to the OFED driver subsystem to post-load tunables
into dynamically created sysctls, we generalize this in the kernel.
Other changes:
- Corrected a possibly incorrect sysctl name from "hw.cbb.intr_mask"
to "hw.pcic.intr_mask".
- Removed redundant TUNABLE statements throughout the kernel.
- Some minor code rewrites in connection to removing not needed
TUNABLE statements.
- Added a missing SYSCTL_DECL().
- Wrapped two very long lines.
- Avoid malloc()/free() inside sysctl string handling, in case it is
called to initialize a sysctl from a tunable, hence malloc()/free() is
not ready when sysctls from the sysctl dataset are registered.
- Bumped FreeBSD version to indicate SYSCTL API change.
MFC after: 2 weeks
Sponsored by: Mellanox Technologies
|
| 267597 |
17-Jun-2014 |
tuexen |
Different versions of the ARM processor use different registers.
Fix the code used on a Raspberry Pi.
Reviewed by: markm@
|
| 267548 |
16-Jun-2014 |
attilio |
- Modify vm_page_unwire() and vm_page_enqueue() to directly accept
the queue where to enqueue pages that are going to be unwired.
- Add stronger checks to the enqueue/dequeue for the pagequeues when
adding and removing pages to them.
Of course, for unmanaged pages the queue parameter of vm_page_unwire() will
be ignored, just as the active parameter today.
This makes adding new pagequeues quicker.
This change effectively modifies the KPI. __FreeBSD_version will be,
however, bumped just when the full cache of free pages will be
evicted.
Sponsored by: EMC / Isilon storage division
Reviewed by: alc
Tested by: pho
|
| 267408 |
12-Jun-2014 |
jmg |
clear the write bit... This allows my AVILA board to survive a
portsnap extract, where previously it would panic.. clearly someone
who knows pmap should optimize this code per alc's comment...
Submitted by: alc
MFC after: probably
|
| 267389 |
12-Jun-2014 |
br |
Activate IRQ 30 (non-secure private timer IRQ) for case we are running
in non-secure state.
|
| 267213 |
07-Jun-2014 |
alc |
Add a page size field to struct vm_page. Increase the page size field when
a partially populated reservation becomes fully populated, and decrease this
field when a fully populated reservation becomes partially populated.
Use this field to simplify the implementation of pmap_enter_object() on
amd64, arm, and i386.
On all architectures where we support superpages, the cost of creating a
superpage mapping is roughly the same as creating a base page mapping. For
example, both kinds of mappings entail the creation of a single PTE and PV
entry. With this in mind, use the page size field to make the
implementation of vm_map_pmap_enter(..., MAP_PREFAULT_PARTIAL) a little
smarter. Previously, if MAP_PREFAULT_PARTIAL was specified to
vm_map_pmap_enter(), that function would only map base pages. Now, it will
create up to 96 base page or superpage mappings.
Reviewed by: kib
Sponsored by: EMC / Isilon Storage Division
|
| 266849 |
29-May-2014 |
cognet |
For old CPUs, map the 64 first MB of RAM as it used to be. Some ports
(XScale mainly) expects the memory located before the kernel to be mapped,
and use it to allocate the page tables, the various stacks, etc.
A better fix would probably be to rewrite the various bla_machdep.c to stop
using that RAM, but I'm not so inclined to do it, especially since I don't
have hardware for all of them.
|
| 266673 |
25-May-2014 |
zbb |
Delete obsolete and unused PJ4B CPU functions
Since PJ4Bv7 uses armv7_ CPU functions only pj4b_config
function is necessary. Remove obsolete routines.
|
| 266672 |
25-May-2014 |
zbb |
Fix context switch on PJ4Bv7 and remove obsolete pj4b_/arm11 functions
Use armv7_setttb that sets proper PT attributes.
Get rid of unused CPU functions, put nullop instead.
Exchange obsolete pj4b_/arm11_ functions to the appropriate armv7_ ones.
|
| 266651 |
25-May-2014 |
ian |
Fix whitespace glitches.
Pointed out by: jhb
|
| 266631 |
24-May-2014 |
zbb |
Enable automatic superpages promotion by default on ARMv6/v7
From now on superpages are enabled by default on ARM.
One can still disable superpages utilization by adding:
vm.pmap.sp_enabled=0
to loader.conf
|
| 266621 |
24-May-2014 |
ian |
Eliminate one of the causes of spurious interrupts on armv6. The arm weak
memory ordering model allows writes to different devices to complete out
of order, leading to a situation where the write that clears an interrupt
source at a device can complete after a write that unmasks and EOIs the
interrupt at the interrupt controller, leading to a spurious re-interrupt.
This adds a generic barrier function specific to the needs of interrupt
controllers, and calls that function from the GIC and TI AINTC controllers.
There may still be other soc-specific controllers that need to make the call.
Reviewed by: cognet, Svatopluk Kraus <onwahe@gmail.com>
MFC after: 3 days
|
| 266565 |
22-May-2014 |
ian |
Map device memory using PTE_DEVICE attributes, and also ensure that the
shared flag is set on normal-memory mappings made via pmap_kenter() for SMP.
The "shared flag" part of this change isn't obvious from the diff, here's
the deal... by using the array of preformatted page table entry templates
instead of constructing the PTE from scratch, we automatically get the
right attribute bits set for both caching and shared.
MFC after: 1 week
|
| 266301 |
17-May-2014 |
andrew |
Add the start of the ARM platform code. This is based on the PowerPC
platform code, it is expected these will be merged in the future when the
ARM code is more complete.
Until more boards can be tested only use this with the Raspberry Pi and
rrename the functions on the other SoCs.
Reviewed by: ian@
|
| 266271 |
16-May-2014 |
gavin |
Fix spelling mistake in comment.
Spotted during: http://www.bsdcan.org/2014/schedule/events/484.en.html
|
| 266083 |
14-May-2014 |
markm |
Give suitably-endowed ARMs a register similar to the x86 TSC register.
Here, "suitably endowed" means that the System Control Coprocessor
(#15) has Performance Monitoring Registers, including a CCNT (Cycle
Count) register.
The CCNT register is used in a way similar to the TSC register in
x86 processors by the get_cyclecount(9) function. The entropy-harvesting
thread is a heavy user of this function, and will benefit from not
having to call binuptime(9) instead.
One problem with the CCNT register is that it is 32-bit only, so
the upper 32-bits of the returned number are always 0. The entropy
harvester does not care, but in case any one else does, follow-up
work may include an interrup trap to increment an upper-32-bit
counter on CCNT overflow.
Another problem is that the CCNT register is not readable in user-mode
code; in can be made readable by userland, but then it is also
writable, and so is a good chunk of the PMU system. For that reason,
the CCNT is not enabled for user-mode access in this commit.
Like the x86, there is one CCNT per core, so they don't all run in
perfect sync.
Reviewed by: ian@ (an earlier version)
Tested by: ian@ (same earlier version)
Committed from: WANDBOARD-QUAD
|
| 265914 |
12-May-2014 |
ian |
Cleanup some style nits.
|
| 265913 |
12-May-2014 |
ian |
Interrupts need to be disabled on entry to cpu_sleep() for ARM. Given
that and the need to be in a critical section when switching to idleclock
mode for event timers, use spinlock_enter()/exit() to achieve both needs.
The ARM WFI (wait for interrupt) instruction blocks until an interrupt is
asserted, and it will unblock even if interrupts are masked, and it will
unblock immediately if an interrupt is already pending. It is necessary
to execute it with interrupts disabled, otherwise the interrupt that
should unblock it may occur and be serviced just prior to executing the
instruction. At that point the system is inappropriately asleep until
the next timer tick or some other random interrupt happens.
In general, interrupts need to be disabled continuously from the time the
decision is made that there is no work to be done and sleeping is needed
until actually going to sleep, to avoid a race where handling a new
interrupt changes the basis for deciding there is no work to be done.
Submitted by: hps@ (in slightly different form)
|
| 265870 |
11-May-2014 |
ian |
Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().
On modern ARM SoCs the L2 cache controller sits between the CPU and the
AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We
map the device registers using the 'Device' memory attribute, which means
the memory is not cached, but writes to it are buffered. Ensuring that a
write has made it all the way to a device may require that the L2
controller take some action.
There is currently only one implementation of the new function, for the
PL310 cache controller. It invokes a function that the controller
manual calls "cache sync" but it actually has nothing to do with cache at
all, it triggers a drain of all pending store buffer writes and it blocks
until they complete.
The sheeva and xscale L2 controllers (which predate the concept of Device
memory) don't seem to have a corresponding function. It appears that the
standard armv5 drain_writebuf function includes draining all the way
through the L2 controller.
|
| 265784 |
09-May-2014 |
ian |
Call idcache_inv_all from the AP core entry code before turning on the MMU.
Also, enable instruction and branch caches, which should be safe now that
they're properly initialized/invalidated first.
|
| 265705 |
08-May-2014 |
ian |
Consolitate all the AP core startup stuff under a single #ifdef SMP block.
Remove some other ifdefs that came in with a copy/paste that mean basically
"if this processor supports multicore stuff", because if you're starting up
an AP core... it does.
|
| 265694 |
08-May-2014 |
ian |
Move the mptramp code which is specific to the Marvell ArmadaXP SoC out of
the common locore.S file and into the mv/armadaxp directory.
|
| 265446 |
06-May-2014 |
ian |
Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.
|
| 265444 |
06-May-2014 |
ian |
Call platform_pl310_init() before enabling the controller, and handle the
case where the controller is already enabled.
Some of the pl310 configuration registers cannot be changed while the
controller is active, so if there is any platform-specific init to be done
it must happen before enabling the controller.
The controller should not be enabled upon entry to the kernel, but u-boot
has recently developed the bad habit of leaving caches enabled when
launching the kernel, and since we have no control over that source code
we have to do our best to cope with it. The PL310 manual doesn't document
a safe sequence for disabling the controller, but the sequence used here
(force write-through mode and disable linefill allocations, then clean and
invalidate the current contents before disabling the hardware) appears to
be sound both by analysis and empirical testing.
These changes were developed and tested in collaboration with
Svatopluk Kraus <onwahe@gmail.com>.
Reviewed by: cognet@
|
| 265441 |
06-May-2014 |
ian |
Break out the code that figures out the L2 cache geometry to its own
routine, so that it can be called from multiple places in upcoming changes.
|
| 265440 |
06-May-2014 |
ian |
Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor
style(9) nits. Use DEVMETHOD_END.
|
| 265036 |
28-Apr-2014 |
ian |
Don't use multiprocessing-extensions instruction on processors that don't
support SMP.
Submitted by: loos@
Pointy hat to: me
|
| 265035 |
27-Apr-2014 |
ian |
Move duplicated code to print l2 cache config into the common code.
|
| 265025 |
27-Apr-2014 |
ian |
Explain why wbinv_all is SMP-safe in this case, and add a missing l2 cache
flush. (Either it was missing here, or it isn't needed in the minidump
case. Adding it here seems like the safer path to consistancy.)
|
| 265024 |
27-Apr-2014 |
ian |
Flush and invalidate caches on each CPU as part of handling IPI_STOP.
Flushing the caches is required before doing a panic dump, but ARM
doesn't provide a flavor of flush that gets broadcast to other cores.
However, all cores except one are stopped before doing a dump, so this
works around the lack of a global flush/invalidate by doing it locally
on each CPU as part of stopping.
Discussed with: cognet@
|
| 265023 |
27-Apr-2014 |
ian |
There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so
map them both to the same interrupt number like other arches do.
|
| 264994 |
27-Apr-2014 |
ian |
Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores. In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).
As part of doing this, all callers of cpu_icache_sync_all() were
inspected to ensure they weren't relying on the old side effect of
doing a wbinv_all along with the icache work.
|
| 264984 |
26-Apr-2014 |
scottl |
Retire smp_active. It was racey and caused demonstrated problems with
the cpufreq code. Replace its use with smp_started. There's at least
one userland tool that still looks at the kern.smp.active sysctl, so
preserve it but point it to smp_started as well.
Discussed with: peter, jhb
MFC after: 3 days
Obtained from: Netflix
|
| 264702 |
20-Apr-2014 |
ian |
Remove uncessary cache and TLB maintenance ops.
- These were needed on armv4/5 (VIVT cache), not needed on armv6.
- The wbinv_all call can't be used on SMP systems; cache operations by
set/way are not broadcast to other cores.
- The TLB maintenance operations needed for pmap_growkernel() happen in
pmap_grow_l2_bucket(), so there's no need to flush all TLB entries at
the end.
- There may not be any need for the TLB flush at the beginning of
pmap_release(), but it's left in for now pending more investigation.
Pointed out by: Svatopluk Kraus <onwahe@gmail.com>
Discussed with: cognet@
|
| 264183 |
06-Apr-2014 |
ian |
Add a couple more required TLB flushes.
These should have been part of r264129, they are part of the overall set
of changes that got several weeks of testing. I must have fumbled them
while merging various patchsets.
|
| 264160 |
05-Apr-2014 |
rpaulo |
Remove code under PMAP_CACHE_VIVT that is not compiled anymore.
This is for ARMv4/ARMv5 and it doesn't belong in ARMv6 code.
Reviewed by: ian
|
| 264130 |
04-Apr-2014 |
ian |
Allocate per-cpu resources for doing pmap_zero_page() and pmap_copy_page().
This is performance enhancement rather than bugfix.
|
| 264129 |
04-Apr-2014 |
ian |
Fix TLB maintenance issues for armv6 and armv7.
- Add cpu_cpwait to comply with the convention.
- Add missing TLB invalidations, especially in pmap_kenter & pmap_kremove
with distinguishing between D and ID pages.
- Modify pmap init/bootstrap invalidations to ID, just to be safe.
- Fix TLB-inv and PTE_SYNC ordering.
This combines changes submitted by ian@, cognet@, and Wojciech Macek,
which have all been tested together as a unit.
|
| 264128 |
04-Apr-2014 |
ian |
Fix TTB set operation for armv7.
Perform sychronization (by "isb" barrier) after TTB is set. This
is done to ensure that TLB invalidation always executes after
TTB modification and operates on valid CP15 data (per specification).
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: ian@, cognet@
|
| 264094 |
04-Apr-2014 |
ian |
Actually save the clock frequency retrieved from fdt data. I fumbled
this when I converted getprop to getencprop.
Submitted by: Thomas Skibo
Pointy hat to: ian
|
| 264065 |
03-Apr-2014 |
br |
- Setup both secure and non-secure timer IRQs.
We don't know our ARM security state, so one of them will operate.
- Don't set frequency, since it's unpossible in non-secure state.
Only rely on DTS clock-frequency value or get clock from timer.
Discussed with: ian, cognet
|
| 264051 |
02-Apr-2014 |
ian |
Trivial changes/forced-commit to document previous change r264050 whose
description was eaten by the dog (or an editor crash or something).
Add variable-frequency support to the arm mpcore eventtimer driver.
This allows a platform's early init code to tell the mpcore driver that the
clock frequency can vary. That causes the mpcore driver to register an
eventtimer, but not a timecounter. The platform has to provide a time
counter using some other fixed-frequency clock, but can still use the
per-cpu goodness of the mpcore hardware for event timers.
When the platform support code does something to change the frequency of
the CPU clocks (power saving, thermal management) it must tell the mpcore
driver code about it using arm_tmr_change_frequency().
|
| 264050 |
02-Apr-2014 |
ian |
|
| 264049 |
02-Apr-2014 |
ian |
Disable the timer and clear any pending bit, then setup the new counter
register values, then restart the timer. This prevents a situation where
an old event fires just as we're about to load a new value into the timer,
when the start routine is called to change the time of the current event.
Also re-nest the parens properly for casting the result of converting
time and frequency to a count. This doesn't actually change the result of
the calcs, but will some day prevent a loss-of-precision warning on the
assignment, if that warning gets enabled.
|
| 263982 |
01-Apr-2014 |
br |
Add Cortex-A15 cpu id revisions.
|
| 263914 |
29-Mar-2014 |
andrew |
VFP fixes/cleanups for ARM11:
* Save the required VFP registers on context switch. If the exception bit
is set we need to save and restore the FPINST register, and if the fp2v
bit is also set we need to save and restore FPINST2.
* Move saving and restoring the floating point control registers to C.
* Clear the fpexc exception and fp2v flags on a floating-point exception.
* Signal a SIGFPE if the fpexc exception flag is set on an undefined
instruction. This is how the ARM core signals to software there is a
floating-point exception.
|
| 263913 |
29-Mar-2014 |
andrew |
Initialise fpscr to a sane value when we create the pcb. This sets NaNs to
be the default NaN and for denormalised numbers to be flushed to zero.
|
| 263620 |
22-Mar-2014 |
bdrewery |
Rename global cnt to vm_cnt to avoid shadowing.
To reduce the diff struct pcu.cnt field was not renamed, so
PCPU_OP(cnt.field) is still used. pc_cnt and pcpu are also used in
kvm(3) and vmstat(8). The goal was to not affect externally used KPI.
Bump __FreeBSD_version_ in case some out-of-tree module/code relies on the
the global cnt variable.
Exp-run revealed no ports using it directly.
No objection from: arch@
Sponsored by: EMC / Isilon Storage Division
|
| 263251 |
16-Mar-2014 |
ian |
Use armv7 TLB flush code, not arm11, for cortex-a processors.
The armv7 architecture uses a unified TLB model for maintenence ops even
if separate instruction and data TLBs are implemented in hardware. That
means that there's no distinction between the 'I' and 'D' flavors of flush,
they all use the same 'ID' implementation. On the other hand, there is a
difference between SMP and UP on armv7, but not on arm11, so use the armv7
routines for cortex-a processors.
|
| 263250 |
16-Mar-2014 |
ian |
Use the same terminology as the ARM docs in comments. No functional changes.
|
| 263233 |
16-Mar-2014 |
rwatson |
Update kernel inclusions of capability.h to use capsicum.h instead; some
further refinement is required as some device drivers intended to be
portable over FreeBSD versions rely on __FreeBSD_version to decide whether
to include capability.h.
MFC after: 3 weeks
|
| 263059 |
11-Mar-2014 |
imp |
Delete stray clause 3 (Advertising clause) and renumber while i'm
here.
Approved by: alc@
|
| 263057 |
11-Mar-2014 |
ian |
Remove #include <machine/asmacros.h> from files that don't need it.
|
| 263036 |
11-Mar-2014 |
imp |
Remove clause 3 (advertising clause), per regent's letter.
|
| 263034 |
11-Mar-2014 |
ian |
Use panic rather than printf to "handle" an arm26 address exception
(should never happen on arm32). Pass the right arguments to panic for
the reset exception (which also should never happen).
|
| 263033 |
11-Mar-2014 |
ian |
No functional changes. Rewrite comments, use tabs consistantly, reorder
some of the functions so that similar things are grouped together.
|
| 263030 |
11-Mar-2014 |
ian |
Remove some unnecessary indirection and jump right to the handler functions.
|
| 262997 |
11-Mar-2014 |
ian |
Revert r262994 for now, it fails to boot on armv5.
|
| 262995 |
11-Mar-2014 |
ian |
Now that the PUSHFRAME and PULLFRAME macros are used only in the swi
entry/exit code, they don't need to be macros. Now they're just inline
code, and rewritten to use shorter instruction sequences.
|
| 262987 |
10-Mar-2014 |
ian |
Arrange for arm fork_trampoline() to return to userland via the standard
swi_exit code in exception.S instead of having its own inline expansion
of the DO_AST and PULLFRAME macros. That means that now all references
to the PUSH/PULLFRAME and DO_AST macros are localized to exception.S,
so move the macros themselves into there and remove them from asmacros.h
|
| 262986 |
10-Mar-2014 |
ian |
Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code
using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.
|
| 262980 |
10-Mar-2014 |
ian |
Move the exception vector table (so-called "page0" data) into exception.S
and eliminate vectors.S. All low-level exception handling is now
consolidated into exception.S.
Along with moving the default FIQ handler, change it to disable FIQs
before returning. An FIQ should never happen, but if it does, it's got
to be disabled as part of ignoring it.
In general, we have hand-wavy support for FIQs that probably hasn't been
used for 10 years and probably doesn't work (almost certainly doesn't
work for SMP because it only updates the vector on the current cpu). This
change doesn't really make the overall situation any better or worse.
|
| 262979 |
10-Mar-2014 |
ian |
Eliminate irq_dispatch.S. Move the data items it contained into arm/intr.c
and the functionality it provided into arm/exception.S. Rename the main
irq handling routine from arm_handler_execute() to arm_irq_handler() to
make it more congruent with how other exception handlers are named, and
also update its signature to reflect what has long been reality: it is
passed just a trapframe pointer, no interrupt number argument.
|
| 262966 |
10-Mar-2014 |
ian |
Make the default exception handler vectors point to where I thought they
were already pointing: the default handlers (not a panic that says there
is no default handler).
|
| 262958 |
09-Mar-2014 |
ian |
Remove all traces of support for ARM chips prior to the arm9 series. We
never actually ran on these chips (other than using SA1 support in an
emulator to do the early porting to FreeBSD long long ago). The clutter
and complexity of some of this code keeps getting in the way of other
maintenance, so it's time to go.
|
| 262952 |
09-Mar-2014 |
ian |
The arm exception entry points currently vector through a function pointer
to the actual handler routine. All the pointers are static-intialized to
the only handlers available, and yet various platform-specific inits still
set those pointers (to the values they're already initialized to). Begin
to drain the swamp by removing all the redundant external declarations and
runtime setting of the pointers that's scattered around various places.
|
| 262950 |
09-Mar-2014 |
ian |
Make undefined exception entry MPSAFE.
The old code used static storage to preserve a couple registers while
setting up the trapframe for the main handler. Doing so was the last
leftover crumbs from the days when a low-level debugger was hooked into
the exception entry code.
Now the exception entry sequence is essentially the same as for the
other exceptions, which still involves needlessly indirecting through
a function pointer which points to the same code on every platform.
Removing that indirection will be handled as a separate cleanup.
This work is based on an analysis by Juergen Weiss.
|
| 262949 |
09-Mar-2014 |
ian |
When a thread begins life it doesn't own the VFP hardware state on any cpu.
|
| 262948 |
09-Mar-2014 |
ian |
Always call vfp_discard() on thread death, not just when the VFP is
enabled. In vfp_discard(), if the state in the VFP hardware belongs to
the thread which is dying, NULL out pcpu fpcurthread to indicate the
state currently in the hardware belongs to nobody.
Submitted by: Juergen Weiss
Pointy hat to: me
|
| 262942 |
09-Mar-2014 |
ian |
Remove all dregs of a per-thread undefined-exception-mode stack. This is
a leftover from the days when a low-level debugger had hooks in the
undefined exception vector and needed stack space to function. These days
it effectively isn't used because we switch immediately to the svc32 mode
stack on exception entry. For that, the single undef mode stack per core
that gets set up at init time works fine.
The stack wasn't necessary but it was harmful, because the space for it
was carved out of the normal per-thread svc32 stack, in effect cutting
that 8K stack in half. If svc32 mode used more than 4k of stack space it
wandered down into the undef mode stack, and then an undef exception would
overwrite a couple words on the stack while switching to svc32 mode,
corrupting the scv32 stack. Having another stack abut the bottom of the
svc32 stack also effectively mooted the guard page below the stack.
This work is based on analysis and patches submitted by Juergen Weiss.
|
| 262941 |
09-Mar-2014 |
ian |
Rework the VFP code that handles demand-based save and restore of state.
The old code was full of complexity that would only matter if the
kernel itself used the VFP hardware. Now that's reduced to either killing
the userland process or panicking the kernel on an illegal VFP instruction.
This removes most of the complexity from the assembler code, reducing it
to just calling the save code if the outgoing thread used the VFP.
The routine that stores the VFP state now takes a flag that indicates
whether the hardware should be disabled after saving state. Right now it
always is, but this makes the code ready to be used by get/set_mcontext()
(doing so will be addressed in a future commit).
Remove the arm-specific pc_vfpcthread from struct pcpu and use the MI
field pc_fpcurthread instead.
Reviewed by: cognet
|
| 262903 |
07-Mar-2014 |
ian |
Fix the arm sys_sigreturn(): its argument is a struct ucontext, not a
struct sigframe containing the struct ucontext.
The signal trampoline return code on the other hand DOES have just a
struct sigframe on the stack to work with, so have it get a pointer to
the ucontext out of there to pass along to sys_sigreturn.
In other words, make everything work right whether sys_sigreturn is
invoked from the trampoline or from userland code calling sigreturn(2).
Submitted by: Takashi Komatsu <komatsu.taka@jp.panasonic.com>
Reviewed by: cognet
|
| 262712 |
03-Mar-2014 |
ian |
Use the standard __used macro instead of a bare __attribute__.
Submitted by: bde
|
| 262696 |
02-Mar-2014 |
ian |
Add __attribute__((used)) so that the delay implementation doesn't get
optimized away as unreferenced, causing linker errors when trying to
resolve the weak reference to the missing function.
|
| 262587 |
28-Feb-2014 |
ian |
Add an armv7 implementation of cpu_sleep(). The arm11/armv6 implementation
we've been using was actually just spinning due to ARM having redefined
the old 'wait for interrupt' operation via the system coprocessor as a nop
and replacing it with a WFI instruction.
|
| 262584 |
28-Feb-2014 |
ian |
Supply a DELAY() implementation via weak linkage, so that SoC-specific
code can supply a better implementation. A SoC with variable CPU frequency
is likely to use a fixed-frequency timer for DELAY() (but still use the
mpcore private timers as eventtimers).
Also remove spaces from the eventtimer and timecounter names.
|
| 262583 |
28-Feb-2014 |
ian |
All our current ARM multi-core systems have all cores in one package with
a shared L2 cache, reflect that in the common cpu_topo() routine.
|
| 262534 |
26-Feb-2014 |
ian |
Replace many pasted identical definitions of cpu_initclocks() with a common
implementation in arm/machdep.c. Most arm platforms either don't need to
do anything, or just need to call the standard eventtimer init routines.
A generic implementation that does that is now provided via weak linkage.
Any platform that needs to do something different can provide a its own
implementation to override the generic one.
|
| 262426 |
24-Feb-2014 |
ian |
Invalidate caches immediately upon entry to init_secondary(). Also set
the Bufferable bit in the PDE entries of the secondary processor startup
pagetables.
The caches really need to be invalidated even earlier than this, but this
is a big step in the right direction. The invalidate needs to happen
before the MMU is enabled, which means it has to be called from asm code
that's running with physical addressing. Fixing that will be handled in
a future change.
|
| 262420 |
24-Feb-2014 |
ian |
Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support. Most chips up through
armv6 can use the armv4 implementation which has a single coprocessor
opcode for this operation. The rather more complex armv7 implementation
comes from netbsd.
|
| 262413 |
23-Feb-2014 |
ian |
Actually set the proper bit to indicate TTB shared memory.
Submitted by: Juergan Weiss
|
| 262411 |
23-Feb-2014 |
ian |
If the L2 cache type is PIPT, pass a physical address for a flush.
While this is technically more correct, I don't think it much matters,
because the only thing in the tree that calls cpu_flush_dcache() is md(4)
and I'm > 99% sure it's bogus that it does so; md has no ability to do
anything that can perturb data cache coherency.
|
| 262278 |
21-Feb-2014 |
imp |
Remove bogus blank line.
|
| 261922 |
15-Feb-2014 |
zbb |
Handle pmap_enter() on already promoted mappings for ARMv6/v7
Attempt to demote the superpage if trying to pmap_enter() on
one. Panic only when the particular superpage should
no longer exist for that pmap and address.
|
| 261921 |
15-Feb-2014 |
zbb |
Remove spurious assertion from pmap_extract_locked() on ARM
The condition under assertion is no longer valid since
superpages support is operating on section mappings.
|
| 261920 |
15-Feb-2014 |
zbb |
Avoid redundant superpage promotion attempts on ARM
Because pmap_enter_locked() is called from few different functions
some redundancy in superpage promotion attempts can be observed.
Hence, avoid promotion in pmap_enter_object() (if the object can
be mapped by superpage it will be handled by pmap_enter_object()
itself) and also do not waste time in pmap_enter_quick().
From now on the promotion will be performed only in pmap_enter().
|
| 261919 |
15-Feb-2014 |
zbb |
Fix superpage promotion on ARM with respect to RO/RW and wired attributes
It was possible to create RW superpage mapping even if
the base pages were RO due to wrong setting of the prot
flag passed to pmap_map_section().
Promotion attempt should be canceled in case of attributes
mismatch between any two base pages. Since we still use
pv_flags to maintain permission to write (PVF_WRITE) and
wired status (PVF_WIRED) for a page, it is also necessary
to take those variables into account.
|
| 261918 |
15-Feb-2014 |
zbb |
Ensure proper TLB invalidation on superpage promotion and demotion on ARM
Base pages within newly created superpage need to be invalidated so that
new mapping is "visible" immediately after creation.
|
| 261917 |
15-Feb-2014 |
zbb |
Always clear L1 PTE descriptor when removing superpage on ARM
Invalidate L1 PTE regardles of existance of the corresponding
l2_bucket. This is relevant when superpage is entered via
pmap_enter_object() and will fix crash on entering page
in place of not properly removed superpage.
|
| 261855 |
13-Feb-2014 |
andrew |
Allow the kernel to be loaded at any 1MiB address. This requirement is
because we use the 1MiB section maps as they only need a single pagetable.
To allow this we only use pc relative loads to ensure we only load from
physical addresses until we are running from a known virtual address.
As a side effect any data from before or 64MiB after the kernel needs to
be mapped in to be used. This should not be an issue for kernels loaded
with ubldr as it places this data just after the kernel. It will be a
problem when loading directly from anything using the Linux ABI that
places the ATAG data outside this range, for example U-Boot.
|
| 261810 |
12-Feb-2014 |
ian |
Use the same logic as the x86 platforms to avoid trying perform fault fixup
while in a critical section or while holding a non-sleepable lock.
Reviewed by: cognet
|
| 261808 |
12-Feb-2014 |
ian |
Use the right symbols for determining arm architecture. Include the
necessary header file which has the new FAULT_WNR symbol defined in it.
|
| 261803 |
12-Feb-2014 |
ian |
On armv6 and later, use the WriteNotRead bit of the fault status register
to decide what protections are required by the faulting access. The old
code disassembled the faulting instruction, and there are a lot of new
instructions that aren't handled. The old code is still used for armv4/5
which doesn't have the WNR bit)
|
| 261789 |
12-Feb-2014 |
imp |
Convert two while(1); statements into proper panics. Soon, kernels
with early printf support will print this info... For kernels without,
the observed behavior will be the same as it is now...
|
| 261783 |
11-Feb-2014 |
imp |
Swap PA and VA so they are in the right registers...
|
| 261677 |
09-Feb-2014 |
ian |
Add some extra debugging output when DEBUG is defined.
|
| 261676 |
09-Feb-2014 |
ian |
Fix the exclude-region clipping logic for the edge-trim case.
|
| 261663 |
09-Feb-2014 |
andrew |
Pass the pagetable used from locore.S to initarm to allow it to map data
in as required.
|
| 261657 |
09-Feb-2014 |
ian |
No need to set physmem in each initarm() instance anymore, it's handled
in common code now.
|
| 261656 |
09-Feb-2014 |
ian |
Use vm_paddr_t, not vm_offset_t, when dealing with physical addresses.
Pointed out by: alc
|
| 261651 |
09-Feb-2014 |
andrew |
Remove the now unused MMU_INIT macro.
|
| 261649 |
09-Feb-2014 |
ian |
It turns out a global variable is the only straightforward way to
communicate the kernel's physical load address from where it's known in
initarm() into cpu_mp_start() which is called from non-arm code and
takes no parameters.
This adds the global variable and ensures that all the various copies
of initarm() set it. It uses the variable in cpu_mp_start(), eliminating
the last uses of KERNPHYSADDR outside of locore.S (where we can now
calculate it instead of relying on the constant).
|
| 261648 |
09-Feb-2014 |
ian |
Calculate the kernel's load address from the PC in the elf / gzip
trampoline instead of relying on KERNPHYSADDR as a compile-time constant.
|
| 261643 |
09-Feb-2014 |
ian |
Consolidate code related to setting up physical memory configuration into
a new physmem.c file. The new code provides helper routines that can be
used by legacy SoCs and newer FDT-based systems. There are routines to
add one or more regions of physically contiguous ram, and exclude one or
more physically contiguous regions of ram. Ram can be excluded from crash
dumps, from being given over to the vm system for allocation management,
or both. After all the included and excluded regions have been added,
arm_physmem_init_kernel_globals() processes the regions into the global
dump_avail and phys_avail arrays and realmem and physmem variables that
communicate memory configuration to the rest of the kernel.
Convert all existing SoCs to use the new helper code.
|
| 261642 |
08-Feb-2014 |
ian |
Remove the ARM_USE_SMALL_ALLOC option and code related to it.
This was an optimization used only by a few xscale platforms. Part of
the optimization was to create a direct map for all physical pages, and
that resulted in making multiple mappings of pages in a way that bypassed
the logic in pmap.c to handle VIVT cache aliasing. It also just generally
made the code more complex and hard to maintain for all SoCs.
Reviewed by: cognet
|
| 261606 |
07-Feb-2014 |
andrew |
Dynamically generate the page table. This will allow us to detect the
physical address we are loaded at to change the mapping.
|
| 261596 |
07-Feb-2014 |
ian |
Remove references to PHYSADDR where it's used only in debugging output,
and where the code that references it can safely be elided if it's not
defined (meaning the code is used for legacy arm platforms that still
define the compile-time PHYSADDR but not on newer systems that calculate
the value at runtime).
|
| 261565 |
06-Feb-2014 |
andrew |
Use abp_physaddr for the physical address over KERNPHYSADDR. This helps us
remove the need to load the kernel at a fixed address.
|
| 261564 |
06-Feb-2014 |
andrew |
Fix __syscall on armeb EABI. As it returns a 64-bit value it needs to place
32-bit data in r1, not r0. 64-bit data is already packed correctly.
|
| 261563 |
06-Feb-2014 |
andrew |
Make functions only used in this file static, and remove vfp_enable as it
is unused.
|
| 261562 |
06-Feb-2014 |
andrew |
Pass the kernel physical address to initarm through the boot param struct.
|
| 261513 |
05-Feb-2014 |
nwhitehorn |
Move Open Firmware device root on PowerPC, ARM, and MIPS systems to
a sub-node of nexus (ofwbus) rather than direct attach under nexus. This
fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier.
SPARC is unchanged.
Reviewed by: imp, ian
|
| 261419 |
02-Feb-2014 |
cognet |
Only use the CPU ID register if SMP is defined. Some non-MPCore armv6 cpu,
such as the one found in the RPi, don't have it, and just hang when we try
to access it.
|
| 261418 |
02-Feb-2014 |
cognet |
Invalidate cachelines for bounce pages on PREREAD too, there may still be
stale entries from a previous transfer.
|
| 261415 |
02-Feb-2014 |
cognet |
Change the way pcpu and curthread are stored per-core:
the old way was to store pcpu in a register, and get curthread from pcpu,
which is not very atomic, and led to issues if the thread was migrated
to another core between the time we got the pcpu address and the time we
got curthread.
Instead, we now store curthread where pcpu used to be store, and we
calculate the pcpu address based on the cpu id.
|
| 261410 |
02-Feb-2014 |
ian |
Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.
Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352. Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.
Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
|
| 261404 |
02-Feb-2014 |
nwhitehorn |
Fix one remnant endian flaw here. The back-and-forth endian conversions are
confusing.
|
| 261396 |
02-Feb-2014 |
nwhitehorn |
Fix typo. Sorry for breakage!
|
| 261393 |
02-Feb-2014 |
ian |
Update all arm code that manipulates the PSR registers to use modern syntax.
It turns out the version of gas we're using interprets the old '_all' mask
as 'fc' instead of 'fsxc'. That is, "all" doesn't really mean "all".
This was the cause of the "wrong-endian register restore" bug that's
been causing problems with some cortex-a9 chips. The 'endian' bit in the
spsr register would never get changed (it falls into the 'x' mask group)
and the first return-from-exception would fail if the chip had powered on
with garbage in the spsr register that included the big-endian bit. It's
unknown why this affected only certain cortex-a9 chips.
|
| 261351 |
01-Feb-2014 |
nwhitehorn |
Open Firmware interrupt specifiers can consist of arbitrary-length byte
strings and include arbitrary information (IRQ line/domain/sense). When the
ofw_bus_map_intr() API was introduced, it assumed that, as on most systems,
these were either 1 cell, containing an interrupt line, or 2, containing
a line number plus a sense code. It turns out a non-negligible number of
ARM systems use 3 (or even 4!) cells for interrupts, so make this more
general.
|
| 261336 |
31-Jan-2014 |
imp |
Fix silly typo...
|
| 261252 |
28-Jan-2014 |
imp |
Fix clang warning.
|
| 261227 |
28-Jan-2014 |
andrew |
Remove STARTUP_PAGETABLE_ADDR from the ARM configs and replace it with
memory at the end of the kernel.
This helps reduce the SoC and board specific configuration required.
Reviewed by: bsdimp
Tested by: jmg (armeb), br
|
| 261214 |
27-Jan-2014 |
imp |
Remove extra parens to silence clang warning.
|
| 261039 |
22-Jan-2014 |
imp |
Add support for mapping a small range of the SoC devices for debugging
purposes early in boot.
|
| 260490 |
09-Jan-2014 |
ian |
Add a function to print the contents of the static device mapping table,
and invoke it for bootverbose logging, and also from a new DDB command,
"show devmap". Also tweak the format string for the bootverbose output
of physical memory chunks to get the leading zeros in the hex values.
|
| 260375 |
06-Jan-2014 |
andreast |
Fix arm build.
Reviewed by: ian, zbb
|
| 260373 |
06-Jan-2014 |
ian |
Don't try to find a static mapping before calling pmap_mapdev(), that logic
is now part of pmap_mapdev() and doesn't need to be duplicated here.
Likewise for unmapping.
|
| 260372 |
06-Jan-2014 |
ian |
Allow 'no static device mappings' to potentially work. It's not clear that
every arm system must have some static mappings to work correctly (although
currently they all do), so remove some panic() calls (which would never
been seen anyway, because they would happen before a console is available).
|
| 260327 |
05-Jan-2014 |
nwhitehorn |
Retire machine/fdt.h as a header used by MI code, as its function is now
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
(aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
requests to its parent (nexus). This allows x86 FDT devices to allocate
both memory and IO requests and removes the last notionally MI use of
fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
|
| 260288 |
04-Jan-2014 |
ian |
In pmap_mapdev(), first check whether a static mapping exists, and if so
use it rather than allocating kva space and making another mapping. In
pmap_unmapdev(), don't unmap/free if the mapping is static.
|
| 260283 |
04-Jan-2014 |
ian |
Use bus_space_map() rather than pmap_mapdev() in nexus_activate_resource(),
when running on FDT systems. Unmap memory in nexus_deactivate_resource().
Also, call rman_activate_resource() before mapping device memory, and only
do the mapping if it returns success.
Reviewed by: nwhitehorn
|
| 260281 |
04-Jan-2014 |
nwhitehorn |
Implement OFW_BUS_MAP_INTR() in terms of the FDT PIC table, which will
become an ARM-specific quirk.
|
| 260161 |
01-Jan-2014 |
zbb |
Add polarity and level support to ARM GIC
Add suport for setting triggering level and polarity in GIC.
New function pointer was added to nexus which corresponds
to the function which sets level/sense in the hardware (GIC).
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
|
| 259936 |
27-Dec-2013 |
adrian |
Revert r252694 - which attempted to fix bit emulation for armv6/armv7.
This seems to cause issues with jemalloc + {dhclient, sshd}.
Thus, revert this for now until the root cause can be found and
fixed.
This should quieten some runtime problems with the Raspberry Pi.
PR: kern/185046
MFC after: 3 days
|
| 259640 |
20-Dec-2013 |
ganbold |
Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in
Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural
similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded
boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064.
Approved by: stas (mentor)
|
| 259202 |
10-Dec-2013 |
jhb |
Correct license statements to reflect the fact that these files were all
derived from sys/arm/mv/bus_space.c.
Approved by: core
|
| 258845 |
02-Dec-2013 |
zbb |
Enable missing Access Flag for secondary cores on ARMv6/v7
Spotted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
> Description of fields to fill in above: 76 columns --|
> PR: If a GNATS PR is affected by the change.
> Submitted by: If someone else sent in the change.
> Reviewed by: If someone else reviewed your modification.
> Approved by: If you needed approval for this commit.
> Obtained from: If the change is from a third party.
> MFC after: N [day[s]|week[s]|month[s]]. Request a reminder email.
> Security: Vulnerability reference (one per line) or description.
> Empty fields above will be automatically removed.
M sys/arm/arm/locore.S
|
| 258787 |
01-Dec-2013 |
eadler |
r258780 should not have applied to .S files.
Reported by: jmallett
|
| 258780 |
30-Nov-2013 |
eadler |
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky
Reviewed by: cperciva
|
| 258742 |
29-Nov-2013 |
ian |
Set the PGA_WRITEABLE flag when the protections indicate write access, not
just when the current access is a write.
Reviewed by: zbb@
|
| 258410 |
20-Nov-2013 |
cognet |
In pmap_unmapdev(), remember the size, and use that as an argument to
kva_free(), or we'd end up always passing it a size of 0, and for some
strange reason it doesn't seem to like it.
|
| 258392 |
20-Nov-2013 |
ian |
Call cpu_setup() immediately after the page tables are installed. This
enables data cache and other chip-specific features. It was previously
done via an early SYSINIT, but it was being done after pmap and vm setup,
and those setups need to use mutexes. On some modern ARM platforms,
the ldrex/strex instructions that implement mutexes require the data cache
to be enabled.
A nice side effect of enabling caching earlier is that it eliminates the
multi-second pause that used to happen early in boot while physical memory
and pmap and vm were being set up. On boards with 1 GB or more of ram
this pause was very noticible, sometimes 5-6 seconds.
PR: arm/183740
|
| 258359 |
19-Nov-2013 |
zbb |
Apply access flags for managed and unmanaged pages properly on ARMv6/v7
When entering a mapping via pmap_enter() unmanaged pages ought to be
naturally excluded from the "modified" and "referenced" emulation.
RW permission should be granted implicitly when requested,
otherwise unmanaged page will not recover from the permission fault
since there will be no PV entry to indicate that the page can be written.
In addition, only managed pages that participate in "modified"
emulation need to be marked as "dirty" and "writeable" when entered
with RW permissions. Likewise with "referenced" flag for managed pages.
Unmanaged ones however should not be marked as such.
Reviewed by: cognet, gber
|
| 258358 |
19-Nov-2013 |
zbb |
Avoid clearing EXEC permission bit when setting the page RW on ARMv6/v7
When emulating modified bit the executable attribute was cleared by
mistake when calling pmap_set_prot(). This was not a problem before
changes to ref/mod emulation since all the pages were created RW basing
on the "prot" argument in pmap_enter(). Now however not all pages are RW
and the RW permission can be cleared in the process.
Added proper KTRs accordingly.
Spotted by: cognet
Reviewed by: gber
|
| 258287 |
17-Nov-2013 |
alc |
Implement pmap_align_superpage().
MFC after: 6 weeks
|
| 258240 |
16-Nov-2013 |
ian |
In the data abort handler, don't panic if kdb is available and says it
handled the condition.
PR: arm/183668
Submitted by: Howard Su <howard0su@gmail.com>
|
| 257857 |
08-Nov-2013 |
alc |
Eliminate an unused macro.
|
| 257738 |
06-Nov-2013 |
ray |
Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs.
Tested by: ian, ray
|
| 257702 |
05-Nov-2013 |
nwhitehorn |
Teach nexus(4) about Open Firmware (e.g. FDT) on ARM and MIPS, retiring
fdtbus in most cases. This brings ARM and MIPS more in line with existing
Open Firmware platforms like sparc64 and powerpc, as well as preventing
double-enumeration of the OF tree on embedded PowerPC (first through nexus,
then through fdtbus).
This change is also designed to simplify resource management on FDT platforms
by letting there exist a platform-defined root bus resource_activate() call
instead of replying on fdtbus to do the right thing through fdt_bs_tag.
The OFW_BUS_MAP_INTR() and OFW_BUS_CONFIG_INTR() kobj methods are also
available to implement for similar purposes.
Discussed on: -arm, -mips
Tested by: zbb, brooks, imp, and others
MFC after: 6 weeks
|
| 257676 |
05-Nov-2013 |
ian |
Style and comment tweaks, no functional changes.
|
| 257673 |
05-Nov-2013 |
ian |
Add new helper routines for arm static device mapping. The new code
allocates kva space from the top down for the device mappings and builds
entries in an internal table which is automatically used later by
arm_devmap_bootstrap(). The platform code just calls the new
arm_devmap_add_entry() function as many times as it needs to (up to 32
entries allowed; most platforms use 2 or 3 at most).
There is also a new arm_devmap_lastaddr() function that returns the lowest
kva address allocated; this can be used to implement initarm_lastaddr()
which is used to initialize vm_max_kernel_address.
The new code is based on a similar concept developed for the imx family
SoCs recently. They will soon be converted to use this new common code.
|
| 257669 |
05-Nov-2013 |
ian |
Call initarm_lastaddr() later in the init sequence, after establishing
static device mappings, rather than as the first of the initializations
that a platform can hook into. This allows a platform to allocate KVA
from the top of the address space downwards for things like static device
mapping, and return the final "last usable address" result after that and
other early init work is done.
Because some platforms were doing work in initarm_lastaddr() that needs to
be done early, add a new initarm_early_init() routine and move the early
init code to that routine on those platforms.
Rename platform_devmap_init() to initarm_devmap_init() to match all the
other init routines called from initarm() that are designed to be
implemented by platform code.
Add a comment block that explains when these routines are called and the
type of work expected to be done in each of them.
|
| 257660 |
04-Nov-2013 |
ian |
Move remaining code and data related to static device mapping into the
new devmap.[ch] files. Emphasize the MD nature of these things by using
the prefix arm_devmap_ on the function and type names (already a few of
these things found their way into MI code, hopefully it will be harder to
do by accident in the future).
|
| 257648 |
04-Nov-2013 |
ian |
Begin reducing code duplication in arm pmap.c and pmap-v6.c by factoring
out common code related to mapping device memory into a new devmap.c file.
Remove the growing duplication of code that used pmap_devmap_find_pa() and
then did some math with the returned results to generate a virtual address,
and likewise in reverse to get a physical address. Now there are a pair
of functions, arm_devmap_vtop() and arm_devmap_ptov(), to do that. The
bus_space_map() implementations are rewritten in terms of these.
|
| 257419 |
31-Oct-2013 |
ian |
Do not EOI an interrupt until the point after the filter handlers / before
threaded handlers.
It's not easy to see from the diffs of this change exactly how it
accomplishes the above. The arm_mask_irq() and arm_unmask_irq() functions
are, respectively, the pre_thread and post_thread hooks. Not seen in
these diffs, the arm_post_filter() routine also EOIs. The post_filter
routine runs after filter handlers if there will be no threaded handlers,
so it just EOIs. The pre_thread routine masks the interrupt (at the
controller, not the source) and EOIs. So one way or another, the EOI
happens at the point where filter handlers are done.
|
| 257281 |
28-Oct-2013 |
zbb |
Remove not working and deprecated PJ4Bv6 support
Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada
SoC family. Current in-tree support for PJ4Bv6 will not work and also
there should be no platforms in active use that would incorporate that
CPU revision.
|
| 257278 |
28-Oct-2013 |
zbb |
Remove hard-coded mappings related to Armada XP support
Armada XP initialization flow requires SoC registers to be
mapped very early in order to configure Snoop Filter for SMP.
Additional mapping in locore.S is redundant as proper mapping is
made in pmap_devmap_bootstrap() prior to calling cpu_setup() which
configures the Snoop Filter.
For secondaru CPUs it is better to pass VA of the SoC
registers defined in MV_BASE and PA consistent with the value
in the Device Tree.
Tested by: kevlo
|
| 257228 |
27-Oct-2013 |
kib |
Add bus_dmamap_load_ma() function to load map with the array of
vm_pages. Provide trivial implementation which forwards the load to
_bus_dmamap_load_phys() page by page. Right now all architectures use
bus_dmamap_load_ma_triv().
Tested by: pho (as part of the functional patch)
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
|
| 257217 |
27-Oct-2013 |
ian |
Remove the last dregs of trapframe_t. It turns out only arm was using
this type, so remove it to make arm code more consistant with other
platforms. Thanks to bde@ for pointing out only arm used trapframe_t.
|
| 257203 |
27-Oct-2013 |
ian |
Eliminate a compiler warning about extraneous parens.
|
| 257201 |
27-Oct-2013 |
ian |
Retire arm_remap_nocache() and the data and constants associated with it.
The only remaining user was the code that allocates bounce pages for armv4
busdma. It's not clear why bounce pages would need uncached memory, but
if that ever changes, kmem_alloc_attr() would be the way to get it.
|
| 257200 |
27-Oct-2013 |
ian |
Remove #include <machine/frame.h> from all the arm code that doesn't
really need it. That would be almost everywhere it was included. Add
it in a couple files that really do need it and were previously getting
it by accident via another header.
|
| 257199 |
27-Oct-2013 |
ian |
Remove all #include <machine/pmap.h> from arm code. It's already
included by vm/pmap.h, which is a prerequisite for arm/machine/pmap.h
so there's no reason to ever include it directly.
Thanks to alc@ for pointing this out.
|
| 256941 |
22-Oct-2013 |
cognet |
Try to make sure the frame is indeed in the kernel memory.
|
| 256756 |
18-Oct-2013 |
cognet |
There's no need to guard pmap_extract(), it won't be called until well after
the VM has been properly initialized.
Spotted out by: alc
|
| 256748 |
18-Oct-2013 |
cognet |
KERNBASE is unsigned, so we'd better use hs instead of ge.
Pointy hat to: cognet
Suggested by: ian
|
| 256707 |
17-Oct-2013 |
cognet |
- Switch to use WBWA mappings for page tables on armv6, this is needed for SMP.
- Fix PTE_SYNC() for PIPT L2 caches, using the virtual address wasn't so useful.
- Use PTE_SYNC() for >= armv6
|
| 256691 |
17-Oct-2013 |
cognet |
Make casuword() atomic for armv6
|
| 256672 |
17-Oct-2013 |
cognet |
If we avoid to use the page at addr 0, we should adjust the size to reflect it.
|
| 256647 |
16-Oct-2013 |
ian |
Invalidate the entire L2 cache before enabling it. Say whether it
has been enabled or disabled.
|
| 256638 |
16-Oct-2013 |
ian |
Add cases for the combinations of busdma sync op flags that we handle
correctly by doing nothing, then add a panic for the default case, because
that implies that some driver asked for a sync (probably incorrectly) and
nothing was done.
|
| 256637 |
16-Oct-2013 |
ian |
When calculating the number of bounce pages needed, round the maxsize
up to a multiple of PAGE_SIZE, and add one page because there can always
be one more boundary crossing than the number of pages in the transfer.
|
| 256629 |
16-Oct-2013 |
br |
Add CPU ID for ARM Cortex A5.
Approved by: cognet (mentor)
|
| 256628 |
16-Oct-2013 |
ian |
Fix a register name typo. The effect was that CPU_CONTROL_AFLT_ENABLE
wasn't being set, but it was almost assuredly already turned on anyway
by the bootloader.
|
| 255786 |
22-Sep-2013 |
glebius |
- Create kern.ipc.sendfile namespace, and put the new "readhead" OID
there as "kern.ipc.sendfile.readahead".
- Push all nsfbuf related tunables into MD code. Don't move them
to new namespace in favor of POLA.
Reviewed by: scottl
Approved by: re (gjb)
|
| 255738 |
20-Sep-2013 |
zbb |
Fix GCC build for all ARMs. Revert bug introduced in r255613.
Previous change applied in r255613 fixed build for ARMv6 but
broke it for previous architecture revisions. This commit
eventually fixes GCC build for all ARM revisions.
Approved by: cognet (mentor)
Approved by: re (kib)
|
| 255724 |
20-Sep-2013 |
alc |
The pmap function pmap_clear_reference() is no longer used. Remove it.
pmap_clear_reference() has had exactly one caller in the kernel for
several years, more precisely, since FreeBSD 8. Now, that call no
longer exists.
Approved by: re (kib)
Sponsored by: EMC / Isilon Storage Division
|
| 255677 |
18-Sep-2013 |
pjd |
Fix panic in ktrcapfail() when no capability rights are passed.
While here, correct all consumers to pass NULL instead of 0 as we pass
capability rights as pointers now, not uint64_t.
Reported by: Daniel Peyrolon
Tested by: Daniel Peyrolon
Approved by: re (marius)
|
| 255613 |
16-Sep-2013 |
zbb |
Fix GCC build error when building for ARMv6
Apply theravens's idea to move __strong_reference
macros into the proper ifdef section.
Approved by: cognet (mentor)
Approved by: re
|
| 255612 |
16-Sep-2013 |
zbb |
Implement pmap_advise() for ARMv6/v7 pmap module
Apply the given advice to the specified range of addresses within the
given pmap. Depending on the advice, clear the referenced and/or
modified flags in each mapping. Superpage within the given range will
be demoted or destroyed.
Reviewed by: alc
Approved by: cognet (mentor)
Approved by: re
|
| 255611 |
16-Sep-2013 |
zbb |
Write protect base page after superpage demotion so that it may repromote
When clearing the modification status of the superpage, one of the
base pages produced during demotion should be marked as write disabled.
The intention is that subsequent write access may repromote.
In the current implementation this was done wrong as write permission was
granted instead of forbidden.
Approved by: cognet (mentor)
Approved by: re
|
| 255092 |
31-Aug-2013 |
theraven |
Unconditionally compile the __sync_* atomics support functions into compiler-rt
for ARM.
This is quite ugly, because it has to work around a clang bug that does not
allow built-in functions to be defined, even when they're ones that are
expected to be built as part of a library.
Reviewed by: ed
|
| 255091 |
31-Aug-2013 |
rpaulo |
Fix a typo in a comment.
|
| 255028 |
29-Aug-2013 |
alc |
Significantly reduce the cost, i.e., run time, of calls to madvise(...,
MADV_DONTNEED) and madvise(..., MADV_FREE). Specifically, introduce a new
pmap function, pmap_advise(), that operates on a range of virtual addresses
within the specified pmap, allowing for a more efficient implementation of
MADV_DONTNEED and MADV_FREE. Previously, the implementation of
MADV_DONTNEED and MADV_FREE relied on per-page pmap operations, such as
pmap_clear_reference(). Intuitively, the problem with this implementation
is that the pmap-level locks are acquired and released and the page table
traversed repeatedly, once for each resident page in the range
that was specified to madvise(2). A more subtle flaw with the previous
implementation is that pmap_clear_reference() would clear the reference bit
on all mappings to the specified page, not just the mapping in the range
specified to madvise(2).
Since our malloc(3) makes heavy use of madvise(2), this change can have a
measureable impact. For example, the system time for completing a parallel
"buildworld" on a 6-core amd64 machine was reduced by about 1.5% to 2.0%.
Note: This change only contains pmap_advise() implementations for a subset
of our supported architectures. I will commit implementations for the
remaining architectures after further testing. For now, a stub function is
sufficient because of the advisory nature of pmap_advise().
Discussed with: jeff, jhb, kib
Tested by: pho (i386), marcel (ia64)
Sponsored by: EMC / Isilon Storage Division
|
| 254918 |
26-Aug-2013 |
raj |
Introduce superpages support for ARMv6/v7.
Promoting base pages to superpages can increase TLB coverage and allow for
efficient use of page table entries. This development provides FreeBSD/ARM
with superpages management mechanism roughly equivalent to what we have for
i386 and amd64 architectures.
1. Add mechanism for automatic promotion of 4KB page mappings to 1MB section
mappings (and demotion when not needed, respectively).
2. Managed and non-kernel mappings are now superpages-aware.
3. The functionality can be enabled by setting "vm.pmap.sp_enabled" tunable to
a non-zero value (either in loader.conf or by modifying "sp_enabled"
variable in pmap-v6.c file). By default, automatic promotion is currently
disabled.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: alc
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254913 |
26-Aug-2013 |
raj |
Add missing TAILQ initializer (omitted in r250634).
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: alc
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254901 |
26-Aug-2013 |
andrew |
Revert r251370 as it contains a deadlock.
|
| 254847 |
25-Aug-2013 |
andrew |
Add the frame information to cpu_switch to allow us to unwind out of it,
for example when dumping threads in the kernel debugger.
|
| 254845 |
25-Aug-2013 |
andrew |
Add the unwind information to irq_entry so we can pass through it when
unwinding the stack.
|
| 254667 |
22-Aug-2013 |
kib |
Revert r254501. Instead, reuse the type stability of the struct pmap
which is the part of struct vmspace, allocated from UMA_ZONE_NOFREE
zone. Initialize the pmap lock in the vmspace zone init function, and
remove pmap lock initialization and destruction from pmap_pinit() and
pmap_release().
Suggested and reviewed by: alc (previous version)
Tested by: pho
Sponsored by: The FreeBSD Foundation
|
| 254536 |
19-Aug-2013 |
raj |
Do not use pv_kva on ARMv6/v7 and save some space on each vm_page. It's only
relevant for older ARM variants (with virtual cache).
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: gber
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254535 |
19-Aug-2013 |
raj |
Simplify and clean up pmap_clearbit()
There is no need for calling vm_page_dirty() when clearing "modified" flag as
it is already set for that page in pmap_fault_fixup() or pmap_enter() thanks
to "modified" bit emulation.
Also, there is no need for checking PTE "referenced" or "writeable" flags. If
there is a request to clear a particular flag we should just do it.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: gber
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254533 |
19-Aug-2013 |
raj |
Fix ARMv6/v7 mapping's wired status.
Last input argument in pmap_modify_pv() should be a mask of flags to be set.
In pmap_change_wiring() however, the straight wired status was used, which
does not represent valid flags (and is of type boolean).
This commit fixes the issue so that wired flag is passed to pmap_modify_pv()
properly.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: gber
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254532 |
19-Aug-2013 |
raj |
Clear all L2 PTE protection bits before their configuration.
Revise L2_S_PROT_MASK to include all of the protection bits. Notice that
clearing these bits does not always take away the corresponding permissions
(for example, permission is granted when the bit is cleared). The bits are
cleared but are to be set or left cleared accordingly in pmap_set_prot(),
pmap_enter_locked(), etc.
Clear L2_XN along with L2_S_PROT_MASK in pmap_set_prot() so that all
permissions related bits are cleared before actual configuration.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: gber
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254531 |
19-Aug-2013 |
raj |
Simplify pv_entry removal or ARMv6/v7:
- PGA_WRITEABLE indicates that there *might be* a writable mapping for the
particular page, so to avoid frequent sweeping of the pv_entries whenever
pmap_nuke_pv(), pmap_modify_pv(), etc. is called, it is sufficient to
clear that flag if there are no managed mappings for that page anymore
(notice that only pmap_enter is authorized to set this flag).
- Avoid redundant checking for PVF_WIRED flag when this flag cannot be set
anyway.
- Clear PGA_WRITEABLE only once for each vm_page instead of multiple,
redundant clearing it in loop when there are no writeable mappings
to that page anymore.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: gber
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254461 |
17-Aug-2013 |
andrew |
Rename device vfp to option VFP and retire the ARM_VFP_SUPPORT option. This
simplifies enabling as previously both options were required to be enabled,
now we only need a single option.
While here enable VFP on the PandaBoard.
|
| 254454 |
17-Aug-2013 |
andrew |
Remove the ARMFPE option. It is unsupported, and appears to be broken as
arm_fpe_core_changecontext is not a function.
|
| 254451 |
17-Aug-2013 |
andrew |
Remove unused FPE code. This is not enabled anywhere as it is the only
file I can find containing FAST_FPE. It appears this would not work as
want_resched is not defined anywhere.
|
| 254229 |
11-Aug-2013 |
cognet |
Only allocate 2 bounce pages for maps that can only use them for buffers that
are unaligned on cache lines boundary, as we will never need more.
|
| 254165 |
09-Aug-2013 |
cognet |
- The address lies in the bus space handle, not in the cookie
- Use the right address when calling kva_free()
|
| 254138 |
09-Aug-2013 |
attilio |
The soft and hard busy mechanism rely on the vm object lock to work.
Unify the 2 concept into a real, minimal, sxlock where the shared
acquisition represent the soft busy and the exclusive acquisition
represent the hard busy.
The old VPO_WANTED mechanism becames the hard-path for this new lock
and it becomes per-page rather than per-object.
The vm_object lock becames an interlock for this functionality:
it can be held in both read or write mode.
However, if the vm_object lock is held in read mode while acquiring
or releasing the busy state, the thread owner cannot make any
assumption on the busy state unless it is also busying it.
Also:
- Add a new flag to directly shared busy pages while vm_page_alloc
and vm_page_grab are being executed. This will be very helpful
once these functions happen under a read object lock.
- Move the swapping sleep into its own per-object flag
The KPI is heavilly changed this is why the version is bumped.
It is very likely that some VM ports users will need to change
their own code.
Sponsored by: EMC / Isilon storage division
Discussed with: alc
Reviewed by: jeff, kib
Tested by: gavin, bapt (older version)
Tested by: pho, scottl
|
| 254061 |
07-Aug-2013 |
cognet |
Don't bother trying to work around buffers which are not aligned on a cache
line boundary. It has never been 100% correct, and it can't work on SMP,
because nothing prevents another core from accessing data from an unrelated
buffer in the same cache line while we invalidated it. Just use bounce pages
instead.
Reviewed by: ian
Approved by: mux (mentor) (implicit)
|
| 254025 |
07-Aug-2013 |
jeff |
Replace kernel virtual address space allocation with vmem. This provides
transparent layering and better fragmentation.
- Normalize functions that allocate memory to use kmem_*
- Those that allocate address space are named kva_*
- Those that operate on maps are named kmap_*
- Implement recursive allocation handling for kmem_arena in vmem.
Reviewed by: alc
Tested by: pho
Sponsored by: EMC / Isilon Storage Division
|
| 253985 |
06-Aug-2013 |
andrew |
We no longer need to align the stack before calling swi_handler as it is
already aligned correctly in the PUSHFRAME macro.
|
| 253971 |
05-Aug-2013 |
cognet |
Let the platform calculate the timer frequency at runtime, and use that for
the omap4, instead of relying on the (wrong) value provided in the dts.
|
| 253968 |
05-Aug-2013 |
andrew |
When entering exception handlers we may not have an aligned stack. This is
because an exception may happen at any time. The stack alignment rules on
ARM EABI state the only place the stack must be 8-byte aligned is on a
function boundary.
If an exception happens while a function is setting up or tearing down it's
stack frame it may not be correctly aligned. There is also no requirement
for it to be when the function is a leaf node.
The fix is to align the stack after we have stored a backup of the old stack
pointer, but before we have stored anything in the trapframe. Along with
this we need to adjust the size of the trapframe by 4 bytes to ensure the
stack below it is also correctly aligned.
|
| 253896 |
02-Aug-2013 |
cognet |
Only receive the interrupts on the first core, to avoid duplicate interrupts.
|
| 253857 |
01-Aug-2013 |
ganbold |
Add identification for Cortex-A7 (R0) cores.
Reviewed by: cognet@
|
| 253788 |
29-Jul-2013 |
cognet |
The errata 727915 requires a different workaround for r2p0, we have to
explicitely clean/invalidate every cache line using way/set operations.
|
| 253787 |
29-Jul-2013 |
cognet |
Remove useless cache operations.
|
| 253400 |
16-Jul-2013 |
andrew |
Fix vfp:
- We should check is_d32 to see howmany registers we have
- In vfp_restore mark vfpscr as an output register
Without the second part it appears we can return the incorrect value from
vfp_bounce if the VFP condition flags are set as it may override the
register holding the return value.
|
| 253351 |
15-Jul-2013 |
ae |
Introduce new structure sfstat for collecting sendfile's statistics
and remove corresponding fields from struct mbstat. Use PCPU counters
and SFSTAT_INC() macro for update these statistics.
Discussed with: glebius
|
| 253309 |
13-Jul-2013 |
rpaulo |
Indent the "scp=... rlv=..." to make it easier to read the backtrace.
|
| 253142 |
10-Jul-2013 |
ray |
Remove trailing whitespaces.
|
| 253052 |
09-Jul-2013 |
emaste |
Remove extraneous format string converison specifier
Submitted by: wxs@
|
| 253005 |
07-Jul-2013 |
rpaulo |
Another warning.
|
| 252997 |
07-Jul-2013 |
rpaulo |
armadaxp_idcache_wbinv_all() is in this file.
|
| 252996 |
07-Jul-2013 |
rpaulo |
Fix all the compiler warnings in elf_trampoline.c.
|
| 252837 |
05-Jul-2013 |
andrew |
Fix the build with gcc.
Gcc outputs pre-UAL asm and expects the ldcl instruction with a condition
in the form ldc<c>l, where the code produces the instruction in the UAL
form ldcl<c>. Work around this by checking if we are using clang or gcc and
adjusting the instruction.
While here correct the cmp instruction's value to include the # before the
immediate value.
|
| 252780 |
05-Jul-2013 |
ray |
o Make fields names short.
o Slim down reg fields comments.
|
| 252695 |
04-Jul-2013 |
gber |
Remove redundant clearing of the PGA_WRITEABLE flag in
pmap_remove_all()
This flag should already be cleared by pmap_nuke_pv()
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 252694 |
04-Jul-2013 |
gber |
Fix modified bit emulation for ARMv6/v7
When doing pmap_enter_locked(), enable write permission only when access
type indicates attempt to write. Otherwise, leave the page read only but
mark it writable in pv_flags.
This will result in:
1. Marking page writable during pmap_enter() but only when ensured that it
will be written right away so that we will not get redundant permissions
fault on write attempt.
2. Keeping page read only when it is permitted to be written but there was
no actual write attempt. Hence, we will get permissions fault on write
access and mark page writable in pmap_fault_fixup() what will indicate
modification status.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 252652 |
03-Jul-2013 |
gonzo |
Fix one of INVARIANTS-related UMA panics on ARM
Force UMA zone to allocate service structures like slabs using own
allocator. uma_debug code performs atomic ops on uma_slab_t fields
and safety of this operation is not guaranteed for write-back caches
|
| 252427 |
30-Jun-2013 |
ray |
Replace some spaces to tab.
|
| 252425 |
30-Jun-2013 |
ray |
Decrypt magic numbers - define names for fields of Generic Timer's CNTKCTL reg.
Submitted by: Ruslan Bukin <br@bsdpad.com>
|
| 252424 |
30-Jun-2013 |
cognet |
In generic_bs_map(), use kmem_alloc_nofault() instead of kmem_alloc(), as we
only need virtual addresses.
Submitted by: alc
|
| 252372 |
29-Jun-2013 |
ray |
Add ARM Generic Timer driver.
Submitted by: Ruslan Bukin <br@bsdpad.com>
|
| 252370 |
29-Jun-2013 |
ray |
o Initialize interrupt groups as Group 0 (secure interrupts).
o Minor cleanup.
Submitted by: Ruslan Bukin <br@bsdpad.com>
|
| 252361 |
28-Jun-2013 |
ray |
Add identification for Cortex-A15 (R0) cores.
Submitted by: Ruslan Bukin <br@bsdpad.com>
|
| 252320 |
27-Jun-2013 |
andrew |
Support reading registers r0-r3 when unwinding. There is a seperate
instruction to load these. We only hit it when unwinding past an trap frame
as in C r0-r3 would never have been saved onto the stack.
|
| 252311 |
27-Jun-2013 |
andrew |
Add UNWINDSVCFRAME to provide the unwind pseudo ops to allow us to unwind
past a trapframe.
Use this macro in exception_exit as it is the function the unwinder enters
as the functions that store the frame setting lr to point to it.
|
| 251781 |
15-Jun-2013 |
ed |
Make support for atomics on ARM complete.
Provide both __sync_*-style and __atomic_*-style functions that perform
the atomic operations on ARMv5 by using Restartable Atomic Sequences.
While there, clean up some pieces of code where it's sufficient to use
regular uint32_t to store register contents and don't need full reg_t's.
Also sync this back to the MIPS code.
|
| 251712 |
13-Jun-2013 |
andrew |
Fix the vfp code to work with the 16 register variants of the VFP unit. We
check which variant we are on, and if it is a VFPv3 or v4, and has 32
double registers we save these. This fixes VFP support on Raspberry Pi.
While here clean fmrx and fmxr up to use the register names from vfp.h
as opposed to the raw register names.
|
| 251695 |
13-Jun-2013 |
ed |
Add C11 atomic fallbacks for ARM.
Basically the situation is as follows:
- When using Clang + armv6, we should not need any intrinsics. It should
support it, even though due to a target misconfiguration it does not.
We should fix this in Clang.
- When using Clang + noarmv6, provide __atomic_* functions that disable
interrupts.
- When using GCC + armv6, we can provide __sync_* intrinsics, similar to
what we did for MIPS. As ARM and MIPS are quite similar, simply base
this implementation on the one I did for MIPS.
- When using GCC + noarmv6, disable the interrupts, like we do for
Clang.
This implementation still lacks functions for noarmv6 userspace. To be
done.
|
| 251370 |
04-Jun-2013 |
gber |
Implement pmap_copy() for ARMv6/v7.
Copy the given range of mappings from the source map to the
destination map, thereby reducing the number of VM faults on fork.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250931 |
23-May-2013 |
gber |
Rework and organize pmap_enter_locked() function.
pmap_enter_locked() implementation was very ambiguous and confusing.
Rearrange it so that each part of the mapping creation is separated.
Avoid walking through the redundant conditions.
Extract vector_page specific PTE setup from normal PTE setting.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250930 |
23-May-2013 |
gber |
Stop using PVF_MOD, PVF_REF & PVF_EXEC flags in pv_entry, use PTE.
Using PVF_MOD, PVF_REF and PVF_EXEC is redundant as we can get the proper
info from PTE bits.
When the mapping is marked as executable and has been referenced we assume
that it has been executed. Similarly, when the mapping is set to be writable
and is referenced, it must have been due to write access to it.
PVF_MOD and PVF_REF flags are kept just for pmap_clearbit() usage,
to pass the information on which bit should be cleared.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250929 |
23-May-2013 |
gber |
Improve, optimize and clean-up ARMv6/v7 memory management related code.
Use pmap_find_pv if needed instead of multiplying its code throughout
pmap-v6.
Avoid possible NULL pointer dereference in pmap_enter_locked()
When trying to get m->md.pv_memattr, make sure that m != NULL,
in particular that vector_page is set to be NULL.
Do not set PGA_REFERENCED flag in pmap_enter_pv().
On ARM any new page reference will result in either entering the new
mapping by calling pmap_enter, etc. or fixing-up the existing mapping in
pmap_fault_fixup().
Therefore we set PGA_REFERENCED flag in the earlier mentioned cases and
setting it later in pmap_enter_pv() is just waste of cycles.
Delete unused pm_pdir pointer from the pmap structure.
Rearrange brackets in the fault cause detection in trap.c
Place the brackets correctly in order to see course of the conditions
instantaneously.
Unify naming in pmap-v6.c and improve style
Use naming common for whole pmap and compatible with other pmaps,
improve style where possible:
pm -> pmap
pg -> m
opg -> om
*pt -> *ptep
*pte -> *ptep
*pde -> *pdep
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250928 |
23-May-2013 |
gber |
Switch to AP[2:1] access permissions model. Store "referenced"
bit in PTE.
Enable Access Flag in CPU control. With AF enabled each valid mapping
needs to have referenced bit in PTE set in order to be able to cache
it in the TLB.
AP[0] bit is to be used as reference flag.
All access permissions are encoded by AP[2:1] wherein AP[1] is in fact
"user enable" and AP[2](APX) is "write disable".
All mappings are always set to be valid. Reference emulation is performed
by setting/clearing reference flag in PTE.
md.pvh_attrs are no longer necessary however pv_flags are still being used
for now.
Marking vm_page as "dirty" or "referenced" is being performed on:
- page or flag fault servicing in pmap_fault_fixup(), basing on the fault
type
- vm_fault servicing in pmap_enter() according to the desired protections
and faulty access type
Redundant page marking has been removed as on ARM we know exactly when the
particular page is referenced or is going to be written.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250884 |
21-May-2013 |
attilio |
o Relax locking assertions for vm_page_find_least()
o Relax locking assertions for pmap_enter_object() and add them also
to architectures that currently don't have any
o Introduce VM_OBJECT_LOCK_DOWNGRADE() which is basically a downgrade
operation on the per-object rwlock
o Use all the mechanisms above to make vm_map_pmap_enter() to work
mostl of the times only with readlocks.
Sponsored by: EMC / Isilon storage division
Reviewed by: alc
|
| 250810 |
19-May-2013 |
andrew |
Add a comment explaining why stack_capture is empty for EABI and clang.
While here add a comment pointing out that, while r11 is not the frame
pointer on EABI as there is no frame pointer, it's value is unused so is
safe.
|
| 250695 |
16-May-2013 |
gber |
Fix L2 cache write-back invalidate for Sheeva core.
Submitted by: Michal Dubiel
Obtained from: Netasq, Semihalf
|
| 250634 |
14-May-2013 |
gber |
Port the new PV entry allocator from amd64/i386/mips to armv6/v7.
PV entries are now roughly half the size.
Instead of using a shared UMA zone for 28 byte pv entries
(two 8-byte tailq nodes, a 4 byte pointer, a 4 byte address and 4 byte
flags), we allocate a page at a time per process.
This provides 252 pv entries per process (actually, per pmap address space)
and eliminates one of the 8-byte tailq entries since we now can track
per-process pv entries implicitly.
The pointer to the pmap can be eliminated by doing address arithmetic to
find the metadata on the page headers to find a single pointer shared by
all 252 entries. There is an 8-int bitmap for the freelist of those 252
entries.
When in serious low memory condition, allocation of another pv_chunk is
possible by freeing some pages in pmap_pv_reclaim().
Added pv_entry/pv_chunk related statistics to pmap.
pv_entry/pv_chunk statistics can be accessed via sysctl vm.pmap.
Ported PTE freelist of KVA allocation and maintenance from i386.
Using an idea from Stephan Uphoff, use the empty pte's that correspond
to the unused kva in the pv memory block to thread a freelist through.
This allows us to free pages that used to be used for pv entry chunks
since we can now track holes in the kva memory block.
As both ARM pmap.c and pmap-v6.c use the same header and pv_entry, pmap and
md_page structures are different, it was needed to separate code designed
for ARMv6/7 from the one for other ARMs.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: alc
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250531 |
11-May-2013 |
kientzle |
Don't use the old stack-walking code with
EABI ARM kernels or clang-compiled ARM kernels.
This fixes a crash seen in clang-compiled ARM
kernels that include WITNESS.
This code could be easily modified to walk the stack
for current clang-generated code (including EABI)
but Andrew Turner has raised concerns that the
stack frame currently emitted by clang isn't actually
required by EABI so such a change might cause problems
down the road.
In case anyone wants to experiment, the change
to support current clang-compiled kernels
involves simply setting FR_RFP=0 and FR_SCP=1.
|
| 250299 |
06-May-2013 |
gber |
Fix page reference emulation on ARMv6 and v7
Submitted by: Zbigniew Bodek
Obtained from: Semihalf
|
| 250297 |
06-May-2013 |
gber |
Fix L2 PTE access permissions management.
Keep following access permissions:
APX AP Kernel User
1 01 R N
1 10 R R
0 01 R/W N
0 11 R/W R/W
Avoid using reserved in ARMv6 APX|AP settings:
- In case of unprivileged (user) access without permission to write,
the access permission bits were being set to reserved for ARMv6
(but valid for ARMv7) value of APX|AP = 111.
Fix-up faulting userland accesses properly:
- Wrong condition statement in pmap_fault_fixup() caused that
any genuine, unprivileged access was being fixed-up instead of
just skip doing anything and return. Staring from now we ensure
proper reaction for illicit user accesses.
L2_S_PROT_R and L2_S_PROT_U names might be misleading as they do not
reflect real permission levels. It will be clarified in following
patches (switch to AP[2:1] permissions model).
Obtained from: Semihalf
|
| 250296 |
06-May-2013 |
gber |
Correct comment about initial VA=>PA mapping
|
| 250294 |
06-May-2013 |
gber |
Avoid calling pcpu_init() simultaneously.
pcpu_init() updates queue, so cannot be called by multiple cores
at the same time
Obtained from: Semihalf
|
| 250293 |
06-May-2013 |
gber |
Properly initialize Armada XP MP subsystem.
- correct setting of Auxiliary Control Register for MP mode
- correct setting of Auxiliarty Debug registers
- cleanup management of memory contains bootup code
- early initialization of Coherency Fabric (MP and not-MP mode)
- enable Snoop Filtering
Obtained from: Semihalf
|
| 250255 |
04-May-2013 |
kientzle |
Make a debugging printf a little more useful.
|
| 250254 |
04-May-2013 |
ian |
Fix comment block formatting.
|
| 250253 |
04-May-2013 |
ian |
Insert STOP_UNWINDING directives in the _start (kernel entry point) and
fork_trampoline (thread entry point) assembler routines, because it's
not possible to unwind beyond those points.
Also insert STOP_UNWINDING in the exception_exit routine, to prevent an
unwind-loop at that point. This is just a stopgap until we get around
to instrumenting all assembler functions with proper unwind metadata.
|
| 250252 |
04-May-2013 |
ian |
EABI unwinder enhancements... When it's time to stop unwinding, don't
exit the loop until after printing info about the current frame. Also,
if executing the unwind function for a frame doesn't change the values of
any registers, log that and exit the loop rather than looping endlessly.
|
| 249999 |
27-Apr-2013 |
wkoszek |
Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.
Submitted by: Thomas Skibo <ThomasSkibo (at) sbcglobal.net>
Tested by: wkoszek (ZedBoard)
Reviewed by: wkoszek, freebsd-arm@ (no objections raised)
|
| 249762 |
22-Apr-2013 |
dmarion |
Initialize GIC_PMRR register on ARM GIC.
Provided by: Thomas Skibo
|
| 249176 |
05-Apr-2013 |
andrew |
Add the hw.floatingpoint sysctl to ARM to tell us if we have vfp support
in the kernel and the hardware includes a vfp unit.
|
| 248961 |
31-Mar-2013 |
ian |
When running on armv6, set alignment checking to modulo-4 mode rather
than modulo-8, because clang emits ldrd and strd instructions for
addresses that are only 4-byte aligned.
|
| 248655 |
23-Mar-2013 |
ian |
Don't check and warn about pmap mismatch on every call to busdma sync.
With some recent busdma refactoring, sometimes it happens that a sync
op gets called when bus_dmamap_load() never got called, which results
in a spurious warning about a map mismatch when no sync operations will
actually happen anyway. Now the check is done only if a sync operation
is actually performed, and the result of the check is a panic, not just
a printf.
Reviewed by: cognet (who prevented me from donning a point hat)
|
| 248508 |
19-Mar-2013 |
kib |
Implement the concept of the unmapped VMIO buffers, i.e. buffers which
do not map the b_pages pages into buffer_map KVA. The use of the
unmapped buffers eliminate the need to perform TLB shootdown for
mapping on the buffer creation and reuse, greatly reducing the amount
of IPIs for shootdown on big-SMP machines and eliminating up to 25-30%
of the system time on i/o intensive workloads.
The unmapped buffer should be explicitely requested by the GB_UNMAPPED
flag by the consumer. For unmapped buffer, no KVA reservation is
performed at all. The consumer might request unmapped buffer which
does have a KVA reserve, to manually map it without recursing into
buffer cache and blocking, with the GB_KVAALLOC flag.
When the mapped buffer is requested and unmapped buffer already
exists, the cache performs an upgrade, possibly reusing the KVA
reservation.
Unmapped buffer is translated into unmapped bio in g_vfs_strategy().
Unmapped bio carry a pointer to the vm_page_t array, offset and length
instead of the data pointer. The provider which processes the bio
should explicitely specify a readiness to accept unmapped bio,
otherwise g_down geom thread performs the transient upgrade of the bio
request by mapping the pages into the new bio_transient_map KVA
submap.
The bio_transient_map submap claims up to 10% of the buffer map, and
the total buffer_map + bio_transient_map KVA usage stays the
same. Still, it could be manually tuned by kern.bio_transient_maxcnt
tunable, in the units of the transient mappings. Eventually, the
bio_transient_map could be removed after all geom classes and drivers
can accept unmapped i/o requests.
Unmapped support can be turned off by the vfs.unmapped_buf_allowed
tunable, disabling which makes the buffer (or cluster) creation
requests to ignore GB_UNMAPPED and GB_KVAALLOC flags. Unmapped
buffers are only enabled by default on the architectures where
pmap_copy_page() was implemented and tested.
In the rework, filesystem metadata is not the subject to maxbufspace
limit anymore. Since the metadata buffers are always mapped, the
buffers still have to fit into the buffer map, which provides a
reasonable (but practically unreachable) upper bound on it. The
non-metadata buffer allocations, both mapped and unmapped, is
accounted against maxbufspace, as before. Effectively, this means that
the maxbufspace is forced on mapped and unmapped buffers separately.
The pre-patch bufspace limiting code did not worked, because
buffer_map fragmentation does not allow the limit to be reached.
By Jeff Roberson request, the getnewbuf() function was split into
smaller single-purpose functions.
Sponsored by: The FreeBSD Foundation
Discussed with: jeff (previous version)
Tested by: pho, scottl (previous version), jhb, bf
MFC after: 2 weeks
|
| 248366 |
16-Mar-2013 |
andrew |
Move the __aeabi_unwind_cpp_pr{0,1,2} functions to libkern so they can be
referenced in a non-debug kernel.
|
| 248364 |
16-Mar-2013 |
andrew |
Implement the required but unused __aeabi_unwind_cpp_* functions in the
trampoline kernel.
|
| 248361 |
16-Mar-2013 |
andrew |
Add an END macro to ARM. This is mostly used to tell gas where the bounds
of the functions are when creating the EABI unwind tables.
|
| 248280 |
14-Mar-2013 |
kib |
Add pmap function pmap_copy_pages(), which copies the content of the
pages around, taking array of vm_page_t both for source and
destination. Starting offsets and total transfer size are specified.
The function implements optimal algorithm for copying using the
platform-specific optimizations. For instance, on the architectures
were the direct map is available, no transient mappings are created,
for i386 the per-cpu ephemeral page frame is used. The code was
typically borrowed from the pmap_copy_page() for the same
architecture.
Only i386/amd64, powerpc aim and arm/arm-v6 implementations were
tested at the time of commit. High-level code, not committed yet to
the tree, ensures that the use of the function is only allowed after
explicit enablement.
For sparc64, the existing code has known issues and a stab is added
instead, to allow the kernel linking.
Sponsored by: The FreeBSD Foundation
Tested by: pho (i386, amd64), scottl (amd64), ian (arm and arm-v6)
MFC after: 2 weeks
|
| 248125 |
10-Mar-2013 |
andrew |
Fix a typo where db_printf was spelt printf.
|
| 248124 |
10-Mar-2013 |
andrew |
Update how we read the stack pointer to work on both GCC and clang.
|
| 248123 |
10-Mar-2013 |
andrew |
Tell the unwinder we can't unwind swi_entry. This fixes an infinite loop
when the kernel attempts to unwind through this function.
The .fnstart and .fnend in this function should be moved to macros but we
are currently missing an END macro on ARM.
|
| 248119 |
10-Mar-2013 |
andrew |
__FreeBSD_ARCH_armv6__ is undefined on clang. We can use __ARM_ARCH in
it's place. This makes 'uname -p' correctly output 'armv6' on a kernel
built with clang.
|
| 248084 |
09-Mar-2013 |
attilio |
Switch the vm_object mutex to be a rwlock. This will enable in the
future further optimizations where the vm_object lock will be held
in read mode most of the time the page cache resident pool of pages
are accessed for reading purposes.
The change is mostly mechanical but few notes are reported:
* The KPI changes as follow:
- VM_OBJECT_LOCK() -> VM_OBJECT_WLOCK()
- VM_OBJECT_TRYLOCK() -> VM_OBJECT_TRYWLOCK()
- VM_OBJECT_UNLOCK() -> VM_OBJECT_WUNLOCK()
- VM_OBJECT_LOCK_ASSERT(MA_OWNED) -> VM_OBJECT_ASSERT_WLOCKED()
(in order to avoid visibility of implementation details)
- The read-mode operations are added:
VM_OBJECT_RLOCK(), VM_OBJECT_TRYRLOCK(), VM_OBJECT_RUNLOCK(),
VM_OBJECT_ASSERT_RLOCKED(), VM_OBJECT_ASSERT_LOCKED()
* The vm/vm_pager.h namespace pollution avoidance (forcing requiring
sys/mutex.h in consumers directly to cater its inlining functions
using VM_OBJECT_LOCK()) imposes that all the vm/vm_pager.h
consumers now must include also sys/rwlock.h.
* zfs requires a quite convoluted fix to include FreeBSD rwlocks into
the compat layer because the name clash between FreeBSD and solaris
versions must be avoided.
At this purpose zfs redefines the vm_object locking functions
directly, isolating the FreeBSD components in specific compat stubs.
The KPI results heavilly broken by this commit. Thirdy part ports must
be updated accordingly (I can think off-hand of VirtualBox, for example).
Sponsored by: EMC / Isilon storage division
Reviewed by: jeff
Reviewed by: pjd (ZFS specific review)
Discussed with: alc
Tested by: pho
|
| 248028 |
08-Mar-2013 |
kientzle |
This file is specific to arm11x6 processors, so tell the
assembler it's okay to use arm11x6 instructions.
|
| 247864 |
06-Mar-2013 |
andrew |
Fix stack alignment in the kernel to be on an 8 byte boundary as required
by AAPCS.
|
| 247776 |
04-Mar-2013 |
cognet |
If we're using a PIPT L2 cache, only merge 2 segments if both the virtual
and the physical addreses are contiguous.
Submitted by: Thomas Skibo <ThomasSkibo@sbcglobal.net>
|
| 247608 |
02-Mar-2013 |
andrew |
Ensure the stack is correctly aligned before calling the first C function.
|
| 247463 |
28-Feb-2013 |
mav |
MFcalloutng:
Switch eventtimers(9) from using struct bintime to sbintime_t.
Even before this not a single driver really supported full dynamic range of
struct bintime even in theory, not speaking about practical inexpediency.
This change legitimates the status quo and cleans up the code.
|
| 247360 |
26-Feb-2013 |
attilio |
Merge from vmc-playground branch:
Replace the sub-optimal uma_zone_set_obj() primitive with more modern
uma_zone_reserve_kva(). The new primitive reserves before hand
the necessary KVA space to cater the zone allocations and allocates pages
with ALLOC_NOOBJ. More specifically:
- uma_zone_reserve_kva() does not need an object to cater the backend
allocator.
- uma_zone_reserve_kva() can cater M_WAITOK requests, in order to
serve zones which need to do uma_prealloc() too.
- When possible, uma_zone_reserve_kva() uses directly the direct-mapping
by uma_small_alloc() rather than relying on the KVA / offset
combination.
The removal of the object attribute allows 2 further changes:
1) _vm_object_allocate() becomes static within vm_object.c
2) VM_OBJECT_LOCK_INIT() is removed. This function is replaced by
direct calls to mtx_init() as there is no need to export it anymore
and the calls aren't either homogeneous anymore: there are now small
differences between arguments passed to mtx_init().
Sponsored by: EMC / Isilon storage division
Reviewed by: alc (which also offered almost all the comments)
Tested by: pho, jhb, davide
|
| 247340 |
26-Feb-2013 |
cognet |
Fix SMP build.
|
| 247339 |
26-Feb-2013 |
cognet |
Don't forget to init the VFP stuff for all cores.
|
| 247195 |
23-Feb-2013 |
mav |
Add basic and not very reliable protection against going to sleep with
thread scheduled by interrupt fired after we entered critical section.
None of cpu_sleep() implementations on ARM check sched_runnable() now, so
put the first line of defence here. This mostly fixes unexpectedly long
sleeps in synthetic tests of calloutng code and probably other situations.
|
| 247046 |
20-Feb-2013 |
alc |
Initialize vm_max_kernel_address on non-FDT platforms. (This should have
been included in r246926.)
The second parameter to pmap_bootstrap() is redundant. Eliminate it.
Reviewed by: andrew
|
| 246926 |
18-Feb-2013 |
alc |
On arm, like sparc64, the end of the kernel map varies from one type of
machine to another. Therefore, VM_MAX_KERNEL_ADDRESS can't be a constant.
Instead, #define it to be a variable, vm_max_kernel_address, just like we
do on sparc64.
Reviewed by: kib
Tested by: ian
|
| 246881 |
16-Feb-2013 |
ian |
In _bus_dmamap_addseg(), the return value must be zero for error, or the size
actually added to the segment (possibly smaller than the requested size if
boundary crossings had to be avoided).
|
| 246859 |
15-Feb-2013 |
ian |
Set map->pmap before _bus_dmamap_count_pages() tries to use it.
Obtained from: Thomas Skibo <ThomasSkibo@sbcglobal.net>
|
| 246713 |
12-Feb-2013 |
kib |
Reform the busdma API so that new types may be added without modifying
every architecture's busdma_machdep.c. It is done by unifying the
bus_dmamap_load_buffer() routines so that they may be called from MI
code. The MD busdma is then given a chance to do any final processing
in the complete() callback.
The cam changes unify the bus_dmamap_load* handling in cam drivers.
The arm and mips implementations are updated to track virtual
addresses for sync(). Previously this was done in a type specific
way. Now it is done in a generic way by recording the list of
virtuals in the map.
Submitted by: jeff (sponsored by EMC/Isilon)
Reviewed by: kan (previous version), scottl,
mjacob (isp(4), no objections for target mode changes)
Discussed with: ian (arm changes)
Tested by: marius (sparc64), mips (jmallet), isci(4) on x86 (jharris),
amd64 (Fabian Keil <freebsd-listen@fabiankeil.de>)
|
| 246601 |
09-Feb-2013 |
kientzle |
Fix breakage introduced in r246318.
|
| 246318 |
04-Feb-2013 |
andrew |
Use the STACKALIGN macro to alight the stack rather than with a magic mask.
Submitted by: Christoph Mallon <christoph.mallon gmx.de>
|
| 246158 |
31-Jan-2013 |
kib |
Use pmap_kextract() instead of inlining the page table walk.
Remove the comment referencing non-existing code.
Reviewed by: cognet, ian (previous version)
Tested by: ian
|
| 246001 |
27-Jan-2013 |
ian |
Fix off-by-one errors in low-level arm9 and arm10 cache maintenance routines.
In all the routines that loop through a range of virtual addresses, the loop
is controlled by subtracting the cache line size from the total length of the
request. After the subtract, a 'bpl' instruction was used, which branches if
the result of the subtraction is zero or greater, but we need to exit the
loop when the count hits zero. Thus, all the bpl instructions in those loops
have been changed to 'bhi' (branch if greater than zero).
In addition, the two routines that walk through the cache using set-and-index
were correct, but confusing. The loop control for those has been simplified,
just so that it's easier to see by examination that the code is correct.
Routines for other arm architectures and generations still have the bpl
instruction, but compensate for the off-by-one situation by decrementing
the count register by one before entering the loop.
PR: arm/174461
Approved by: cognet (mentor)
|
| 246000 |
27-Jan-2013 |
ian |
Restore the irq number to the display string; I fumbled this in the previous
commit while trying to make the code internally self-consistant.
Approved by: cognet (mentor)
Obtained from: Christoph Mallon
|
| 245948 |
26-Jan-2013 |
ian |
Fix a buffer overrun while pre-formatting the names array, perpetrated in
the prior commit. Use essentially the same sprintf() statement for both
formatting and pre-formatting, and use a format string which eliminates the
need for an extra temporary buffer when formatting the name.
Noted by: Christoph Mallon
Pointy hat to: ian
Approved by: cognet (mentor)
|
| 245942 |
26-Jan-2013 |
andrew |
Align td_frame as it will be placed into the sp register which must be
8 byte aligned on ARM EABI.
|
| 245637 |
19-Jan-2013 |
ian |
Eliminate the need for an intermediate array of indices into the arrays of
interrupt counts and names, by making the names into an array of fixed-length
strings that can be directly indexed. This eliminates extra memory accesses
on every interrupt to increment the counts.
As a side effect, it also fixes a bug that would corrupt the names data
if a name was longer than MAXCOMLEN, which led to incorrect vmstat -i output.
Approved by: cognet (mentor)
|
| 245551 |
17-Jan-2013 |
andrew |
* Correct KINFO_PROC_SIZE for ARM EABI.
* Update the syscall interface to pass in the syscall value in register r7.
|
| 245549 |
17-Jan-2013 |
andrew |
Implement stack unwinding based on section 9 of the "Exception handling ABI
for the ARM architecture" documentation. The unwind tables are currently
not stored in the kernel but will be added later.
|
| 245478 |
15-Jan-2013 |
cognet |
Use armv7_drain_writebuf() and armv7_context_switch, instead of the arm11
variants.
|
| 245477 |
15-Jan-2013 |
cognet |
Only spin on the blocked_lock for SCHED_ULE+SMP, as it's done on the other
arches.
|
| 245414 |
14-Jan-2013 |
andrew |
Update sigcode to use both the current ABI and FreeBSD's version of the
ARM EABI syscall calling convention.
The current ABI encodes the syscall number in the instruction. This causes
issues with the thumb mode as it only has 8 bits to encode this value and
we have too many system calls and by using a register will simplify the
code to get the syscall number in the kernel.
With the ARM EABI we reuse the Linux calling convention by storing the
value in r7. Because of this we use both methods to encode the syscall
number in this function.
|
| 245192 |
08-Jan-2013 |
cognet |
Remove old declarations.
|
| 245146 |
08-Jan-2013 |
gonzo |
Fix cache-related issue with pmap for ARMv6/ARMv7:
- Missing PTE_SYNC in pmap_kremove caused memory corruption
in userland applications
- Fix lack of cache flushes when using special PTEs for zeroing or
copying pages. If there are dirty lines for destination memory
and page later remapped as a non-cached region actual content
might be overwritten by these dirty lines when cache eviction
happens as a result of applying cache eviction policy or because
of wbinv_all call.
- icache sync for new mapping for userland applications.
Tested by: gber
|
| 245120 |
07-Jan-2013 |
gonzo |
Release version check for erratum 727915 workaround in
l2_wbinv_range function implementation causes function
fail to flush caches for chip with RTL number 0x7. I failed
to find official PL310 revision with this RTL number
so further research on this matter required.
|
| 245087 |
06-Jan-2013 |
andrew |
Fix the build:
* Use pl310_softc when the softc is otherwise unavailable.
* Use the correct spelling of sc_rtl_revision.
|
| 245083 |
06-Jan-2013 |
andrew |
Only work around errata when we are on a part where the erratum applies.
Reviewed by: gonzo
|
| 245079 |
05-Jan-2013 |
gonzo |
Add hw.board.serial and hw.board.revision for exporting board-specific info
|
| 244914 |
31-Dec-2012 |
gonzo |
PL310 driver update:
- Add pl310.disable tunable to disable L2 cache altogether. In
order to make sure that it's 100% disabled we use cache event
counters for cache line eviction and read allocate events
and panic if any of these counters increased. This is purely
for debugging purpose
- Direct access DEBUG_CTRL and CTRL might be unavailable in
unsecure mode, so use platform-specific functions for
these registers
- Replace #if 1 with proper erratum numbers
- Add erratum 753970 workaround
- Remove wait function for atomic operations
- Protect cache operations with spin mutex in order to prevent race condition
- Disable instruction cache prefetch and make sure data cache
prefetch is enabled in OMAP4-specific intialization
|
| 244912 |
31-Dec-2012 |
gonzo |
Merge r234561 from busdma_machdep.c to ARMv6 version of busdma:
Interrupts must be disabled while handling a partial cache line flush,
as otherwise the interrupt handling code may modify data in the non-DMA
part of the cache line while we have it stashed away in the temporary
stack buffer, then we end up restoring a stale value.
PR: 160431
Submitted by: Ian Lepore
|
| 244575 |
22-Dec-2012 |
cognet |
The manpage states that bus_dmamap_create(9) returns ENOMEM if it can't
allocate a map or mapping resources. That seems to imply that any memory
allocations it does must use M_NOWAIT and check for NULL.
Submitted by: Ian Lepore <freebsd@damnhippie.dyndns.org>
|
| 244574 |
22-Dec-2012 |
cognet |
The VM_MEMATTR_ constants are enumerated, not a bitset. Compare accordingly.
Submitted by: Ian Lepore <freebsd@damnhippie.dyndns.org>
|
| 244480 |
20-Dec-2012 |
gonzo |
Replace generic ARM11 option with more specific
support for ARM1136 and ARM1176
Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Obtained from: NetBSD
|
| 244473 |
20-Dec-2012 |
cognet |
Use C comments instead of C++ comments.
Spotted out by: gonzo (thanks, man)
|
| 244471 |
20-Dec-2012 |
cognet |
Busdma enhancements, especially for managing small uncacheable buffers.
- Use the new architecture-agnostic buffer pool manager that uses uma(9)
to manage a set of power-of-2 sized buffers for bus_dmamem_alloc().
- Create pools of buffers backed by both regular and uncacheable memory,
and use them to handle regular versus BUS_DMA_COHERENT allocations.
- Use uma(9) to manage a pool of bus_dmamap structs instead of local code
to manage a static list of 500 items (it took 3300 maps to get to
multi-user mode, so the static pool wasn't much of an optimization).
- Small BUS_DMA_COHERENT allocations no longer waste an entire page per
allocation, or set pages to uncached when they contain data other than
DMA buffers. There's no longer a need for drivers to work around the
inefficiency by allocing large buffers then sub-dividing them.
- Because we know the alignment and padding of buffers allocated by
bus_dmamem_alloc() (whether coherent or regular memory, and whether
obtained from the pool allocator or directly from the kernel) we
can avoid doing partial cacheline flushes on them.
- Add a fast-out to _bus_dma_could_bounce() (and some comments about
what the routine really does because the old misplaced comment was wrong).
- Everywhere the dma tag alignment is used, the interpretation is that
an alignment of 1 means no special alignment. If the tag is created
with an alignment argument of zero, store it in the tag as one, and
remove all the code scattered around that changed 0->1 at point of use.
- Remove stack-allocated arrays of segments, use a local array of two
segments within the tag struct, or dynamically allocate an array at first
use if nsegments > 2. On an arm system I tested, only 5 of 97 tags used
more than two segments. On my x86 desktop it was only 7 of 111 tags.
Submitted by: Ian Lepore <freebsd@damnhippie.dyndns.org>
|
| 244469 |
20-Dec-2012 |
cognet |
Use the new allocator in bus_dmamem_alloc().
|
| 244414 |
19-Dec-2012 |
cognet |
Properly implement pmap_[get|set]_memattr
Submitted by: Ian Lepore <freebsd@damnhippie.dyndns.org>
|
| 244195 |
13-Dec-2012 |
gonzo |
Add driver for PrimeCell Vectored Interrupt Controller (PL190)
|
| 243909 |
05-Dec-2012 |
cognet |
Don't write-back the cachelines if we really just want to invalidate them.
Spotted out by: Ian Lepore <freebsd at damnhippie DOT dyndns dot org>
|
| 243691 |
30-Nov-2012 |
gonzo |
Get reserved memory regions and exclude them from available memory map
|
| 243602 |
27-Nov-2012 |
gonzo |
Do not enable data cache until later in kernel init. Stale bits in
cache might cause erroneus behavior on early stage.
Submitted by: Ian Lepore
Tested on: Atmel, Marvell, and Eyxnos
|
| 243579 |
27-Nov-2012 |
marcel |
Don't include arm/xscale/i8134x/i81342reg.h when we're compiling LINT.
The definitions in i81342reg.h clash with those in i80321reg.h.
|
| 243578 |
27-Nov-2012 |
marcel |
Remove print_kernel_section_addr(). All statements in that function
expand to uncompilable code when the kernel configuration contains
"options DEBUG", such as it is for LINT. The toolchain is often a
better approach to figure this out, as it doesn't require one to
boot the kernel.
|
| 243523 |
25-Nov-2012 |
kientzle |
Fix spelling.
|
| 243359 |
21-Nov-2012 |
cognet |
Make sure the address starts on a cache line boundary.
|
| 243132 |
16-Nov-2012 |
kib |
Move the declaration of vm_phys_paddr_to_vm_page() from vm/vm_page.h
to vm/vm_phys.h, where it belongs.
Requested and reviewed by: alc
MFC after: 2 weeks
|
| 243109 |
16-Nov-2012 |
cognet |
Don't forget to unlock the pmap lock on failure.
|
| 243108 |
15-Nov-2012 |
cognet |
Remove a useless printf
|
| 243107 |
15-Nov-2012 |
cognet |
Use the "inner shareable" variations of flush/invalidate functions for SMP.
Submitted by: Giovanni Trematerra <gianni at freebsd DOT org>
|
| 243040 |
14-Nov-2012 |
kib |
Flip the semantic of M_NOWAIT to only require the allocation to not
sleep, and perform the page allocations with VM_ALLOC_SYSTEM
class. Previously, the allocation was also allowed to completely drain
the reserve of the free pages, being translated to VM_ALLOC_INTERRUPT
request class for vm_page_alloc() and similar functions.
Allow the caller of malloc* to request the 'deep drain' semantic by
providing M_USE_RESERVE flag, now translated to VM_ALLOC_INTERRUPT
class. Previously, it resulted in less aggressive VM_ALLOC_SYSTEM
allocation class.
Centralize the translation of the M_* malloc(9) flags in the single
inline function malloc2vm_flags().
Discussion started by: "Sears, Steven" <Steven.Sears@netapp.com>
Reviewed by: alc, mdf (previous version)
Tested by: pho (previous version)
MFC after: 2 weeks
|
| 243026 |
14-Nov-2012 |
cognet |
Make it clear the L2 ops are filled for any cpu using a PL310 cache, not just
the omap4.
Spotted out by: Giovanni Trematerra <gianni at freebsd DOT org>
|
| 243024 |
14-Nov-2012 |
cognet |
Use the arrmv7 version for flushID too, as it does something different for SMP.
Submitted by: Giovanni Trematerra <gianni at freebsd DOT org>
|
| 242746 |
08-Nov-2012 |
imp |
Reduce differences between these two initarms a bit more.
|
| 242700 |
07-Nov-2012 |
imp |
Minor cosmetic changes to bring atmel's initarm and the default
initarm for FDT closer together. More to follow.
|
| 242531 |
03-Nov-2012 |
andrew |
Merge the FDT versions of initarm.
The copies of initarm used on platforms with FDT support were almost
identical. The differences were pulled out into separate functions that
were called by initarm.
This change merges the, now identical, copies of initarm and a few of it's
support functions. This is a step towards a common kernel on ARMv6.
|
| 241063 |
30-Sep-2012 |
alc |
Stop calling pmap_remove_write() from pmap_remove_all(). Doing so is not
only inefficient but also leads to recursive lock acquisition.
Tested by: ray
|
| 241055 |
29-Sep-2012 |
alc |
Eliminate unused variables.
|
| 241054 |
29-Sep-2012 |
alc |
Add support for mincore(). Specifically, this is an adaptation of the
pmap_mincore() implementation that was added to the original arm pmap
in r235717.
|
| 241044 |
29-Sep-2012 |
alc |
Update a comment to reflect recent locking changes.
|
| 240983 |
27-Sep-2012 |
alc |
Implementing pmap_kextract(va) as pmap_extract(kernel_pmap, va) is
problematic because some callers to pmap_kextract() expect its
implementation to be lock-less. In particular, uma_dbg_alloc() implicitly
requires this. Otherwise, lock-order reversals occur between pmap locks and
UMA zone locks. So, this change introduces a lock-less implementation of
pmap_kextract().
Disable recursion on the pvh global lock in the new armv6 pmap. While
recursion on this locks occurs in the old arm pmap, it thankfully doesn't
occur in the armv6 pmap.
Tested by: jmg
|
| 240913 |
25-Sep-2012 |
alc |
Eliminate an unused declaration.
|
| 240803 |
22-Sep-2012 |
alc |
Since UMA_ZONE_NOFREE is specified when l2zone and l2table_zone are created,
there is no need to release and reacquire the pmap and pvh global locks
around calls to uma_zfree(). Recursion into the pmap simply won't occur.
Eliminate the use of M_USE_RESERVE. It is deprecated and, in fact, counter-
productive, meaning that it actually makes the memory allocation request
more likely to fail.
Eliminate the macros pmap_{alloc,free}_l2_dtable(). They are of limited
utility, and pmap_free_l2_dtable() was inconsistently used.
Tidy up pmap_init(). In particular, change the initialization of the PV
zone so that it doesn't span the initialization of the l2 and l2table zones.
Tested by: jmg
|
| 240802 |
22-Sep-2012 |
andrew |
Create a common set_stackptrs in sys/arm/machdep.c.
On single core devices set_stackptrs is only ever called with cpu = 0 in
initarm and will be identical to the existing function. On SMP this needs
to be implemented for sys/arm/mp_machdep.c, but the implementations are
identical for each SoC.
|
| 240532 |
15-Sep-2012 |
alc |
Eliminate an unused malloc type.
|
| 240486 |
14-Sep-2012 |
gber |
Support identification of new PJ4B cores.
Obtained from: Semihalf
|
| 240442 |
13-Sep-2012 |
alc |
Simplify the kernel pmap locking in pmap_enter_pv(). While I'm here, tidy
up the comments and whitespace.
Tested by: cognet
|
| 240321 |
10-Sep-2012 |
alc |
Replace all uses of the vm page queues lock by a r/w lock that is private
to this pmap.
Revise some comments.
The file vm/vm_param.h includes the file machine/vmparam.h, so there is no
need to directly include it.
Tested by: andrew
|
| 240177 |
06-Sep-2012 |
jhb |
Dynamically allocate the S/G lists passed to callback routines rather than
allocating them on the stack of various bus_dmamap_load*() functions. The
S/G lists are stored in the DMA tags. This matches the implementation on
all other platforms.
Discussed with: scottl, gibbs
Tested by: stas (arm@)
|
| 240166 |
06-Sep-2012 |
alc |
There is no need to release the pvh global lock around calls to
pmap_get_pv_entry(). In fact, some callers already held it around calls.
(In earlier versions, the same statements would apply to the page queues
lock.)
While I'm here tidy up the style of a few nearby statements and revise
some comments.
Tested by: Ian Lepore
|
| 239934 |
31-Aug-2012 |
alc |
Replace all uses of the vm page queues lock by a r/w lock that is private
to this pmap.
Tested by: Ian Lepore
|
| 239702 |
26-Aug-2012 |
gonzo |
Add ARM11 support for elf trampoline
|
| 239701 |
26-Aug-2012 |
gonzo |
Add support for ARM11 cpufunc
Obtained from: NetBSD (partially)
|
| 239698 |
26-Aug-2012 |
gonzo |
Call set_pcpu for ARMv6 architecture too
|
| 239697 |
26-Aug-2012 |
gonzo |
Merge fix for hang on ARM11 from NetBSD
|
| 239696 |
26-Aug-2012 |
gonzo |
Piggyback MIPS changes and add ARM syscons support for devices with
framebuffer
While here - sort #if defined() order alphabetically
|
| 239687 |
25-Aug-2012 |
gonzo |
Add clrex, strex , ldrex, strex and variants
Submitted by: Alexander Rybalko
|
| 239597 |
22-Aug-2012 |
gonzo |
Do not change "cachable" attribute for DMA memory allocated with
BUS_DMA_COHERENT attribute
The minimum unit for changing "cachable" attribute is page, so call
to pmap_change_attr effectively disable cache for all pages that newly
allocated DMA memory region spans on. The problem is that general-purpose
memory could reside on these pages too and disabling cache might affect
performance. Moreover ldrex/strex operators raise Data Abort exception
when accessing memory on page with "cachable" attribute off.
BUS_DMA_COHERENT does nto require memory to be coherent. It just suggests
to do best effort for reducing synchronization overhead.
|
| 239369 |
18-Aug-2012 |
hrs |
Fix build when DEBUG is defined.
|
| 239268 |
15-Aug-2012 |
gonzo |
Merging projects/armv6, part 1
Cummulative patch of changes that are not vendor-specific:
- ARMv6 and ARMv7 architecture support
- ARM SMP support
- VFP/Neon support
- ARM Generic Interrupt Controller driver
- Simplification of startup code for all platforms
|
| 239191 |
11-Aug-2012 |
andrew |
Move the decoding of the swi instruction to the syscall function. With the
ARM EABI the syscall value will be moved to a register to ease adding thumb
support. When this happens decoding of the instruction will no longer be
required.
|
| 239065 |
05-Aug-2012 |
kib |
After the PHYS_TO_VM_PAGE() function was de-inlined, the main reason
to pull vm_param.h was removed. Other big dependency of vm_page.h on
vm_param.h are PA_LOCK* definitions, which are only needed for
in-kernel code, because modules use KBI-safe functions to lock the
pages.
Stop including vm_param.h into vm_page.h. Include vm_param.h
explicitely for the kernel code which needs it.
Suggested and reviewed by: alc
MFC after: 2 weeks
|
| 239033 |
04-Aug-2012 |
andrew |
Correctly return EFAULT in copyin & copyout on a fault. This fixes NFS
when running FreeBSD on QEMU emulating a Gumstix board.
While here remove the use of a magic number in the not-XScale version.
Pointed out by: kib
Reviewed by: stas
|
| 239032 |
04-Aug-2012 |
andrew |
Ensure we align the stack to 8 bytes in system calls.
This is not strictly required with the current ABI but will be when we
switch to the ARM EABI. The aapcs requires the stack to be 4 byte aligned
at all times and 8 byte aligned when calling a public subroutine where the
current ABI only requires sp to be a multiple of 4.
|
| 238545 |
17-Jul-2012 |
gonzo |
Move unmask IRQ function call up to nexus device level.
FDT-enabled targets were broken after r238043 that relies
on device up the hierarchy to properly setup interrupt.
nexus device for ARM platforms did job only partially:
setting handler but not unmasking interrupt. Unmasking
was performed by platform code.
Reviewed by: andrew@
|
| 237118 |
15-Jun-2012 |
imp |
Fix a global shadowing problem when LINUX_BOOT_ABI was defined.
|
| 237045 |
14-Jun-2012 |
imp |
More Linux boot support. Create arm_dump_avail_init() to initialize
this array either from Linux boot data, when enabled, or in the
typical way that most ports do it. arm_pyhs_avail_init is coming
soon since it must be a separate function.
|
| 237044 |
14-Jun-2012 |
imp |
Add support for parsing Linux ATAGs such as you'd see from uboot or
redboot. Support is very preiminary and likely needs some work. Also,
do some minor code shuffling of the FreeBSD /boot/loader metadata
parsing code. This code is preliminary and should be used with
caution.
|
| 237042 |
14-Jun-2012 |
imp |
Create default_parse_boot_param which, if FreeBSD /boot/loader support
is enabled, sets values based on the metadata passed in. Otherwise
fake_preload_metadata is called. Change the default parse_boot_param
to default_parse_boot_param. Enable this functionality only on the mv
platform, which is where most of the code is from.
Reviewed by: cognet, Ian Lapore
|
| 237040 |
14-Jun-2012 |
imp |
Modify all the arm platform files to call parse_boot_param passing in
the boot parameters from initarm first thing. parse_boot_param parses
the boot arguments and converts them to the /boot/loader metadata the
rest of the kernel uses. parse_boot_param is a weak alias to
fake_preload_metadata, which all the platforms use now, but may become
more extensive in the future.
Since it is a weak symbol, specific boards may define their own
parse_boot_param to interface to custom boot loaders.
Reviewed by: cognet@, Ian Lapore
|
| 236991 |
13-Jun-2012 |
imp |
Final whitespace trim.
|
| 236828 |
10-Jun-2012 |
andrew |
Pull out the common code to initialise proc0 & thread0 from initarm to a
common function.
Reviewed by: imp
|
| 236524 |
03-Jun-2012 |
imp |
Minor rearrangement of the locore <-> initarm interface. Pass in a
structure with the first 4 registers to allow a wider range of boot
loaders to work. Future commits will make use of this to centralize
support for the different loaders.
|
| 236308 |
30-May-2012 |
gber |
Print userspace backtrace for current thread.
Reviewed by: imp
Obtained from: Semihalf
|
| 235908 |
24-May-2012 |
gber |
Return Supervisor SP and LR registers instead of User ones while in KDB thread.
Obtained from: Semihalf
|
| 235907 |
24-May-2012 |
gber |
ARMs don't have motherboards.
Obtained from: Semihalf
|
| 235831 |
23-May-2012 |
fabient |
Soft PMC support for ARM.
Callgraph is not captured, only current location.
Sample system wide profiling: "pmcstat -Sclock.hard -T"
|
| 235717 |
21-May-2012 |
imp |
Implement pmap_mincore for arm. Now programs using it don't cause a
flood of console messages.
Reviewed by: alc@
|
| 235278 |
11-May-2012 |
imp |
Remove unused cruft. We call through memcpy more directly when we
need to move the kernel, so we no longer need this.
|
| 235277 |
11-May-2012 |
imp |
This comment has become unmoored from the code to which it applies.
Move it back.
|
| 235062 |
05-May-2012 |
imp |
I need to change uname -p, not uname -m, so back this out.
Also, fix a couple of style(9) issues while I'm here.
Submitted by: nathanw, bde
|
| 235050 |
05-May-2012 |
imp |
Big endian arm boxes need to have a uname -m of armeb, not arm, so
that the bootstrap from source works correctly.
MFC after: 4 days
|
| 234688 |
25-Apr-2012 |
stas |
- Disable MMU before reconfiguring the pagetables in the trampoline code.
Otherwise we might end up overwriting the PTEs we're currently using
for some reason.
Reviewed by: cognet
|
| 234561 |
22-Apr-2012 |
marius |
Interrupts must be disabled while handling a partial cache line flush,
as otherwise the interrupt handling code may modify data in the non-DMA
part of the cache line while we have it stashed away in the temporary
stack buffer, then we end up restoring a stale value.
PR: 160431
Submitted by: Ian Lepore
MFC after: 1 week
|
| 232356 |
01-Mar-2012 |
jhb |
- Change contigmalloc() to use the vm_paddr_t type instead of an unsigned
long for specifying a boundary constraint.
- Change bus_dma tags to use bus_addr_t instead of bus_size_t for boundary
constraints.
These allow boundary constraints to be fully expressed for cases where
sizeof(bus_addr_t) != sizeof(bus_size_t). Specifically, it allows a
driver to properly specify a 4GB boundary in a PAE kernel.
Note that this cannot be safely MFC'd without a lot of compat shims due
to KBI changes, so I do not intend to merge it.
Reviewed by: scottl
|
| 230455 |
22-Jan-2012 |
pjd |
TDF_* flags should be used with td_flags field and TDP_* flags should be used
with td_pflags field. Correct two places where it was not the case.
Discussed with: kib
MFC after: 1 week
|
| 228530 |
15-Dec-2011 |
raj |
ARM pmap fixes:
- Write Buffers have to be drained after write to Page Table even if caches
are in write-through mode.
- Make sure to sync PTE in pmap_zero_page_generic().
Submitted by: Michal Mazur
Reviewed by: cognet
Obtained from: Semihalf
MFC after: 1 month
|
| 228522 |
15-Dec-2011 |
alc |
Eliminate vestiges of page coloring.
|
| 228504 |
14-Dec-2011 |
raj |
Make *intr{cnt,names} on ARM reside in data section, similar to other arches.
sintrnames and sintrcnt are initialized with non-zero values, which were
discarded by the .bss directive, so consumers like "vmstat -i" were not
getting correct data.
Submitted by: Lukasz Plachno
Obtained from: Semihalf
MFC after: 1 month
|
| 227309 |
07-Nov-2011 |
ed |
Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.
The SYSCTL_NODE macro defines a list that stores all child-elements of
that node. If there's no SYSCTL_DECL macro anywhere else, there's no
reason why it shouldn't be static.
|
| 227293 |
07-Nov-2011 |
ed |
Mark MALLOC_DEFINEs static that have no corresponding MALLOC_DECLAREs.
This means that their use is restricted to a single C file.
|
| 226498 |
18-Oct-2011 |
des |
Trace attempts to call restricted MD syscalls.
|
| 226441 |
16-Oct-2011 |
cognet |
Explicitely set ARM_RAS_START and ARM_RAS_END once the cacheline or the
page has been allocated, or we could end up using random values, and bad things
could happen.
PR: arm/161492
Submitted by: Ian Lepore <freebsd AT damnhippie dot dyndns DOT org>
MFC after: 1 week
|
| 225990 |
04-Oct-2011 |
marcel |
Include opt_* headers first. Otherwise we can end up with redefined
symbols.
|
| 225988 |
04-Oct-2011 |
marcel |
Fix build when DEBUG is defined (e.g. for LINT).
|
| 225973 |
04-Oct-2011 |
kib |
Convert ARM to the syscallenter/syscallret system call sequence handlers.
Tested by: gber
MFC after: 1 month
|
| 225617 |
16-Sep-2011 |
kmacy |
In order to maximize the re-usability of kernel code in user space this
patch modifies makesyscalls.sh to prefix all of the non-compatibility
calls (e.g. not linux_, freebsd32_) with sys_ and updates the kernel
entry points and all places in the code that use them. It also
fixes an additional name space collision between the kernel function
psignal and the libc function of the same name by renaming the kernel
psignal kern_psignal(). By introducing this change now we will ease future
MFCs that change syscalls.
Reviewed by: rwatson
Approved by: re (bz)
|
| 225418 |
06-Sep-2011 |
kib |
Split the vm_page flags PG_WRITEABLE and PG_REFERENCED into atomic
flags field. Updates to the atomic flags are performed using the atomic
ops on the containing word, do not require any vm lock to be held, and
are non-blocking. The vm_page_aflag_set(9) and vm_page_aflag_clear(9)
functions are provided to modify afalgs.
Document the changes to flags field to only require the page lock.
Introduce vm_page_reference(9) function to provide a stable KPI and
KBI for filesystems like tmpfs and zfs which need to mark a page as
referenced.
Reviewed by: alc, attilio
Tested by: marius, flo (sparc64); andreast (powerpc, powerpc64)
Approved by: re (bz)
|
| 224746 |
09-Aug-2011 |
kib |
- Move the PG_UNMANAGED flag from m->flags to m->oflags, renaming the flag
to VPO_UNMANAGED (and also making the flag protected by the vm object
lock, instead of vm page queue lock).
- Mark the fake pages with both PG_FICTITIOUS (as it is now) and
VPO_UNMANAGED. As a consequence, pmap code now can use use just
VPO_UNMANAGED to decide whether the page is unmanaged.
Reviewed by: alc
Tested by: pho (x86, previous version), marius (sparc64),
marcel (arm, ia64, powerpc), ray (mips)
Sponsored by: The FreeBSD Foundation
Approved by: re (bz)
|
| 224612 |
02-Aug-2011 |
attilio |
Fix for arm and mips case the size of storage for sintrcnt/sintrnames.
It seems that "info as" is not much precise on what expect by pseudo-op
.word, by the way.
No MFC is previewed for this patch.
Tested by: andreast, pluknet
Approved by: re (kib)
|
| 224187 |
18-Jul-2011 |
attilio |
- Remove the eintrcnt/eintrnames usage and introduce the concept of
sintrcnt/sintrnames which are symbols containing the size of the 2
tables.
- For amd64/i386 remove the storage of intr* stuff from assembly files.
This area can be widely improved by applying the same to other
architectures and likely finding an unified approach among them and
move the whole code to be MI. More work in this area is expected to
happen fairly soon.
No MFC is previewed for this patch.
Tested by: pluknet
Reviewed by: jhb
Approved by: re (kib)
|
| 224049 |
15-Jul-2011 |
marcel |
In pmap_protect(), don't call vm_page_dirty() if the page is unmanaged.
|
| 223692 |
30-Jun-2011 |
jonathan |
Add some checks to ensure that Capsicum is behaving correctly, and add some
more explicit comments about what's going on and what future maintainers
need to do when e.g. adding a new operation to a sys_machdep.c.
Approved by: mentor(rwatson), re(bz)
|
| 223677 |
29-Jun-2011 |
alc |
Add a new option, OBJPR_NOTMAPPED, to vm_object_page_remove(). Passing this
option to vm_object_page_remove() asserts that the specified range of pages
is not mapped, or more precisely that none of these pages have any managed
mappings. Thus, vm_object_page_remove() need not call pmap_remove_all() on
the pages.
This change not only saves time by eliminating pointless calls to
pmap_remove_all(), but it also eliminates an inconsistency in the use of
pmap_remove_all() versus related functions, like pmap_remove_write(). It
eliminates harmless but pointless calls to pmap_remove_all() that were being
performed on PG_UNMANAGED pages.
Update all of the existing assertions on pmap_remove_all() to reflect this
change.
Reviewed by: kib
|
| 223668 |
29-Jun-2011 |
jonathan |
We may split today's CAPABILITIES into CAPABILITY_MODE (which has
to do with global namespaces) and CAPABILITIES (which has to do with
constraining file descriptors). Just in case, and because it's a better
name anyway, let's move CAPABILITIES out of the way.
Also, change opt_capabilities.h to opt_capsicum.h; for now, this will
only hold CAPABILITY_MODE, but it will probably also hold the new
CAPABILITIES (implying constrained file descriptors) in the future.
Approved by: rwatson
Sponsored by: Google UK Ltd
|
| 222813 |
07-Jun-2011 |
attilio |
etire the cpumask_t type and replace it with cpuset_t usage.
This is intended to fix the bug where cpu mask objects are
capped to 32. MAXCPU, then, can now arbitrarely bumped to whatever
value. Anyway, as long as several structures in the kernel are
statically allocated and sized as MAXCPU, it is suggested to keep it
as low as possible for the time being.
Technical notes on this commit itself:
- More functions to handle with cpuset_t objects are introduced.
The most notable are cpusetobj_ffs() (which calculates a ffs(3)
for a cpuset_t object), cpusetobj_strprint() (which prepares a string
representing a cpuset_t object) and cpusetobj_strscan() (which
creates a valid cpuset_t starting from a string representation).
- pc_cpumask and pc_other_cpus are target to be removed soon.
With the moving from cpumask_t to cpuset_t they are now inefficient
and not really useful. Anyway, for the time being, please note that
access to pcpu datas is protected by sched_pin() in order to avoid
migrating the CPU while reading more than one (possible) word
- Please note that size of cpuset_t objects may differ between kernel
and userland. While this is not directly related to the patch itself,
it is good to understand that concept and possibly use the patch
as a reference on how to deal with cpuset_t objects in userland, when
accessing kernland members.
- KTR_CPUMASK is changed and now is represented through a string, to be
set as the example reported in NOTES.
Please additively note that no MAXCPU is bumped in this patch, but
private testing has been done until to MAXCPU=128 on a real 8x8x2(htt)
machine (amd64).
Please note that the FreeBSD version is not yet bumped because of
the upcoming pcpu changes. However, note that this patch is not
targeted for MFC.
People to thank for the time spent on this patch:
- sbruno, pluknet and Nicholas Esborn (nick AT desert DOT net) tested
several revision of the patches and really helped in improving
stability of this work.
- marius fixed several bugs in the sparc64 implementation and reviewed
patches related to ktr.
- jeff and jhb discussed the basic approach followed.
- kib and marcel made targeted review on some specific part of the
patch.
- marius, art, nwhitehorn and andreast reviewed MD specific part of
the patch.
- marius, andreast, gonzo, nwhitehorn and jceel tested MD specific
implementations of the patch.
- Other people have made contributions on other patches that have been
already committed and have been listed separately.
Companies that should be mentioned for having participated at several
degrees:
- Yahoo! for having offered the machines used for testing on big
count of CPUs.
- The FreeBSD Foundation for having sponsored my devsummit attendance,
which has been instrumental.
- Sandvine for having offered offices and infrastructure during
development.
(I really hope I didn't forget anyone, if it happened I apologize in
advance).
|
| 221844 |
13-May-2011 |
cognet |
In pmap_change_wiring(), use the right argument for pmap_modify_pv().
It only worked because the only consumer calls pmap_change_wiring() to remove
the wiring.
|
| 221218 |
29-Apr-2011 |
jhb |
Change rman_manage_region() to actually honor the rm_start and rm_end
constraints on the rman and reject attempts to manage a region that is out
of range.
- Fix various places that set rm_end incorrectly (to ~0 or ~0u instead of
~0ul).
- To preserve existing behavior, change rman_init() to set rm_start and
rm_end to allow managing the full range (0 to ~0ul) if they are not set by
the caller when rman_init() is called.
|
| 221173 |
28-Apr-2011 |
attilio |
Add the watchdogs patting during the (shutdown time) disk syncing and
disk dumping.
With the option SW_WATCHDOG on, these operations are doomed to let
watchdog fire, fi they take too long.
I implemented the stubs this way because I really want wdog_kern_*
KPI to not be dependant by SW_WATCHDOG being on (and really, the option
only enables watchdog activation in hardclock) and also avoid to
call them when not necessary (avoiding not-volountary watchdog
activations).
Sponsored by: Sandvine Incorporated
Discussed with: emaste, des
MFC after: 2 weeks
|
| 219405 |
08-Mar-2011 |
dchagin |
Extend struct sysvec with new method sv_schedtail, which is used for an
explicit process at fork trampoline path instead of eventhadler(schedtail)
invocation for each child process.
Remove eventhandler(schedtail) code and change linux ABI to use newly added
sysvec method.
While here replace explicit comparing of module sysentvec structure with the
newly created process sysentvec to detect the linux ABI.
Discussed with: kib
MFC after: 2 Week
|
| 219134 |
01-Mar-2011 |
rwatson |
Continue to introduce Capsicum capability mode:
White list sysarch calls allowed in capability mode; arguably, there
should be some link between the capability mode model and the privilege
model here. Sysarch is a morass similar to ioctl, in many senses.
Submitted by: anderson
Discussed with: benl, kris, pjd
Sponsored by: Google, Inc.
Obtained from: Capsicum Project
MFC after: 3 months
|
| 218780 |
17-Feb-2011 |
marcel |
Fix the R_ARM_ABS32 relocation implementation. The memory address
contains the addend that we need to include.
Obtained from: Juniper Networks.
Fixed by: Santhanakrishnan Balraj <sbalraj@juniper.net>
|
| 218310 |
05-Feb-2011 |
imp |
Make md_tp a register_t not a void *. This will keep us from
accidentally dereferencng it and might be one fewer things to change
if arm64 happens...
Submitted by: rwatson's question on irc...
|
| 218227 |
03-Feb-2011 |
marcel |
Accept r1 as having the metadata pointer argument if r0 is 0.
This provides backward compatibility with Juniper loaders.
Sponsored by: Juniper Networks
|
| 218195 |
02-Feb-2011 |
mdf |
Put the general logic for being a CPU hog into a new function
should_yield(). Use this in various places. Encapsulate the common
case of check-and-yield into a new function maybe_yield().
Change several checks for a magic number of iterations to use
should_yield() instead.
MFC after: 1 week
|
| 217561 |
18-Jan-2011 |
kib |
For architectures not using direct map , and requiring real KVA page for
sf buf allocation, use wakeup() instead of wakeup_one() to notify sf
buffer waiters about free buffer.
sf_buf_alloc() calls msleep(PCATCH) when SFB_CATCH flag was given,
and for simultaneous wakeup and signal delivery, msleep() returns
EINTR/ERESTART despite the thread was selected for wakeup_one(). As
result, we loose a wakeup, and some other waiter will not be woken up.
Reported and tested by: az
Reviewed by: alc, jhb
MFC after: 1 week
|
| 217519 |
17-Jan-2011 |
jkim |
Remove empty dev_mem_md_init() stubs.
|
| 217515 |
17-Jan-2011 |
jkim |
Add reader/writer lock around mem_range_attr_get() and mem_range_attr_set().
Compile sys/dev/mem/memutil.c for all supported platforms and remove now
unnecessary dev_mem_md_init(). Consistently define mem_range_softc from
mem.c for all platforms. Add missing #include guards for machine/memdev.h
and sys/memrange.h. Clean up some nearby style(9) nits.
MFC after: 1 month
|
| 214835 |
05-Nov-2010 |
jhb |
Adjust the order of operations in spinlock_enter() and spinlock_exit() to
work properly with single-stepping in a kernel debugger. Specifically,
these routines have always disabled interrupts before increasing the nesting
count and restored the prior state of interrupts after decreasing the nesting
count to avoid problems with a nested interrupt not disabling interrupts
when acquiring a spin lock. However, trap interrupts for single-stepping
can still occur even when interrupts are disabled. Now the saved state of
interrupts is not saved in the thread until after interrupts have been
disabled and the nesting count has been increased. Similarly, the saved
state from the thread cannot be read once the nesting count has been
decreased to zero. To fix this, use temporary variables to store interrupt
state and shuffle it between the thread's MD area and the appropriate
registers.
In cooperation with: bde
MFC after: 1 month
|
| 214648 |
01-Nov-2010 |
cognet |
Try to be a little smart at guessing where _start is located in flash, instead
of relying on a binutils bug.
Reported by: dim
|
| 212825 |
18-Sep-2010 |
mav |
Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug's
heatsink termperature in open air from 49C to 43C when idle.
|
| 212507 |
12-Sep-2010 |
cognet |
In pmap_remove_all(), do not decrease pm_stats.wired_count if the mapping was
wired, as it's been done later in pmap_nuke_pv().
Submitted by: Mark Tinguely
|
| 212413 |
10-Sep-2010 |
avg |
bus_add_child: change type of order parameter to u_int
This reflects actual type used to store and compare child device orders.
Change is mostly done via a Coccinelle (soon to be devel/coccinelle)
semantic patch.
Verified by LINT+modules kernel builds.
Followup to: r212213
MFC after: 10 days
|
| 209613 |
30-Jun-2010 |
jhb |
Move prototypes for kern_sigtimedwait() and kern_sigprocmask() to
<sys/syscallsubr.h> where all other kern_<syscall> prototypes live.
|
| 209232 |
16-Jun-2010 |
raj |
Move ARM nexus rman initialization to attach routine.
This fixes a panic, which started to trigger after r209129 cleanup.
Submitted by: Andrew Turner
|
| 209223 |
15-Jun-2010 |
cognet |
Turn off cache if there's more than one kernel mapping, and one is writable.
Submitted by: Mark Tinguely
|
| 209129 |
13-Jun-2010 |
raj |
Improve style.
|
| 209048 |
11-Jun-2010 |
alc |
Relax one of the new assertions in pmap_enter() a little. Specifically,
allow pmap_enter() to be performed on an unmanaged page that doesn't have
VPO_BUSY set. Having VPO_BUSY set really only matters for managed pages.
(See, for example, pmap_remove_write().)
|
| 208990 |
10-Jun-2010 |
alc |
Reduce the scope of the page queues lock and the number of
PG_REFERENCED changes in vm_pageout_object_deactivate_pages().
Simplify this function's inner loop using TAILQ_FOREACH(), and shorten
some of its overly long lines. Update a stale comment.
Assert that PG_REFERENCED may be cleared only if the object containing
the page is locked. Add a comment documenting this.
Assert that a caller to vm_page_requeue() holds the page queues lock,
and assert that the page is on a page queue.
Push down the page queues lock into pmap_ts_referenced() and
pmap_page_exists_quick(). (As of now, there are no longer any pmap
functions that expect to be called with the page queues lock held.)
Neither pmap_ts_referenced() nor pmap_page_exists_quick() should ever
be passed an unmanaged page. Assert this rather than returning "0"
and "FALSE" respectively.
ARM:
Simplify pmap_page_exists_quick() by switching to TAILQ_FOREACH().
Push down the page queues lock inside of pmap_clearbit(), simplifying
pmap_clear_modify(), pmap_clear_reference(), and pmap_remove_write().
Additionally, this allows for avoiding the acquisition of the page
queues lock in some cases.
PowerPC/AIM:
moea*_page_exits_quick() and moea*_page_wired_mappings() will never be
called before pmap initialization is complete. Therefore, the check
for moea_initialized can be eliminated.
Push down the page queues lock inside of moea*_clear_bit(),
simplifying moea*_clear_modify() and moea*_clear_reference().
The last parameter to moea*_clear_bit() is never used. Eliminate it.
PowerPC/BookE:
Simplify mmu_booke_page_exists_quick()'s control flow.
Reviewed by: kib@
|
| 208846 |
05-Jun-2010 |
alc |
Don't set PG_WRITEABLE in pmap_enter() unless the page is managed.
Correct a typo in a nearby comment on sparc64.
|
| 208688 |
01-Jun-2010 |
alc |
In pmap_enter_locked(), don't require the vector page to be VPO_BUSY.
|
| 208574 |
26-May-2010 |
alc |
Push down page queues lock acquisition in pmap_enter_object() and
pmap_is_referenced(). Eliminate the corresponding page queues lock
acquisitions from vm_map_pmap_enter() and mincore(), respectively. In
mincore(), this allows some additional cases to complete without ever
acquiring the page queues lock.
Assert that the page is managed in pmap_is_referenced().
On powerpc/aim, push down the page queues lock acquisition from
moea*_is_modified() and moea*_is_referenced() into moea*_query_bit().
Again, this will allow some additional cases to complete without ever
acquiring the page queues lock.
Reorder a few statements in vm_page_dontneed() so that a race can't lead
to an old reference persisting. This scenario is described in detail by a
comment.
Correct a spelling error in vm_page_dontneed().
Assert that the object is locked in vm_page_clear_dirty(), and restrict the
page queues lock assertion to just those cases in which the page is
currently writeable.
Add object locking to vnode_pager_generic_putpages(). This was the one
and only place where vm_page_clear_dirty() was being called without the
object being locked.
Eliminate an unnecessary vm_page_lock() around vnode_pager_setsize()'s call
to vm_page_clear_dirty().
Change vnode_pager_generic_putpages() to the modern-style of function
definition. Also, change the name of one of the parameters to follow
virtual memory system naming conventions.
Reviewed by: kib
|
| 208504 |
24-May-2010 |
alc |
Roughly half of a typical pmap_mincore() implementation is machine-
independent code. Move this code into mincore(), and eliminate the
page queues lock from pmap_mincore().
Push down the page queues lock into pmap_clear_modify(),
pmap_clear_reference(), and pmap_is_modified(). Assert that these
functions are never passed an unmanaged page.
Eliminate an inaccurate comment from powerpc/powerpc/mmu_if.m:
Contrary to what the comment says, pmap_mincore() is not simply an
optimization. Without a complete pmap_mincore() implementation,
mincore() cannot return either MINCORE_MODIFIED or MINCORE_REFERENCED
because only the pmap can provide this information.
Eliminate the page queues lock from vfs_setdirty_locked_object(),
vm_pageout_clean(), vm_object_page_collect_flush(), and
vm_object_page_clean(). Generally speaking, these are all accesses
to the page's dirty field, which are synchronized by the containing
vm object's lock.
Reduce the scope of the page queues lock in vm_object_madvise() and
vm_page_dontneed().
Reviewed by: kib (an earlier version)
|
| 208453 |
23-May-2010 |
kib |
Reorganize syscall entry and leave handling.
Extend struct sysvec with three new elements:
sv_fetch_syscall_args - the method to fetch syscall arguments from
usermode into struct syscall_args. The structure is machine-depended
(this might be reconsidered after all architectures are converted).
sv_set_syscall_retval - the method to set a return value for usermode
from the syscall. It is a generalization of
cpu_set_syscall_retval(9) to allow ABIs to override the way to set a
return value.
sv_syscallnames - the table of syscall names.
Use sv_set_syscall_retval in kern_sigsuspend() instead of hardcoding
the call to cpu_set_syscall_retval().
The new functions syscallenter(9) and syscallret(9) are provided that
use sv_*syscall* pointers and contain the common repeated code from
the syscall() implementations for the architecture-specific syscall
trap handlers.
Syscallenter() fetches arguments, calls syscall implementation from
ABI sysent table, and set up return frame. The end of syscall
bookkeeping is done by syscallret().
Take advantage of single place for MI syscall handling code and
implement ptrace_lwpinfo pl_flags PL_FLAG_SCE, PL_FLAG_SCX and
PL_FLAG_EXEC. The SCE and SCX flags notify the debugger that the
thread is stopped at syscall entry or return point respectively. The
EXEC flag augments SCX and notifies debugger that the process address
space was changed by one of exec(2)-family syscalls.
The i386, amd64, sparc64, sun4v, powerpc and ia64 syscall()s are
changed to use syscallenter()/syscallret(). MIPS and arm are not
converted and use the mostly unchanged syscall() implementation.
Reviewed by: jhb, marcel, marius, nwhitehorn, stas
Tested by: marcel (ia64), marius (sparc64), nwhitehorn (powerpc),
stas (mips)
MFC after: 1 month
|
| 208175 |
16-May-2010 |
alc |
On entry to pmap_enter(), assert that the page is busy. While I'm
here, make the style of assertion used by pmap_enter() consistent
across all architectures.
On entry to pmap_remove_write(), assert that the page is neither
unmanaged nor fictitious, since we cannot remove write access to
either kind of page.
With the push down of the page queues lock, pmap_remove_write() cannot
condition its behavior on the state of the PG_WRITEABLE flag if the
page is busy. Assert that the object containing the page is locked.
This allows us to know that the page will neither become busy nor will
PG_WRITEABLE be set on it while pmap_remove_write() is running.
Correct a long-standing bug in vm_page_cowsetup(). We cannot possibly
do copy-on-write-based zero-copy transmit on unmanaged or fictitious
pages, so don't even try. Previously, the call to pmap_remove_write()
would have failed silently.
|
| 207954 |
12-May-2010 |
kevlo |
The FA526 belongs to the ARM9TDMI family
|
| 207796 |
08-May-2010 |
alc |
Push down the page queues into vm_page_cache(), vm_page_try_to_cache(), and
vm_page_try_to_free(). Consequently, push down the page queues lock into
pmap_enter_quick(), pmap_page_wired_mapped(), pmap_remove_all(), and
pmap_remove_write().
Push down the page queues lock into Xen's pmap_page_is_mapped(). (I
overlooked the Xen pmap in r207702.)
Switch to a per-processor counter for the total number of pages cached.
|
| 207611 |
04-May-2010 |
kevlo |
Add support for FA626TE.
Tested on GM8181 development board.
|
| 207410 |
30-Apr-2010 |
kmacy |
On Alan's advice, rather than do a wholesale conversion on a single
architecture from page queue lock to a hashed array of page locks
(based on a patch by Jeff Roberson), I've implemented page lock
support in the MI code and have only moved vm_page's hold_count
out from under page queue mutex to page lock. This changes
pmap_extract_and_hold on all pmaps.
Supported by: Bitgravity Inc.
Discussed with: alc, jeffr, and kib
|
| 207155 |
24-Apr-2010 |
alc |
Resurrect pmap_is_referenced() and use it in mincore(). Essentially,
pmap_ts_referenced() is not always appropriate for checking whether or
not pages have been referenced because it clears any reference bits
that it encounters. For example, in mincore(), clearing the reference
bits has two negative consequences. First, it throws off the activity
count calculations performed by the page daemon. Specifically, a page
on which mincore() has called pmap_ts_referenced() looks less active
to the page daemon than it should. Consequently, the page could be
deactivated prematurely by the page daemon. Arguably, this problem
could be fixed by having mincore() duplicate the activity count
calculation on the page. However, there is a second problem for which
that is not a solution. In order to clear a reference on a 4KB page,
it may be necessary to demote a 2/4MB page mapping. Thus, a mincore()
by one process can have the side effect of demoting a superpage
mapping within another process!
|
| 205642 |
25-Mar-2010 |
nwhitehorn |
Change the arguments of exec_setregs() so that it receives a pointer
to the image_params struct instead of several members of that struct
individually. This makes it easier to expand its arguments in the future
without touching all platforms.
Reviewed by: jhb
|
| 205425 |
21-Mar-2010 |
cognet |
Make sure we insert and remove the PV entries related to unmanaged kernel
mappings into the kernel pmap, not into the pmap related to the
pmap_enter_pv()/pmap_remove_pv() call.
|
| 205028 |
11-Mar-2010 |
raj |
Fix ARM cache handling yet more.
1) vm_machdep.c: remove the dangling allocations so they do not
un-necessarily turn off the cache upon consecutive access.
2) busdma_machdep.c: remove the same amount than shadow mapped.
Reported by: Maks Verver
Submitted by: Mark Tinguely
Reviewed by: Grzegorz Bernacki
MFC after: 3 days
|
| 205027 |
11-Mar-2010 |
raj |
Let detailed info about CPU features print on Marvell Sheeva CPU as well.
Provide missing entry in the cpu_classes[].
Reported by: Maks Verver
MFC after: 1 week
|
| 204122 |
20-Feb-2010 |
kevlo |
Show the cpu info for fa526
Submitted by: Yohanes Nugroho <yohanes at gmail dot com>
|
| 203974 |
16-Feb-2010 |
imp |
The NetBSD Foundation has granted permission to remove clauses 3 and 4.
Obtained from: NetBSD
|
| 203637 |
07-Feb-2010 |
raj |
Improve checking whether an ARM VA has a valid mapping before performing cache
sync.
VIPT/PIPT caches need valid VA-PA mapping in PTE for a cache operation to
succeed (unlike VIVT). Prior to this fix pmap was using l2pte_valid() for that
check, but this is not sufficient as the function merely checks if a PTE
exists (there can be existing but _invalid_ entries in the table).
A new pmap_has_valid_mapping() routine is introduced to do this job right by
checking proper PTE flags.
Among other potential problems this cures coherency issues with L2 caches on
MV-78100.
Submitted by: Grzegorz Bernacki, Piotr Ziecik
Reviewed, tested by: marcel
Obtained from: Semihalf
MFC after: 1 week
|
| 203171 |
29-Jan-2010 |
marcel |
When backtracing self, start with the current frame (i.e. the
frame of db_trace_self()) and not the caller's frame. The use
of builtin_frame_address(1) to get the caller's frame is not
reliable and can cause panics.
|
| 202353 |
15-Jan-2010 |
cognet |
Do not free the dmamap if it is still busy.
Submitted by: Mark Tinguely
MFC after: 3 days
|
| 201468 |
04-Jan-2010 |
rpaulo |
Add support for Cavium Econa CNS11XX ARM boards. These boards were
previously know by StarSemi STR9104.
Tested by the submitter on an Emprex NSD-100 board.
Submitted by: Yohanes Nugroho <yohanes at gmail.com>
Reviewed by: freebsd-arm, stas
Obtained from: //depot/projects/str91xx/...
|
| 201223 |
29-Dec-2009 |
rnoland |
Update d_mmap() to accept vm_ooffset_t and vm_memattr_t.
This replaces d_mmap() with the d_mmap2() implementation and also
changes the type of offset to vm_ooffset_t.
Purge d_mmap2().
All driver modules will need to be rebuilt since D_VERSION is also
bumped.
Reviewed by: jhb@
MFC after: Not in this lifetime...
|
| 199868 |
27-Nov-2009 |
alc |
Simplify the invocation of vm_fault(). Specifically, eliminate the flag
VM_FAULT_DIRTY. The information provided by this flag can be trivially
inferred by vm_fault().
Discussed with: kib
|
| 199135 |
10-Nov-2009 |
kib |
Extract the code that records syscall results in the frame into MD
function cpu_set_syscall_retval().
Suggested by: marcel
Reviewed by: marcel, davidxu
PowerPC, ARM, ia64 changes: marcel
Sparc64 tested and reviewed by: marius, also sunv reviewed
MIPS tested by: gonzo
MFC after: 1 month
|
| 198944 |
05-Nov-2009 |
marcel |
Fix gdb_cpu_getreg() to actually match GDB's register
definition.
|
| 198943 |
05-Nov-2009 |
marcel |
Implement db_trace_thread() by calling db_stack_trace_cmd() and
passing a frame pointer that comes from the thread context. This
fixes DDB backtraces by not unwinding debugger functions first.
|
| 198942 |
05-Nov-2009 |
marcel |
Implement db_trace_self() by calling db_stack_trace_cmd()
and not db_trace_thread().
|
| 198872 |
04-Nov-2009 |
alc |
Eliminate an unnecessary vm include file.
|
| 198507 |
27-Oct-2009 |
kib |
In r197963, a race with thread being selected for signal delivery
while in kernel mode, and later changing signal mask to block the
signal, was fixed for sigprocmask(2) and ptread_exit(3). The same race
exists for sigreturn(2), setcontext(2) and swapcontext(2) syscalls.
Use kern_sigprocmask() instead of direct manipulation of td_sigmask to
reschedule newly blocked signals, closing the race.
Reviewed by: davidxu
Tested by: pho
MFC after: 1 month
|
| 198341 |
21-Oct-2009 |
marcel |
o Introduce vm_sync_icache() for making the I-cache coherent with
the memory or D-cache, depending on the semantics of the platform.
vm_sync_icache() is basically a wrapper around pmap_sync_icache(),
that translates the vm_map_t argumument to pmap_t.
o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc
it replaces the pmap_page_executable() function, added to solve
the I-cache problem in uiomove_fromphys().
o In proc_rwmem() call vm_sync_icache() when writing to a page that
has execute permissions. This assures that when breakpoints are
written, the I-cache will be coherent and the process will actually
hit the breakpoint.
o This also fixes the Book-E PMAP implementation that was missing
necessary locking while trying to deal with the I-cache coherency
in pmap_enter() (read: mmu_booke_enter_locked).
The key property of this change is that the I-cache is made coherent
*after* writes have been done. Doing it in the PMAP layer when adding
or changing a mapping means that the I-cache is made coherent *before*
any writes happen. The difference is key when the I-cache prefetches.
|
| 197770 |
05-Oct-2009 |
stas |
- Drop unused pmap_use_l1 function and comment out currently unused
pmap_dcache_wbinv_all/pmap_copy_page functions which we might want
to take advatage of later. This fixes the build with PMAP_DEBUG
defined.
Discussed with: cognet
|
| 197733 |
03-Oct-2009 |
rpaulo |
Remove remaining bits of performance counter support.
Submitted by: Tom Judge <tom at tomjudge.com>
|
| 197729 |
03-Oct-2009 |
bz |
Make sure that the primary native brandinfo always gets added
first and the native ia32 compat as middle (before other things).
o(ld)brandinfo as well as third party like linux, kfreebsd, etc.
stays on SI_ORDER_ANY coming last.
The reason for this is only to make sure that even in case we would
overflow the MAX_BRANDS sized array, the native FreeBSD brandinfo
would still be there and the system would be operational.
Reviewed by: kib
MFC after: 1 month
|
| 197704 |
02-Oct-2009 |
rpaulo |
Remove performance counter headers. This code came from NetBSD, but our
hardware perf. counter support is different, so we don't need these
files.
Reviewed by: freebsd-arm (no comments)
|
| 197523 |
26-Sep-2009 |
rpaulo |
Promote the cpu_class local variable to global and expose it in md_var.h
Reviewed by: freebsd-arm
|
| 196730 |
01-Sep-2009 |
kib |
Reintroduce the r196640, after fixing the problem with my testing.
Remove the altkstacks, instead instantiate threads with kernel stack
allocated with the right size from the start. For the thread that has
kernel stack cached, verify that requested stack size is equial to the
actual, and reallocate the stack if sizes differ [1].
This fixes the bug introduced by r173361 that was committed several days
after r173004 and consisted of kthread_add(9) ignoring the non-default
kernel stack size.
Also, r173361 removed the caching of the kernel stacks for a non-first
thread in the process. Introduce separate kernel stack cache that keeps
some limited amount of preallocated kernel stacks to lower the latency
of thread allocation. Add vm_lowmem handler to prune the cache on
low memory condition. This way, system with reasonable amount of the
threads get lower latency of thread creation, while still not exhausting
significant portion of KVA for unused kstacks.
Submitted by: peter [1]
Discussed with: jhb, julian, peter
Reviewed by: jhb
Tested by: pho (and retested according to new test scenarious)
MFC after: 1 week
|
| 196648 |
29-Aug-2009 |
kib |
Reverse r196640 and r196644 for now.
|
| 196640 |
29-Aug-2009 |
kib |
Remove the altkstacks, instead instantiate threads with kernel stack
allocated with the right size from the start. For the thread that has
kernel stack cached, verify that requested stack size is equial to the
actual, and reallocate the stack if sizes differ [1].
This fixes the bug introduced by r173361 that was committed several days
after r173004 and consisted of kthread_add(9) ignoring the non-default
kernel stack size.
Also, r173361 removed the caching of the kernel stacks for a non-first
thread in the process. Introduce separate kernel stack cache that keeps
some limited amount of preallocated kernel stacks to lower the latency
of thread allocation. Add vm_lowmem handler to prune the cache on
low memory condition. This way, system with reasonable amount of the
threads get lower latency of thread creation, while still not exhausting
significant portion of KVA for unused kstacks.
Submitted by: peter [1]
Discussed with: jhb, julian, peter
Reviewed by: jhb
Tested by: pho
MFC after: 1 week
|
| 196484 |
23-Aug-2009 |
cognet |
KDB needs <machine/db_machdep.h>, so move it under #ifdef KDB.
While I'm there, remove dead code, we will never support acorn26.
|
| 196193 |
13-Aug-2009 |
raj |
Use correct wbinv operation in pmap_l2cache_wbinv_range().
Submitted by: Michal Hajduk
Reviewed by: stas
Approved by: re (kib)
Obtained from: Semihalf
|
| 196019 |
01-Aug-2009 |
rwatson |
Merge the remainder of kern_vimage.c and vimage.h into vnet.c and
vnet.h, we now use jails (rather than vimages) as the abstraction
for virtualization management, and what remained was specific to
virtual network stacks. Minor cleanups are done in the process,
and comments updated to reflect these changes.
Reviewed by: bz
Approved by: re (vimage blanket)
|
| 195840 |
24-Jul-2009 |
jhb |
Add a new type of VM object: OBJT_SG. An OBJT_SG object is very similar to
a device pager (OBJT_DEVICE) object in that it uses fictitious pages to
provide aliases to other memory addresses. The primary difference is that
it uses an sglist(9) to determine the physical addresses for a given offset
into the object instead of invoking the d_mmap() method in a device driver.
Reviewed by: alc
Approved by: re (kensmith)
MFC after: 2 weeks
|
| 195798 |
21-Jul-2009 |
raj |
Make dcache_inv_range() point to the proper routines on ARM9 and ARM9E/ARM10.
On some ARM variations CPU func dispatcher has the D-cache invalidate method
point to write-back invalidate, which is wrong, and can lead to a crash/panic
on affected platforms.
Spotted by: HPS
Reviewed by: cognet
Approved by: re (kib)
|
| 195779 |
20-Jul-2009 |
raj |
ARM pmap fixes.
a) nocache-remap problem
When a page is remapped into a non-cacheable virtual memory region there
was no associated write-back invalidate operation performed. We remove
writeback of the original buffer size from bus_dmamem_alloc() and add
appropriate L1/L2 flush operation.
b) missing write-back invalidate operation
In pmap_kremove a page is removed so we must do a write-back
invalidate operation aligned to the page virtual address.
Submitted by: Michal Hajduk
Reviewed by: Mark Tinguely, rpaulo, stas
Approved by: re (kib)
Obtained from: Semihalf
|
| 194908 |
24-Jun-2009 |
cognet |
Fix typo.
|
| 194906 |
24-Jun-2009 |
cognet |
Fix typo.
|
| 194784 |
23-Jun-2009 |
jeff |
Implement a facility for dynamic per-cpu variables.
- Modules and kernel code alike may use DPCPU_DEFINE(),
DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
PCPU_*. Requires only one extra instruction more than PCPU_* and is
virtually the same as __thread for builtin and much faster for shared
objects. DPCPU variables can be initialized when defined.
- Modules are supported by relocating the module's per-cpu linker set
over space reserved in the kernel. Modules may fail to load if there
is insufficient space available.
- Track space available for modules with a one-off extent allocator.
Free may block for memory to allocate space for an extent.
Reviewed by: jhb, rwatson, kan, sam, grehan, marius, marcel, stas
|
| 194609 |
21-Jun-2009 |
cognet |
Disable write-back until I figure out what's wrong with it on the i81342.
There's no need to disable the MMU once we're done inflating the kernel.
|
| 194459 |
18-Jun-2009 |
thompsa |
Track the kernel mapping of a physical page by a new entry in vm_page
structure. When the page is shared, the kernel mapping becomes a special
type of managed page to force the cache off the page mappings. This is
needed to avoid stale entries on all ARM VIVT caches, and VIPT caches
with cache color issue.
Submitted by: Mark Tinguely
Reviewed by: alc
Tested by: Grzegorz Bernacki, thompsa
|
| 193847 |
09-Jun-2009 |
marcel |
Pass the previously returned IRQ back to arm_get_next_irq() so that
the implementation can guarantee forward progress in the event of
a stuck interrupt or interrupt storm. This is especially critical
for fast interrupt handlers, as they can cause a hard hang in that
case. When first called, arm_get_next_irq() is passed -1.
Obtained from: Juniper Networks, Inc.
|
| 193846 |
09-Jun-2009 |
marcel |
Disable interrupts to allow booting on firmware (e.g. U-Boot) that
has interrupts enabled and active.
Obtained from: Juniper Networks, Inc.
|
| 193712 |
08-Jun-2009 |
raj |
Invalidate cache in pmap_remove_all() on ARM.
When pages are removed from virtual address space by calling pmap_remove_all()
CPU caches were not invalidated, which led to read corruption when another
page got mapped at this same virtual address at later time (the CPU was
retrieving stale contents).
Submitted by: Piotr Ziecik
Obtained from: Semihalf
|
| 193066 |
29-May-2009 |
jamie |
Place hostnames and similar information fully under the prison system.
The system hostname is now stored in prison0, and the global variable
"hostname" has been removed, as has the hostname_mtx mutex. Jails may
have their own host information, or they may inherit it from the
parent/system. The proper way to read the hostname is via
getcredhostname(), which will copy either the hostname associated with
the passed cred, or the system hostname if you pass NULL. The system
hostname can still be accessed directly (and without locking) at
prison0.pr_host, but that should be avoided where possible.
The "similar information" referred to is domainname, hostid, and
hostuuid, which have also become prison parameters and had their
associated global variables removed.
Approved by: bz (mentor)
|
| 192323 |
18-May-2009 |
marcel |
Add cpu_flush_dcache() for use after non-DMA based I/O so that a
possible future I-cache coherency operation can succeed. On ARM
for example the L1 cache can be (is) virtually mapped, which
means that any I/O that uses temporary mappings will not see the
I-cache made coherent. On ia64 a similar behaviour has been
observed. By flushing the D-cache, execution of binaries backed
by md(4) and/or NFS work reliably.
For Book-E (powerpc), execution over NFS exhibits SIGILL once in
a while as well, though cpu_flush_dcache() hasn't been implemented
yet.
Doing an explicit D-cache flush as part of the non-DMA based I/O
read operation eliminates the need to do it as part of the
I-cache coherency operation itself and as such avoids pessimizing
the DMA-based I/O read operations for which D-cache are already
flushed/invalidated. It also allows future optimizations whereby
the bcopy() followed by the D-cache flush can be integrated in a
single operation, which could be implemented using on-chips DMA
engines, by-passing the D-cache altogether.
|
| 191873 |
07-May-2009 |
alc |
Define the kernel pmap in the same way on arm as on every other
architecture.
Eliminate an unused definition.
Tested by: cognet
|
| 191817 |
05-May-2009 |
stas |
- Add support for PXA270 cpu.
Submitted by: Jacques Fourie <jacques.fourie@gmail.com>
|
| 191438 |
23-Apr-2009 |
jhb |
Reduce the number of bounce zones (and thus the number of bounce pages
used in some cases):
- Ignore DMA tag boundaries when allocating bounce pages. The boundaries
don't determine whether or not parts of a DMA request bounce. Instead,
they are just used to carve up segments.
- Allow tags with sub-page alignment to share bounce pages since bounce
pages are always page aligned.
Reviewed by: scottl (amd64)
MFC after: 1 month
|
| 191201 |
17-Apr-2009 |
jhb |
Restore bus DMA bounce pages to an offset of 0 when they are released by
a tag that has BUS_DMA_KEEP_PG_OFFSET set. Otherwise the page could be
reused with a non-zero offset by a tag that doesn't have
BUS_DMA_KEEP_PG_OFFSET leading to data corruption.
Sleuthing by: avg
Reviewed by: scottl
|
| 191141 |
16-Apr-2009 |
raj |
Minor style fixes and better comments.
|
| 191011 |
13-Apr-2009 |
kib |
The bus_dmamap_load_uio(9) shall use pmap of the thread recorded in the
uio_td to extract pages from, instead of unconditionally use kernel
pmap.
Submitted by: Jason Harmening <jason.harmening gmail com> (amd64 version)
PR: amd64/133592
Reviewed by: scottl (original patch), jhb
MFC after: 2 weeks
|
| 190845 |
08-Apr-2009 |
raj |
Minor description fix.
|
| 190844 |
08-Apr-2009 |
raj |
Properly handle KDB entry in fatal abort. This lets KDB_UNATTENDED work on ARM.
Submitted by: Grzegorz Bernacki gjb ! semihalf dot com
|
| 190708 |
05-Apr-2009 |
dchagin |
Fix KBI breakage by r190520 which affects older linux.ko binaries:
1) Move the new field (brand_note) to the end of the Brandinfo structure.
2) Add a new flag BI_BRAND_NOTE that indicates that the brand_note pointer
is valid.
3) Use the brand_note field if the flag BI_BRAND_NOTE is set and as old
modules won't have the flag set, so the new field brand_note would be
ignored.
Suggested by: jhb
Reviewed by: jhb
Approved by: kib (mentor)
MFC after: 6 days
|
| 190634 |
01-Apr-2009 |
jhb |
Remove some pointless mergeinfo that is the result of doing a local
'svn cp' and having svn create empty mergeinfo for the file.
|
| 190633 |
01-Apr-2009 |
piso |
Implement an ipfw action to reassemble ip packets: reass.
|
| 190602 |
31-Mar-2009 |
cognet |
Use Oxf0000000 instead of 0xff000000 to guess the physical address, relative
to the virtual one. I may had a reason at some point to use the later, but
can't remember which, and it can leads to issues.
Reported by: Guillaume Ballet <gballet gmail com>
|
| 190581 |
30-Mar-2009 |
mav |
Integrate user/mav/ata branch:
Add ch_suspend/ch_resume methods for PCI controllers and implement them
for AHCI. Refactor AHCI channel initialization according to it.
Fix Port Multipliers operation. It is far from perfect yet, but works now.
Tested with JMicron JMB363 AHCI + SiI 3726 PMP pair.
Previous version was also tested with SiI 4726 PMP.
Hardware sponsored by: Vitsch Electronics / VEHosting.nl
|
| 189771 |
13-Mar-2009 |
dchagin |
Implement new way of branding ELF binaries by looking to a
".note.ABI-tag" section.
The search order of a brand is changed, now first of all the
".note.ABI-tag" is looked through.
Move code which fetch osreldate for ELF binary to check_note() handler.
PR: 118473
Approved by: kib (mentor)
|
| 188581 |
13-Feb-2009 |
cognet |
Oops. ARM_RAS_END is ARM_TP_ADDRESS + 8, not 4.
Spotted out by: Mark Tinguely <tinguely at casselton d0t net>
|
| 188540 |
12-Feb-2009 |
cognet |
To prevent various race conditions in the RAS code, store and restore the
values in ARM_RAS_START and ARM_RAS_END at context switch time.
MFC after: 1 week
|
| 188539 |
12-Feb-2009 |
cognet |
Do not set thread0.td_frame to a bogus value, as it's going to overwrite the
thread0 pcb, while the board-dependant code already set a good trapframe.
Reported by: Mark Tinguely <tinguely at casselton d0t net>
MFC after: 1 week
|
| 188403 |
09-Feb-2009 |
cognet |
The bounce zone sees its page number increased if multiple dma maps use it in
the same dma tag. However, it can happen multiple dma tags share the same
bounce zone too, so add a per-bounce zone map counter, and check it instead of
the dma tag map counter, to know if we have to alloc more pages.
Reported by: miwi
Reviewed by: scottl
|
| 188350 |
08-Feb-2009 |
imp |
When bouncing pages, allow a new option to preserve the intra-page
offset. This is needed for the ehci hardware buffer rings that assume
this behavior.
This is an interim solution, and a more general one is being worked
on. This solution doesn't break anything that doesn't ask for it
directly. The mbuf and uio variants with this flag likely don't work
and haven't been tested.
Universe builds with these changes. I don't have a huge-memory
machine to test these changes with, but will be happy to work with
folks that do and hps if this changes turns out not to be sufficient.
Submitted by: alfred@ from Hans Peter Selasky's original
|
| 188112 |
04-Feb-2009 |
cognet |
Erm... Report the buffer as being bounced even when it's the entire buffer,
or we would end up invalidating the cache line for what we just copied...
Reported by: thompsa
Pointy at to: cognet
MFC after: 3 days
|
| 188019 |
02-Feb-2009 |
cognet |
Remove unused variables.
Spotted out by: Christoph Mallon <christoph d0t mallon AT gmx d0t de>
|
| 187911 |
30-Jan-2009 |
thompsa |
Increment total_bounced busdma stat as required.
|
| 187192 |
13-Jan-2009 |
thompsa |
Restore the if_*var.h and if_*reg.h to their original names, they dont need to
be different.
|
| 186934 |
09-Jan-2009 |
raj |
Rename Marvell ARM CPU specific file according to r186933.
|
| 186933 |
09-Jan-2009 |
raj |
Fix confusing naming of Marvell ARM CPU specific routines.
- The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the
new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon.
- Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does
not require dedicated routines.
This will be accompanied by a file rename commit.
|
| 186352 |
20-Dec-2008 |
sam |
Merge support for Gateworks Cambria boards:
o add support for IXP435 cpu's (e.g. 64 irq's)
o add support for Cambria-specific devices: npe, led's (front panel and
octal latch), ehci, mcu, ide cf
o redo memory mapping for xscale/ixp4xx boards: previously memory
was assumed aliased to 0x10000000 but this appears to be true only
for ixp425 systems and breaks operation on others; rework so memory
is assumed to start at 0
o rework NPE configuration support to use NPE id's instead of port #'s;
these changes also rename the associated MAC's to follow the NPE's
they are attached to
o update npe firmware to latest rev (same license) and update default fw
imageid's to match; in particular this adds NPE-A and crypto support
o re-style NPE fw handling code and add a console msg identifying the
attributes of the loaded fw
o fix numerous problems with handling failures during npe setup
o fix npe rx q setup; need to spin waiting for mailbox responses during
early boot stages as qmgr interrupts are not delivered; this fixes
the problem where all 8 traffic classifications were not tied to the
rx q (and eliminates the console msg "remember to fix rx q setup")
o add DELAY to npe MII wait logic for IXP435
o strip down builtin phys->virt address translation table in resource
handling to just those resources that require it and add a console msg
to alert people when this (kludge) table needs to be extended
o purge a bunch of dead netbsd-ism's
o cleanup avila led driver
o add Cambria support to boot2 and rework code for better multi-board support
Notes:
1. NPE-A doesn't work and causes NPE-C to stop working; it is disabled
in the hints
2. USB isn't working yet; controller communicates ok but device
discovery fails
3. Cambria support must be configured separately from IXP425 boards;
multi-board support is TBD
Sponsored by: Hobnob, Gateworks (board donation)
Reviewed by: imp
|
| 185494 |
30-Nov-2008 |
stas |
- Get rid of unused variable in KTR checks. This allows ktr(4) enabled
ARM kernel to compile.
PR: arm/128897
Submitted by: Pankov Pavel <pankov_p@mail.ru>
Reviewed by: raj
Approved by: kib (mentor, implicit)
MFC after: 1 week
|
| 185169 |
22-Nov-2008 |
kib |
Add sv_flags field to struct sysentvec with intention to provide description
of the ABI of the currently executing image. Change some places to test
the flags instead of explicit comparing with address of known sysentvec
structures to determine ABI features.
Discussed with: dchagin, imp, jhb, peter
|
| 184730 |
06-Nov-2008 |
raj |
ARM pmap style(9) and cosmetics.
|
| 184728 |
06-Nov-2008 |
raj |
Support kernel crash mini dumps on ARM architecture.
Obtained from: Juniper Networks, Semihalf
|
| 184205 |
23-Oct-2008 |
des |
Retire the MALLOC and FREE macros. They are an abomination unto style(9).
MFC after: 3 months
|
| 183958 |
16-Oct-2008 |
raj |
Eliminate flushing of L2 cache in ARM context switch routines.
With VIPT L2 cache such syncing not only is redundant, but also a performance
penalty.
Pointed out by: cognet
|
| 183878 |
14-Oct-2008 |
raj |
Initial support of loader(8) for ARM machines running U-Boot.
This uses the common U-Boot support lib (sys/boot/uboot, already used on
FreeBSD/powerpc), and assumes the underlying firmware has the modern API for
stand-alone apps enabled in the config (CONFIG_API).
Only netbooting is supported at the moment.
Obtained from: Marvell, Semihalf
|
| 183840 |
13-Oct-2008 |
raj |
Introduce basic support for Marvell families of system-on-chip ARM devices:
* Orion
- 88F5181
- 88F5182
- 88F5281
* Kirkwood
- 88F6281
* Discovery
- MV78100
The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:
* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART
Other peripherals drivers will be introduced separately.
Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf
|
| 183839 |
13-Oct-2008 |
raj |
One more L2 cache synchronization call that didn't make the previous commit.
|
| 183838 |
13-Oct-2008 |
raj |
Provide L2 cache synchronization (write back + invalidation) on ARM.
Note the cpu_l2cache_wbinv_* routines are no-ops on systems not populated with
L2 caches.
Obtained from: Marvell, Semihalf
|
| 183836 |
13-Oct-2008 |
raj |
Do not use cached page for temporary mapping in pmap_zero_page_generic()
The physical page which we clear is accessed via additional temp kernel
mapping for the period of zeroing operation. However in systems with virtual
d-cache (most ARMs) when write-allocate feature is enabled, we can have
modified but unflushed content pertaining to this physical page still in the
d-cache due to its primary (pre-existing) mapping. In such scenario that
cached content upon flush is likely to overwrite [portions of] the physical
page we want to zero here..
This is a general problem with multiple virtual mappings covering the same
physical page with write-allocate and virtual d-cache: there is inherent
potential for corruptions of this kind, which are not easily resolved; it is
best policy that such multiple mappings be not allowed.
Obtained from: Marvell, Semihalf
|
| 183835 |
13-Oct-2008 |
raj |
Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.
They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and
MV78100 (Discovery) system-on-chip families.
Obtained from: Marvell, Semihalf
|
| 183527 |
01-Oct-2008 |
peter |
Collect N identical (or near identical) mkdumpheader() implementations into
one, as threatened in the comment. Textdump magic can be passed in.
|
| 183429 |
28-Sep-2008 |
imp |
White space nit.
|
| 183397 |
27-Sep-2008 |
ed |
Replace all calls to minor() with dev2unit().
After I removed all the unit2minor()/minor2unit() calls from the kernel
yesterday, I realised calling minor() everywhere is quite confusing.
Character devices now only have the ability to store a unit number, not
a minor number. Remove the confusion by using dev2unit() everywhere.
This commit could also be considered as a bug fix. A lot of drivers call
minor(), while they should actually be calling dev2unit(). In -CURRENT
this isn't a problem, but it turns out we never had any problem reports
related to that issue in the past. I suspect not many people connect
more than 256 pieces of the same hardware.
Reviewed by: kib
|
| 183322 |
24-Sep-2008 |
kib |
Change the static struct sysentvec and struct Elf_Brandinfo initializers
to the C99 style. At least, it is easier to read sysent definitions
that way, and search for the actual instances of sigcode etc.
Explicitely initialize sysentvec.sv_maxssiz that was missed in most
sysvecs.
No objection from: jhb
MFC after: 1 month
|
| 182934 |
11-Sep-2008 |
raj |
ARM nexus style(9) improvements.
|
| 182933 |
11-Sep-2008 |
raj |
ARM interrupts improvements.
- Fix nexus_setup_intr() abuse of setting up multiple IRQs in one go. Calling
arm_setup_irqhandler() in loop is bogus, as there's just one cookie given
from the caller and it is overwritten in each iteration so that only the
last handler's cookie value prevails.
- Proper intr masking/unmasking handling: the IRQ source is masked at PIC level
only after the last handler has been removed from the list.
Reviewed by: cognet, imp, sam, stass
Obtained from: Grzegorz Bernacki gjb ! semihalf dot com
|
| 181803 |
17-Aug-2008 |
bz |
Commit step 1 of the vimage project, (network stack)
virtualization work done by Marko Zec (zec@).
This is the first in a series of commits over the course
of the next few weeks.
Mark all uses of global variables to be virtualized
with a V_ prefix.
Use macros to map them back to their global names for
now, so this is a NOP change only.
We hope to have caught at least 85-90% of what is needed
so we do not invalidate a lot of outstanding patches again.
Obtained from: //depot/projects/vimage-commit2/...
Reviewed by: brooks, des, ed, mav, julian,
jamie, kris, rwatson, zec, ...
(various people I forgot, different versions)
md5 (with a bit of help)
Sponsored by: NLnet Foundation, The FreeBSD Foundation
X-MFC after: never
V_Commit_Message_Reviewed_By: more people than the patch
|
| 181302 |
04-Aug-2008 |
cognet |
Do not modify td->td_intr_nesting_level, it is now done in the MI code.
This fixes the cpu time being falsely reported as interrupt time.
MFC after: 3 days
|
| 181296 |
04-Aug-2008 |
raj |
Fix ARM nocache allocator:
- let the loop iterate every page (as intended), and not some multiplies
(which led to a fake exhaustion of the ARM_NOCACHE_KVA_SIZE)
- eliminate using MIN(): it compared number of pages vs. address
(ARM_TP_ADDRESS), which was bogus
Reviewed by: cognet, imp
Obtained from: Piotr Ziecik kosmo ! semihalf dot com
MFC after: 3 days
|
| 181293 |
04-Aug-2008 |
cognet |
Remove unneeded #include <stdlib.h> (?)
MFC after: 3 days
|
| 181253 |
03-Aug-2008 |
cognet |
Add "add pc, whatever" as a branch instruction, we use it in memcpy().
MFC after: 3 days
|
| 181223 |
03-Aug-2008 |
cognet |
Handle ldr pc, [reg] in branch_taken().
Obtained from: NetBSD
MFC after: 3 days
|
| 181144 |
02-Aug-2008 |
cognet |
Store the PC while context switching, for the benefits of DDB.
|
| 179229 |
23-May-2008 |
alc |
The VM system no longer uses setPQL2(). Remove it and its helpers.
|
| 179081 |
18-May-2008 |
alc |
Retire pmap_addr_hint(). It is no longer used.
|
| 178893 |
09-May-2008 |
alc |
Add a stub for pmap_align_superpage() on machines that don't (yet)
implement pmap-level support for superpages.
|
| 178471 |
25-Apr-2008 |
jeff |
- Add an integer argument to idle to indicate how likely we are to wake
from idle over the next tick.
- Add a new MD routine, cpu_wake_idle() to wakeup idle threads who are
suspended in cpu specific states. This function can fail and cause the
scheduler to fall back to another mechanism (ipi).
- Implement support for mwait in cpu_idle() on i386/amd64 machines that
support it. mwait is a higher performance way to synchronize cpus
as compared to hlt & ipis.
- Allow selecting the idle routine by name via sysctl machdep.idle. This
replaces machdep.cpu_idle_hlt. Only idle routines supported by the
current machine are permitted.
Sponsored by: Nokia
|
| 178366 |
20-Apr-2008 |
cognet |
On the AT91, we need to write on the EOI register after we handle an
interrupt. So, add a new function pointer, arm_post_filter, which defaults
to NULL, and which will be used as the post_filter arg for
intr_event_create(). Set it properly for the AT91, so that it boots again.
Reported by: hps
|
| 178092 |
11-Apr-2008 |
jeff |
- Add the interrupt vector number to intr_event_create so MI code can
lookup hard interrupt events by number. Ignore the irq# for soft intrs.
- Add support to cpuset for binding hardware interrupts. This has the
side effect of binding any ithread associated with the hard interrupt.
As per restrictions imposed by MD code we can only bind interrupts to
a single cpu presently. Interrupts can be 'unbound' by binding them
to all cpus.
Reviewed by: jhb
Sponsored by: Nokia
|
| 178001 |
08-Apr-2008 |
kevlo |
Remove some long-dead code
Reviewed by: cognet
|
| 177940 |
05-Apr-2008 |
jhb |
Add a MI intr_event_handle() routine for the non-INTR_FILTER case. This
allows all the INTR_FILTER #ifdef's to be removed from the MD interrupt
code.
- Rename the intr_event 'eoi', 'disable', and 'enable' hooks to
'post_filter', 'pre_ithread', and 'post_ithread' to be less x86-centric.
Also, add a comment describe what the MI code expects them to do.
- On amd64, i386, and powerpc this is effectively a NOP.
- On arm, don't bother masking the interrupt unless the ithread is
scheduled in the non-INTR_FILTER case to match what INTR_FILTER did.
Also, don't bother unmasking the interrupt in the post_filter case if
we never masked it. The INTR_FILTER case had been doing this by having
arm_unmask_irq for the post_filter (formerly 'eoi') hook.
- On ia64, stray interrupts are now masked for the non-INTR_FILTER case.
They were already masked in the INTR_FILTER case.
- On sparc64, use the a NULL pre_ithread hook and use intr_enable_eoi() for
both the 'post_filter' and 'post_ithread' hooks to match what the
non-INTR_FILTER code did.
- On sun4v, retire the ithread wrapper hack by using an appropriate
'post_ithread' hook instead (it's what 'post_ithread'/'enable' was
designed to do even in 5.x).
Glanced at by: piso
Reviewed by: marius
Requested by: marius [1], [5]
Tested on: amd64, i386, arm, sparc64
|
| 177916 |
04-Apr-2008 |
raj |
Make kernel.tramp build properly on ARM9E.
Reviewed by: imp
Approved by: cognet (mentor)
|
| 177888 |
03-Apr-2008 |
raj |
Now really add the bus_space_generic.c file...
Reviewed by: sam
Approved by: cognet (mentor)
|
| 177883 |
03-Apr-2008 |
imp |
Take the first baby step towards unifying and cleaning up arminit():
- Pull all the code to deal with the trampoline stuff into one
centeralized place and use it from everywhere.
- Some minor style tidiness
Reviewed by: tinguely
|
| 177508 |
22-Mar-2008 |
cognet |
We need to prototype _start() as well, as we use it to test if we're running
from flash or from RAM.
Reported by: imp
MFC After: 3 days
|
| 177325 |
17-Mar-2008 |
jhb |
Simplify the interrupt code a bit:
- Always include the ie_disable and ie_eoi methods in 'struct intr_event'
and collapse down to one intr_event_create() routine. The disable and
eoi hooks simply aren't used currently in the !INTR_FILTER case.
- Expand 'disab' to 'disable' in a few places.
- Use function casts for arm and i386:intr_eoi_src() instead of wrapper
routines since to trim one extra indirection.
Compiled on: {arm,amd64,i386,ia64,ppc,sparc64} x {FILTER, !FILTER}
Tested on: {amd64,i386} x {FILTER, !FILTER}
|
| 177253 |
16-Mar-2008 |
rwatson |
In keeping with style(9)'s recommendations on macros, use a ';'
after each SYSINIT() macro invocation. This makes a number of
lightweight C parsers much happier with the FreeBSD kernel
source, including cflow's prcc and lxr.
MFC after: 1 month
Discussed with: imp, rink
|
| 177181 |
14-Mar-2008 |
jhb |
Add preliminary support for binding interrupts to CPUs:
- Add a new intr_event method ie_assign_cpu() that is invoked when the MI
code wishes to bind an interrupt source to an individual CPU. The MD
code may reject the binding with an error. If an assign_cpu function
is not provided, then the kernel assumes the platform does not support
binding interrupts to CPUs and fails all requests to do so.
- Bind ithreads to CPUs on their next execution loop once an interrupt
event is bound to a CPU. Only shared ithreads are bound. We currently
leave private ithreads for drivers using filters + ithreads in the
INTR_FILTER case unbound.
- A new intr_event_bind() routine is used to bind an interrupt event to
a CPU.
- Implement binding on amd64 and i386 by way of the existing pic_assign_cpu
PIC method.
- For x86, provide a 'intr_bind(IRQ, cpu)' wrapper routine that looks up
an interrupt source and binds its interrupt event to the specified CPU.
MI code can currently (ab)use this by doing:
intr_bind(rman_get_start(irq_res), cpu);
however, I plan to add a truly MI interface (probably a bus_bind_intr(9))
where the implementation in the x86 nexus(4) driver would end up calling
intr_bind() internally.
Requested by: kmacy, gallatin, jeff
Tested on: {amd64, i386} x {regular, INTR_FILTER}
|
| 177105 |
12-Mar-2008 |
raj |
Respect RF_SHAREABLE flag in ARM nexus_setup_intr()
Reviewed by: imp
Approved by: cognet (mentor)
|
| 177103 |
12-Mar-2008 |
raj |
Improve ARM bus_dmamap_load_buffer() error handling.
Reviewed by: imp
Approved by: cognet (mentor)
Spotted by: Grzegorz Bernacki gjb AT semihalf DOT com
|
| 177091 |
12-Mar-2008 |
jeff |
Remove kernel support for M:N threading.
While the KSE project was quite successful in bringing threading to
FreeBSD, the M:N approach taken by the kse library was never developed
to its full potential. Backwards compatibility will be provided via
libmap.conf for dynamically linked binaries and static binaries will
be broken.
|
| 176886 |
06-Mar-2008 |
cognet |
MFi386:
revision 1.6
date: 2004/08/21 18:50:34; author: alc; state: Exp; lines: +3 -1
Properly free the temporary sf_buf in uiomove_fromphys() if a copyin or
copyout fails.
Obtained from: DragonFlyBSD
Spotted out by: Mark Tinguely
MFC After: 3 days
|
| 176885 |
06-Mar-2008 |
cognet |
Remove unused pv_list_count from the vm_page, and pm_count from the struct
pmap.
Submitted by: Mark Tinguely
|
| 175983 |
05-Feb-2008 |
raj |
ARM locore cosmetics.
Approved by: cognet (mentor)
|
| 175982 |
05-Feb-2008 |
raj |
Improve ARM_TP_ADDRESS and RAS area.
De-hardcode usage of ARM_TP_ADDRESS and RAS local storage, and move this
special purpose page to a more convenient place i.e. after the vectors high
page, more towards the end of address space. Previous location (0xe000_0000)
caused grief if KVA was to go beyond the default limit.
Note that ARM world rebuilding is required after this change since the
location of ARM_TP_ADDRESS is shared between kernel and userland.
Submitted by: Grzegorz Bernacki (gjb AT semihalf dot com)
Reviewed by: imp
Approved by: cognet (mentor)
|
| 175840 |
31-Jan-2008 |
cognet |
Bring in the nice work from Mark Tinguely on arm pmap.
The only downside is that it renames pmap_vac_me_harder() to pmap_fix_cache().
From Mark's email on -arm :
pmap_get_vac_flags(), pmap_vac_me_harder(), pmap_vac_me_kpmap(), and
pmap_vac_me_user() has been rewritten as pmap_fix_cache() to be more
efficient in the kernel map case. I also removed the reference to
the md.kro_mappings, md.krw_mappings, md.uro_mappings, and md.urw_mappings
counts.
In pmap_clearbit(), we can also skip over tests and writeback/invalidations
in the PVF_MOD and PVF_REF cases if those bits are not set in the pv_flag.
PVF_WRITE will turn caching back on and remove the PV_MOD bit.
In pmap_nuke_pv(), the vm_page_flag_clear(pg, PG_WRITEABLE) has been moved
to the pmap_fix_cache().
We can be more agressive in attempting to turn caching back on by calling
pmap_fix_cache() at times that may be appropriate to turn cache on
(a kernel mapping has been removed, a write has been removed or a read
has been removed and we know the mapping does not have multiple write
mappings to a page).
In pmap_remove_pages() the cpu_idcache_wbinv_all() is moved to happen
before the page tables are NULLed because the caches are virtually
indexed and virtually tagged.
In pmap_remove_all(), the pmap_remove_write(m) is added before the
page tables are NULLed because the caches are virtually indexed and
virtually tagged. This also removes the need for the caches fixing routine
(whichever is being used pmap_vac_me_harder() or pmap_fix_cache()) to be
called on any of these mappings.
In pmap_remove(), I simplified the cache cleaning process and removed
extra TLB removals. Basically if more than PMAP_REMOVE_CLEAN_LIST_SIZE
are removed, then just flush the entire cache.
|
| 175768 |
28-Jan-2008 |
ru |
Add a wrapper function that bound checks writes to the dump device.
|
| 175397 |
17-Jan-2008 |
cognet |
Unbreak build by adding the missing parameter to pmap_enter().
|
| 175255 |
12-Jan-2008 |
cognet |
Back when I committed the arm port, I've been asked to move
memcpy/memset/memcmp and friends from libkern/arm to arm/arm/support.S, and so
I did, but in the process, I didn't add the appropriate copyrights.
This is a major oversight from me, and I apology to the NetBSD people for it.
MFC After: 1 day
|
| 175067 |
03-Jan-2008 |
alc |
Add an access type parameter to pmap_enter(). It will be used to implement
superpage promotion.
Correct a style error in kmem_malloc(): pmap_enter()'s last parameter is
a Boolean.
|
| 175066 |
03-Jan-2008 |
imp |
Use correct function name in panic message
|
| 175064 |
03-Jan-2008 |
imp |
Modernize comment about diagnostic.
|
| 174540 |
11-Dec-2007 |
cognet |
There's no need to call pmap_vac_me_harder() in pmap_protect(), as it
already happened in pmap_modify_pv().
Submitted by: Mark Tinguely <tinguely AT casselton DOT net>
|
| 174402 |
07-Dec-2007 |
cognet |
Fix style in previous commit.
Pointed out by: njl
|
| 174378 |
06-Dec-2007 |
cognet |
Erm, add a missing else, we do not want to increase the mapping counters for
both kernel and userland when we create a pv for pmap_kernel.
Reported by: Mark Tinguely <tinguely AT casselton DOT net>
MFC After: 3 days
|
| 174195 |
02-Dec-2007 |
rwatson |
Break out stack(9) from ddb(4):
- Introduce per-architecture stack_machdep.c to hold stack_save(9).
- Introduce per-architecture machine/stack.h to capture any common
definitions required between db_trace.c and stack_machdep.c.
- Add new kernel option "options STACK"; we will build in stack(9) if it is
defined, or also if "options DDB" is defined to provide compatibility
with existing users of stack(9).
Add new stack_save_td(9) function, which allows the capture of a stacktrace
of another thread rather than the current thread, which the existing
stack_save(9) was limited to. It requires that the thread be neither
swapped out nor running, which is the responsibility of the consumer to
enforce.
Update stack(9) man page.
Build tested: amd64, arm, i386, ia64, powerpc, sparc64, sun4v
Runtime tested: amd64 (rwatson), arm (cognet), i386 (rwatson)
|
| 174181 |
02-Dec-2007 |
cognet |
Fix a potential bug in pmap :
We used to allocate the domains 0-14 for userland, and leave the domain 15
for the kernel. Now supersections requires the use of domain 0, so we
switched the kernel domain to 0, and use 1-15 for userland.
How it's done currently, the kernel domain could be allocated for a
userland process.
So switch back to the previous way we did things, set the first available
domain to 0, and just add 1 to get the real domain number in the struct pmap.
Reported by: Mark Tinguely <tinguely AT casselton DOT net>
MFC After: 3 days
|
| 174172 |
02-Dec-2007 |
cognet |
Cleanup : make nexus standard, as it is mandatory anyway.
Garbage-collect unused nexus_io.c and nexus_io_asm.S
Submitted by: Rafal Jaworowski <raj AT semihalf DOT com>
|
| 174058 |
28-Nov-2007 |
cognet |
Fixes for ARM9/ARM10 :
Call uma_sel_align() there at well.
Set CPU_CONTROL_VECRELOC if we're using the high vectors page.
Submitted by: Rafal Jaworowski <raj AT semihalf DOT com>
MFC After: 1 week
|
| 174051 |
28-Nov-2007 |
cognet |
Correct the logic : we can just invalidate the cache lines, and not
write-back them, only if PREWRITE is not set, and if the buffer is
cache-line aligned.
MFC After: 1 week
|
| 173988 |
27-Nov-2007 |
jhb |
Remove the 'needbounce' variable from the _bus_dmamap_load_buffer()
routine. It is not needed as the existing tests for segment coalescing
already handle bounced addresses and it prevents legal segment coalescing
in certain edge cases.
MFC after: 1 week
Reviewed by: scottl
|
| 173708 |
17-Nov-2007 |
alc |
Prevent the leakage of wired pages in the following circumstances:
First, a file is mmap(2)ed and then mlock(2)ed. Later, it is truncated.
Under "normal" circumstances, i.e., when the file is not mlock(2)ed, the
pages beyond the EOF are unmapped and freed. However, when the file is
mlock(2)ed, the pages beyond the EOF are unmapped but not freed because
they have a non-zero wire count. This can be a mistake. Specifically,
it is a mistake if the sole reason why the pages are wired is because of
wired, managed mappings. Previously, unmapping the pages destroys these
wired, managed mappings, but does not reduce the pages' wire count.
Consequently, when the file is unmapped, the pages are not unwired
because the wired mapping has been destroyed. Moreover, when the vm
object is finally destroyed, the pages are leaked because they are still
wired. The fix is to reduce the pages' wired count by the number of
wired, managed mappings destroyed. To do this, I introduce a new pmap
function pmap_page_wired_mappings() that returns the number of managed
mappings to the given physical page that are wired, and I use this
function in vm_object_page_remove().
Reviewed by: tegge
MFC after: 6 weeks
|
| 173615 |
14-Nov-2007 |
marcel |
o Rename cpu_thread_setup() to cpu_thread_alloc() to better
communicate that it relates to (is called by) thread_alloc()
o Add cpu_thread_free() which is called from thread_free()
to counter-act cpu_thread_alloc().
i386: Have cpu_thread_free() call cpu_thread_clean() to
preserve behaviour.
ia64: Have cpu_thread_free() call mtx_destroy() for the
mutex initialized in cpu_thread_alloc().
PR: ia64/118024
|
| 173600 |
14-Nov-2007 |
julian |
generally we are interested in what thread did something as
opposed to what process. Since threads by default have teh name of the
process unless over-written with more useful information, just print the
thread name instead.
|
| 173442 |
08-Nov-2007 |
cognet |
Add entries for the L2 cache-related functions for armv5.
Spotted out by: Rafal Jaworowski
|
| 173361 |
05-Nov-2007 |
kib |
Fix for the panic("vm_thread_new: kstack allocation failed") and
silent NULL pointer dereference in the i386 and sparc64 pmap_pinit()
when the kmem_alloc_nofault() failed to allocate address space. Both
functions now return error instead of panicing or dereferencing NULL.
As consequence, vmspace_exec() and vmspace_unshare() returns the errno
int. struct vmspace arg was added to vm_forkproc() to avoid dealing
with failed allocation when most of the fork1() job is already done.
The kernel stack for the thread is now set up in the thread_alloc(),
that itself may return NULL. Also, allocation of the first process
thread is performed in the fork1() to properly deal with stack
allocation failure. proc_linkup() is separated into proc_linkup()
called from fork1(), and proc_linkup0(), that is used to set up the
kernel process (was known as swapper).
In collaboration with: Peter Holm
Reviewed by: jhb
|
| 173215 |
31-Oct-2007 |
kevlo |
Don't define get_cachetype() for CPU_ARM9E unless it's going to be used.
|
| 172738 |
18-Oct-2007 |
imp |
Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not
yet connected to the build, but reduces diffs to p4 repo.
Obtained from: NetBSD
|
| 172713 |
16-Oct-2007 |
cognet |
Use the direct mapping, if available, for pmap_zero_page_xscale() as well.
|
| 172614 |
13-Oct-2007 |
cognet |
Do not use __XSCALE__ to detect if pld/strd/ldrd is available, use
_ARM_ARCH_5E instead.
MFC After: 3 days
|
| 172356 |
27-Sep-2007 |
cognet |
Fix a comment to reflect the truth.
Spotted out by: Marius Nuennerich <marius.nuennerich AT gmx D0T de>
Approved by: re (blanket)
|
| 172300 |
22-Sep-2007 |
cognet |
Make sure we do not call _arm_bzero() or _arm_memcpy() if the size is not at
least the minimum asked by the driver.
Approved by: re (blanket)
|
| 172245 |
19-Sep-2007 |
cognet |
Remove dead code.
Approved by: re (blanket)
Beer from: jadawin
|
| 172189 |
15-Sep-2007 |
alc |
It has been observed on the mailing lists that the different categories
of pages don't sum to anywhere near the total number of pages on amd64.
This is for the most part because uma_small_alloc() pages have never been
counted as wired pages, like their kmem_malloc() brethren. They should
be. This changes fixes that.
It is no longer necessary for the page queues lock to be held to free
pages allocated by uma_small_alloc(). I removed the acquisition and
release of the page queues lock from uma_small_free() on amd64 and ia64
weeks ago. This patch updates the other architectures that have
uma_small_alloc() and uma_small_free().
Approved by: re (kensmith)
|
| 171890 |
18-Aug-2007 |
cognet |
Just wbinv if both PREREAD and PREWRITE are set.
In PREREAD, just invalidate the cache lines, and do not write back them, if
the buffer is properly aligned.
Approved by: re (blanket)
|
| 171788 |
08-Aug-2007 |
cognet |
Ooops, we need to define TD_LOCK here.
Approved by: re (blanket)
Pointy hat to: cognet
|
| 171781 |
07-Aug-2007 |
cognet |
Add cast to silent gcc warnings.
Approved by: re (blanket)
|
| 171780 |
07-Aug-2007 |
cognet |
Use the third argument of cpu_switch(), as done for i386/amd63, as it is
required for ULE.
Approved by: re (blanket)
|
| 171672 |
31-Jul-2007 |
cognet |
MFppc:
revision 1.66
date: 2007/07/31 06:23:26; author: marcel; state: Exp; lines: +2 -2
Fix backward compatibility of the "old" (i.e. FreeBSD6) lseek
syscall. It was broken when a new lseek syscall was introduced.
The problem is that we need to swap the 32-bit td_retval values
for the __syscall indirect syscall when the actual syscall has
a 32-bit return value. Hence, we need to exclude lseek(2). And
this means the "old" lseek(2) as well -- which we didn't.
Based on a patch from: grehan@
Approved by: re (blanket)
|
| 171625 |
27-Jul-2007 |
cognet |
Say if the L2 cache is enabled or disabled as well.
Approved by: re (blanket)
|
| 171623 |
27-Jul-2007 |
cognet |
Handle supersections and L2 cache.
Approved by: re (blanket)
|
| 171622 |
27-Jul-2007 |
cognet |
Use supersection instead of standard sections to map the whole memory
when available.
Approved by: re (blanket)
|
| 171620 |
27-Jul-2007 |
cognet |
Properly handle supersections.
Make sure we cache entries in the L2 cache.
Approved by: re (blanket)
|
| 171619 |
27-Jul-2007 |
cognet |
Bring in two bandaids to get the elf trampoline to work again, until I find
a proper solution.
- Add a dummy entry point which just calls the C entry points, and try to make
sure it's the first code in the binary.
- Copy a bit more than func_end to try to copy the whole load_kernel()
function. gcc4 puts code behind the func_end symbol.
Approved by: re (blanket)
|
| 171618 |
27-Jul-2007 |
cognet |
Add a new set of functions to handle L2 cache. Make them no-op for every
CPU except Xscale core 3.
Approved by: re (blanket)
|
| 171617 |
27-Jul-2007 |
cognet |
Import xscale core 3 cache management functions.
Approved by: re (blanket)
|
| 171616 |
27-Jul-2007 |
cognet |
INTR_FILTER bits for arm
Approved by: re (blanket)
|
| 170582 |
11-Jun-2007 |
cognet |
Introduce pmap_kenter_supersection(), which maps 16MB super-sections into
the kernel pmap.
Document a bit more the behavior of the xscale core 3.
|
| 170502 |
10-Jun-2007 |
cognet |
Initialize the dma tag's bounce_zone to NULL if we didn't allocate it.
|
| 170406 |
07-Jun-2007 |
cognet |
There's no nobounce_dmamap on arm.
|
| 170305 |
04-Jun-2007 |
jeff |
- Change comments and asserts to reflect the removal of the global
scheduler lock.
Tested by: kris, current@
Tested on: i386, amd64, ULE, 4BSD, libthr, libkse, PREEMPTION, etc.
Discussed with: kris, attilio, kmacy, jhb, julian, bde (small parts each)
|
| 170291 |
04-Jun-2007 |
attilio |
Rework the PCPU_* (MD) interface:
- Rename PCPU_LAZY_INC into PCPU_INC
- Add the PCPU_ADD interface which just does an add on the pcpu member
given a specific value.
Note that for most architectures PCPU_INC and PCPU_ADD are not safe.
This is a point that needs some discussions/work in the next days.
Reviewed by: alc, bde
Approved by: jeff (mentor)
|
| 170170 |
31-May-2007 |
attilio |
Revert VMCNT_* operations introduction.
Probabilly, a general approach is not the better solution here, so we should
solve the sched_lock protection problems separately.
Requested by: alc
Approved by: jeff (mentor)
|
| 170162 |
31-May-2007 |
piso |
In some particular cases (like in pccard and pccbb), the real device
handler is wrapped in a couple of functions - a filter wrapper and an
ithread wrapper. In this case (and just in this case), the filter
wrapper could ask the system to schedule the ithread and mask the
interrupt source if the wrapped handler is composed of just an ithread
handler: modify the "old" interrupt code to make it support
this situation, while the "new" interrupt code is already ok.
Discussed with: jhb
|
| 170086 |
29-May-2007 |
yongari |
Honor maxsegsz of less than a page size in a DMA tag. Previously it
used to return PAGE_SIZE without respect to restrictions of a DMA tag.
This affected all of the busdma load functions that use
_bus_dmamap_loader_buffer() as their back-end.
Reviewed by: scottl
|
| 169900 |
23-May-2007 |
cognet |
Remove duplicate includes.
Submitted by: Cyril Nguyen Huu <cyril ci0 org>
|
| 169846 |
22-May-2007 |
kan |
Allow FreeBSD's native ELF image activators to execute shared libraries the
same way it was enabled for Linux binares in linuxulator.
This allows binaries built with -pie. Many ports auto-detect -fPIE support
in GCC 4.2 and build binaries FreeBSD was unable to run.
|
| 169764 |
19-May-2007 |
cognet |
Constify to please gcc 4.2.
|
| 169763 |
19-May-2007 |
cognet |
Do not try to inline pmap_kremove(), as it's exported.
|
| 169761 |
19-May-2007 |
cognet |
Do not try to inline bus_dmamap_sync_buf(), gcc 4.2 doesn't want to do so
because it uses alloca().
Initialize lastaddr in bus_dmamap_load_uio().
|
| 169756 |
19-May-2007 |
cognet |
Switch the kernel's pmap domain from 15 to 0.
This should be a no-op, and this is needed for xscale core 3 supersections
support, as they are always part of the domain 0
|
| 169667 |
18-May-2007 |
jeff |
- define and use VMCNT_{GET,SET,ADD,SUB,PTR} macros for manipulating
vmcnts. This can be used to abstract away pcpu details but also changes
to use atomics for all counters now. This means sched lock is no longer
responsible for protecting counts in the switch routines.
Contributed by: Attilio Rao <attilio@FreeBSD.org>
|
| 167761 |
21-Mar-2007 |
kevlo |
Fix a comment
|
| 167009 |
26-Feb-2007 |
kevlo |
Remove unused header file <machine/katelib.h>
|
| 167003 |
26-Feb-2007 |
cognet |
Erm we can't change the value of arm_memcpy if we're running from flash.
Instead, make memcpy() check if we're running from flash, and avoid
using arm_memcpy if we're doing so.
|
| 166901 |
23-Feb-2007 |
piso |
o break newbus api: add a new argument of type driver_filter_t to
bus_setup_intr()
o add an int return code to all fast handlers
o retire INTR_FAST/IH_FAST
For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current
Reviewed by: many
Approved by: re@
|
| 166819 |
19-Feb-2007 |
cognet |
Teach the kernel and the ELF trampoline how to boot from onboard flash.
|
| 166697 |
14-Feb-2007 |
kevlo |
Add KTR tracing
|
| 166695 |
14-Feb-2007 |
kevlo |
style(9) cleanup.
|
| 166694 |
14-Feb-2007 |
kevlo |
In sendsig:
- Add sigacts locking.
- Add a mutex to struct sigacts that protects all the members of the struct.
- Create and log events via the CTRx macros.
Reviewed by: cognet
|
| 166688 |
13-Feb-2007 |
cognet |
Make sure the address is valid before mapping it.
MFC after: 1 week
|
| 166686 |
13-Feb-2007 |
kevlo |
Fix typo: MacPPC -> ARM
|
| 166655 |
11-Feb-2007 |
cognet |
Use uma_set_align().
|
| 166510 |
05-Feb-2007 |
kevlo |
<sys/sx.h> is unneeded.
|
| 166063 |
17-Jan-2007 |
cognet |
- Add bounce pages for arm, largely based on the i386 implementation.
- Add a default parent dma tag, similar to what has been done for sparc64.
- Before invalidating the dcache in POSTREAD, save the bits which are in the
same cachelines than our buffers, but not part of it, and restore them after
the invalidation.
|
| 164874 |
04-Dec-2006 |
cognet |
Do not forget to call pmap_free_l2_bucket() in pmap_remove_pages().
This can fix the pmap-related panics reported on arm.
MFC After: 3 days
|
| 164790 |
01-Dec-2006 |
cognet |
We can have no PV entry here if the previous mapping was unmanaged, and the new
one is unmanaged too, so update the KASSERT to reflect this.
|
| 164779 |
30-Nov-2006 |
cognet |
In pmap_ts_referenced(), don't attempt to do anything if the page is
fictitious, and just return 0.
|
| 164778 |
30-Nov-2006 |
cognet |
First bits of Xscale core 3 support (the VM bits are far from being optimal
yet).
|
| 164760 |
30-Nov-2006 |
jb |
Turn console printf buffering into a kernel option and only on
by default for sun4v where it is absolutely required.
This change moves the buffer from struct pcpu to the stack to avoid
using the critical section which created a LOR in a couple of cases
due to interaction with the tty code and kqueue. The LOR can't be
fixed with the critical section and the pcpu buffer can't be used
without the critical section.
Putting the buffer on the stack was my initial solution, but it was
pointed out that the stress on the stack might cause problems
depending on the call path. We don't have a way of creating tests
for those possible cases, so it's best to leave this as an option
for the time being. In time we may get enough data to enable this
option more generally.
|
| 164426 |
19-Nov-2006 |
sam |
Gateworks Avila board support:
o ixp425 support
o NPE network driver (requires Intel microcode)
o h/w qmgr support
o True IDE compact flash over expansion bus
o pci (ath and hifn795x parts tested)
o xscale watchdog timer
o ds1672 RTC on i2c bus
o ad7418 voltage + temp monitoring on i2c bus
o uart
Work done together with cognet, kevlo, and jmg. Parts of
the ixp425 support obtaine/derived from netbsd.
Reviewed by: cognet, imp
MFC after: 1 month
|
| 164424 |
19-Nov-2006 |
sam |
correct bus space unmap prototype
Reviewed by: cognet, imp
MFC after: 1 month
|
| 164423 |
19-Nov-2006 |
sam |
elaborate on stepping names; add intel terminology to help
people cross-referencing intel docs
Reviewed by: imp, cognet
MFC after: 1 month
|
| 164355 |
17-Nov-2006 |
cognet |
Erm we really want to mask all interrupts in the range, just not the first
one.
Submitted by: ru
|
| 164229 |
12-Nov-2006 |
alc |
Make pmap_enter() responsible for setting PG_WRITEABLE instead
of its caller. (As a beneficial side-effect, a high-contention
acquisition of the page queues lock in vm_fault() is eliminated.)
|
| 164198 |
11-Nov-2006 |
alc |
Eliminate unused global variables.
|
| 164090 |
08-Nov-2006 |
alc |
MFamd64/ia64/i386/sun4v
Use cnt.v_page_count, the actual count of available physical pages,
instead of vm_page_array_size to compute the maximum number of pv
entries.
|
| 164087 |
08-Nov-2006 |
cognet |
Increate cnt.v_intr on interrupt.
|
| 164080 |
07-Nov-2006 |
cognet |
Identify the xscale 81342.
|
| 164079 |
07-Nov-2006 |
cognet |
In the ARM_USE_SMALL_ALLOC case, vm_page_t may have an address < KERNBASE,
so adjust the KASSERT to reflect this.
|
| 163871 |
01-Nov-2006 |
cognet |
Do not include both <sys/types.h> and <sys/param.h>, it is a style bug as
sys/types.h is included in sys/param.h, so instead just move the
#include <sys/param.h> before the headers that need it.
Spotted out by: bde
|
| 163858 |
01-Nov-2006 |
jb |
Add a cnputs() function to write a string to the console with
a lock to prevent interspersed strings written from different CPUs
at the same time.
To avoid putting a buffer on the stack or having to malloc one,
space is incorporated in the per-cpu structure. The buffer
size if 128 bytes; chosen because it's the next power of 2 size
up from 80 characters.
String writes to the console are buffered up the end of the line
or until the buffer fills. Then the buffer is flushed to all
console devices.
Existing low level console output via cnputc() is unaffected by
this change. ithread calls to log() are also unaffected to avoid
blocking those threads.
A minor change to the behaviour in a panic situation is that
console output will still be buffered, but won't be written to
a tty as before. This should prevent interspersed panic output
as a number of CPUs panic before we end up single threaded
running ddb.
Reviewed by: scottl, jhb
MFC after: 2 weeks
|
| 163810 |
30-Oct-2006 |
cognet |
Include <sys/types.h>, to get definition for uint32_t.
Submitted by: David Sharp
|
| 163709 |
26-Oct-2006 |
jb |
Make KSE a kernel option, turned on by default in all GENERIC
kernel configs except sun4v (which doesn't process signals properly
with KSE).
Reviewed by: davidxu@
|
| 163694 |
25-Oct-2006 |
cognet |
Let allow to teardown multiple irqs as well.
|
| 163693 |
25-Oct-2006 |
cognet |
Setup multiple interrupts if needed.
|
| 163674 |
24-Oct-2006 |
cognet |
Ooops, dump_avail[i] can be 0 if the RAM starts at 0x00000000, so check that
dump_avail[i + 1] is == 0 as a stop condition instead.
MFC after: 3 days
|
| 163553 |
21-Oct-2006 |
kevlo |
style(9) cleanup.
Approved by: cognet
|
| 163551 |
21-Oct-2006 |
cognet |
Ok I am an idiot. On 32 bits big-endian systems, it is needed to handle the
syscalls using __syscall but only actually returning 32bits, such as mmap(),
specially : they set the return value in td->td_retval[0], but the userland
functions will expect this in r1, and not in r0 as it is normally done, as it
is the LSB. So add a special case for all these syscalls (all except lseek,
which truly returns 64bits).
Many thanks to Peter Grehan for his patience while explaining me the issue.
|
| 163547 |
20-Oct-2006 |
cognet |
Use __QUAD_LOWWORD for __syscall, to always use the good word, whatever the
endianness is.
|
| 163537 |
20-Oct-2006 |
cognet |
There's no need to special-case lseek for arm/big-endian.
|
| 163449 |
17-Oct-2006 |
davidxu |
o Add keyword volatile for user mutex owner field.
o Fix type consistent problem by using type long for old
umtx and wait channel.
o Rename casuptr to casuword.
|
| 161734 |
30-Aug-2006 |
cognet |
Use ENTRY_NP for alternate entry points instead of ENTRY to avoid calling
mcount twice when profiling.
Spotted out by: bde
|
| 161727 |
29-Aug-2006 |
cognet |
Use ENTRY instead of ALTENTRY, it doesn't exist on arm.
|
| 161705 |
28-Aug-2006 |
cognet |
Ooops m->md.pvh_attrs can't be used to know if the page is writeable, because
it only remembers if the page is modified or referenced.
Bad review from: cognet
|
| 161675 |
28-Aug-2006 |
davidxu |
Implement casuword32, compare and set user integer, thank Marcel Moolenarr
who wrote the IA64 version of casuword32.
|
| 161618 |
25-Aug-2006 |
cognet |
Explicitely set the "allocbuffer" field to NULL when creating a new dmamap.
|
| 161592 |
24-Aug-2006 |
cognet |
Finally bring it support for the i80219 XScale processor.
Submitted by: Max M. Boyarov <m.boyarov bsd by>
|
| 161334 |
15-Aug-2006 |
imp |
add comment about why we include opt_global.h
|
| 161323 |
15-Aug-2006 |
cognet |
Ooops we need to include <machine/vmparam.h> to get the definition of
KERNBASE and VM_MAXUSER_ADDRESS.
Remove the useless include of opt_global.h, as noticed by netchild@ (the one
in arm/elf_trampoline.c is legit, because this file is compiled outside the
kernel, and doesn't use the standard CFLAGS).
|
| 161105 |
08-Aug-2006 |
cognet |
Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it maps
whole the physical memory, cached, using 1MB section mappings. This reduces
the address space available for user processes a bit, but given the amount of
memory a typical arm machine has, it is not (yet) a big issue.
It then provides a uma_small_alloc() that works as it does for architectures
which have a direct mapping.
|
| 160889 |
01-Aug-2006 |
alc |
Complete the transition from pmap_page_protect() to pmap_remove_write().
Originally, I had adopted sparc64's name, pmap_clear_write(), for the
function that is now pmap_remove_write(). However, this function is more
like pmap_remove_all() than like pmap_clear_modify() or
pmap_clear_reference(), hence, the name change.
The higher-level rationale behind this change is described in
src/sys/amd64/amd64/pmap.c revision 1.567. The short version is that I'm
trying to clean up and fix our support for execute access.
Reviewed by: marcel@ (ia64)
|
| 160801 |
28-Jul-2006 |
jhb |
Retire SYF_ARGMASK and remove both SYF_MPSAFE and SYF_ARGMASK. sy_narg is
now back to just being an argument count.
|
| 160798 |
28-Jul-2006 |
jhb |
Now that all system calls are MPSAFE, retire the SYF_MPSAFE flag used to
mark system calls as being MPSAFE:
- Stop conditionally acquiring Giant around system call invocations.
- Remove all of the 'M' prefixes from the master system call files.
- Remove support for the 'M' prefix from the script that generates the
syscall-related files from the master system call files.
- Don't explicitly set SYF_MPSAFE when registering nfssvc.
|
| 160773 |
27-Jul-2006 |
jhb |
Unify the checking for lock misbehavior in the various syscall()
implementations and adjust some of the checks while I'm here:
- Add a new check to make sure we don't return from a syscall in a critical
section.
- Add a new explicit check before userret() to make sure we don't return
with any locks held. The advantage here is that we can include the
syscall number and name in syscall() whereas that info is not available
in userret().
- Drop the mtx_assert()'s of sched_lock and Giant. They are replaced by
the more general checks just added.
MFC after: 2 weeks
|
| 160537 |
20-Jul-2006 |
alc |
Implement pmap_clear_write().
Discussed with: cognet@
|
| 160459 |
18-Jul-2006 |
cognet |
Make sure we use REDUCE32 on the result of do_cksum(), as in_cksum_skip()
expects this. If we do not, this could result in wrong checksums.
MFC after: 1 day
|
| 160393 |
15-Jul-2006 |
cognet |
Oops bring back code that shouldn't have been removed by the previous
commit.
|
| 160392 |
15-Jul-2006 |
cognet |
Make sure that if uma_small_alloc() gets called recursively, we just give up
and call kmem_malloc(), to avoid a deadlock.
|
| 160332 |
14-Jul-2006 |
cognet |
Add remote GDB bits for arm.
|
| 160312 |
12-Jul-2006 |
jhb |
Simplify the pager support in DDB. Allowing different db commands to
install custom pager functions didn't actually happen in practice (they
all just used the simple pager and passed in a local quit pointer). So,
just hardcode the simple pager as the only pager and make it set a global
db_pager_quit flag that db commands can check when the user hits 'q' (or a
suitable variant) at the pager prompt. Also, now that it's easy to do so,
enable paging by default for all ddb commands. Any command that wishes to
honor the quit flag can do so by checking db_pager_quit. Note that the
pager can also be effectively disabled by setting $lines to 0.
Other fixes:
- 'show idt' on i386 and pc98 now actually checks the quit flag and
terminates early.
- 'show intr' now actually checks the quit flag and terminates early.
|
| 160260 |
11-Jul-2006 |
cognet |
Add a new flag to pmap_enter_locked() to say if it's OK to wait. If it is, and
we're unable to allocate the memory for a PTE, we'll wait until we can. If not,
we'll just return.
Use M_NOWAIT|M_USE_RESERVE to allocate PTEs, it is less aggressive than
M_NOWAIT alone.
Suggested by: alc
|
| 159901 |
23-Jun-2006 |
cognet |
There's no need to allocate that much phdr/shdr from the stack.
|
| 159900 |
23-Jun-2006 |
cognet |
Add the arm9_setup() prototype.
|
| 159868 |
22-Jun-2006 |
cognet |
arm9_setup() is now needed even if we're not using a gzipped kernel, so move
it outside the #ifdef KZIP
Pointy Hat to: cognet
|
| 159849 |
21-Jun-2006 |
imp |
Nitsville: the routine is called initarm, not init_arm, correct it in
a comment.
|
| 159758 |
18-Jun-2006 |
cognet |
Make sure the stack is properly aligned.
Enable the MMU when relocating as well, and use write-through cache.
|
| 159627 |
15-Jun-2006 |
ups |
Remove mpte optimization from pmap_enter_quick().
There is a race with the current locking scheme and removing
it should have no measurable performance impact.
This fixes page faults leading to panics in pmap_enter_quick_locked()
on amd64/i386.
Reviewed by: alc,jhb,peter,ps
|
| 159557 |
12-Jun-2006 |
cognet |
MFp4:
- Try hard to calculate a safe sp, so that the stack doesn't get smashed
while uncompressing or relocating the kernel.
- Bring in code needed to calculate the cacheline size etc, needed for
arm9_idcache_wbinv_all.
|
| 159500 |
11-Jun-2006 |
alc |
Remove pmap_pagedaemon_waken and update pmap_get_pv_entry() to match the
current interface with the machine-independent layer. Without this change,
the page daemon would only have been awakened the first time that the
number of pv entries went above the high water mark, not each time.
|
| 159499 |
11-Jun-2006 |
alc |
Eliminate spl calls.
|
| 159474 |
10-Jun-2006 |
alc |
Add a lock assertion. Remove dead (locking) code. Change some white
space.
Reviewed by: cognet@
|
| 159450 |
09-Jun-2006 |
alc |
Add pmap locking to pmap_extract().
Tested by: cognet@
|
| 159384 |
07-Jun-2006 |
alc |
Add pmap locking to pmap_fault_fixup().
Add an assertion to pmap_vac_me_harder().
Tested by: cognet@
|
| 159378 |
07-Jun-2006 |
alc |
Properly synchronize access to the pmap in pmap_extract_and_hold().
Eliminate an unneeded variable from pmap_extract_and_hold().
Tested by: cognet@
|
| 159359 |
06-Jun-2006 |
cognet |
Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, and
completely nuke the !ARM32_NEW_VM_LAYOUT case.
|
| 159352 |
06-Jun-2006 |
alc |
Add partial pmap locking.
Tested by: cognet@
|
| 159325 |
06-Jun-2006 |
alc |
Add partial pmap locking.
Eliminate the unused allpmaps list.
Tested by: cognet@
|
| 159322 |
06-Jun-2006 |
cognet |
Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add it
as an option.
Submitted by: Max N. Boyarov <m.boyarov at bsd dot by>
|
| 159321 |
05-Jun-2006 |
cognet |
vm_page_alloc_contig() can sleep, so don't even think about using it
in the M_NOWAIT case.
|
| 159303 |
05-Jun-2006 |
alc |
Introduce the function pmap_enter_object(). It maps a sequence of resident
pages from the same object. Use it in vm_map_pmap_enter() to reduce the
locking overhead of premapping objects.
Reviewed by: tegge@
|
| 159127 |
01-Jun-2006 |
alc |
Introduce pmap_enter_locked() and use it to reimplement pmap_enter_quick().
Tested by: cognet@
|
| 159108 |
31-May-2006 |
cognet |
Avoid a LOR by unlocking the vm_page_queue_mtx before calling uma_zalloc,
and freeing the allocated memory if another thread already did the same.
|
| 159107 |
31-May-2006 |
cognet |
If our buffer is not aligned on the cache line size, write back/invalidate
the first and last cache line in PREREAD, and just invalidate the cache
lines in POSTREAD, instead of write-back/invalidating in POSTREAD, which
could lead to stale data overriding what has been transfered by DMA.
|
| 159088 |
30-May-2006 |
cognet |
Protect the mapping used for pmap_copy_page/pmap_zero_page with a
mutex.
|
| 159084 |
30-May-2006 |
cognet |
To avoid problems, invalidate the data cache and disable the MMU once
we're done uncompressing the kernel.
|
| 159073 |
30-May-2006 |
cognet |
In pmap_is_prefaultable(), assert that the pte isn't NULL if
pmap_get_pde_pte() returns TRUE.
Suggested by: ssouhlal
|
| 159068 |
30-May-2006 |
benno |
In pmap_mapdev we correctly round the address off to the nearest page
boundary, but we must also add the offset back on to the va we return.
|
| 158590 |
15-May-2006 |
benno |
Display real/avail memory as per other platforms.
Approved by: cognet
|
| 158396 |
10-May-2006 |
cognet |
Move the call to cpu_setup() before the call to vm_ksubmap_init().
vm_ksubmap_init() calls pmap_copy_page(), which uses the mini data cache
to do the copy, but we're running uncaching before cpu_setup().
For some reason it hasn't been a problem so far, but it is for the
PXA255.
Spotted out by: benno
|
| 157970 |
22-Apr-2006 |
cognet |
MFother arches :
date: 2006/04/12 04:22:50; author: alc; state: Exp; lines: +14 -41
Retire pmap_track_modified(). We no longer need it because we do not
create managed mappings within the clean submap. To prevent regressions,
add assertions blocking the creation of managed mappings within the clean
submap.
Reviewed by: tegge
|
| 157891 |
20-Apr-2006 |
imp |
When returning a resource that we've allocated with rman_reserve_resource,
go ahead and set the rid for that resource.
|
| 157618 |
09-Apr-2006 |
cognet |
MFp4: Use CPU_CONTROL_ROUNDROBIN for arm9, it seems to give marginally
better performances.
|
| 157616 |
09-Apr-2006 |
cognet |
Not only disable/enable interrupts, do it for FIQs as well, when needed.
|
| 157443 |
03-Apr-2006 |
peter |
Remove the unused sva and eva arguments from pmap_remove_pages().
|
| 157156 |
26-Mar-2006 |
cognet |
Implement pmap_object_init_pt() the way it is on sparc64/alpha, by doing
nothing except asserting the vm object is locked, and a device object,
instead of a useless printf.
|
| 157027 |
22-Mar-2006 |
cognet |
MFp4: More special casing of when vector_page == 0x00000000 :
catch attempts to write to vector_page earlier in pmap_fault_fixup(),
and deny it.
|
| 157025 |
22-Mar-2006 |
cognet |
MFp4: If we're mapping the vector page (this will happen if we didn't
relocate it), do not attempt to call pmap_vac_me_harder() on the page.
At this point m will be NULL, and we know we won't have any cache
issues with this page.
|
| 156520 |
09-Mar-2006 |
cognet |
MFp4: Forget the asm inlined version of in_cksum_hdr(). It doesn't work if
the pointer is unaligned, and it just doesn't worth it.
|
| 156199 |
02-Mar-2006 |
cognet |
Use 8 * sizeof(int) instead of hardcoding 32, for the unlikely case this
code ever get used on a plateform where sizeof(int) != 4.
Suggested by: jmg
|
| 156191 |
01-Mar-2006 |
cognet |
Try to honor BUS_DMA_COHERENT : if the flag is set, normally allocate memory
with malloc() or contigmalloc() as usual, but try to re-map the allocated
memory into a VA outside the KVA, non-cached, thus making the calls to
bus_dmamap_sync() for these buffers useless.
|
| 156175 |
01-Mar-2006 |
cognet |
Use a better panic message than lol.
|
| 156174 |
01-Mar-2006 |
cognet |
Make sure we decrement p_lock before leaving prefetch_abort_handler()
|
| 156166 |
01-Mar-2006 |
cognet |
userret() now only takes 2 parameters.
|
| 155922 |
22-Feb-2006 |
jhb |
Close some races between procfs/ptrace and exit(2):
- Reorder the events in exit(2) slightly so that we trigger the S_EXIT
stop event earlier. After we have signalled that, we set P_WEXIT and
then wait for any processes with a hold on the vmspace via PHOLD to
release it. PHOLD now KASSERT()'s that P_WEXIT is clear when it is
invoked, and PRELE now does a wakeup if P_WEXIT is set and p_lock drops
to zero.
- Change proc_rwmem() to require that the processing read from has its
vmspace held via PHOLD by the caller and get rid of all the junk to
screw around with the vmspace reference count as we no longer need it.
- In ptrace() and pseudofs(), treat a process with P_WEXIT set as if it
doesn't exist.
- Only do one PHOLD in kern_ptrace() now, and do it earlier so it covers
FIX_SSTEP() (since on alpha at least this can end up calling proc_rwmem()
to clear an earlier single-step simualted via a breakpoint). We only
do one to avoid races. Also, by making the EINVAL error for unknown
requests be part of the default: case in the switch, the various
switch cases can now just break out to return which removes a _lot_ of
duplicated PRELE and proc unlocks, etc. Also, it fixes at least one bug
where a LWP ptrace command could return EINVAL with the proc lock still
held.
- Changed the locking for ptrace_single_step(), ptrace_set_pc(), and
ptrace_clear_single_step() to always be called with the proc lock
held (it was a mixed bag previously). Alpha and arm have to drop
the lock while the mess around with breakpoints, but other archs
avoid extra lock release/acquires in ptrace(). I did have to fix a
couple of other consumers in kern_kse and a few other places to
hold the proc lock and PHOLD.
Tested by: ps (1 mostly, but some bits of 2-4 as well)
MFC after: 1 week
|
| 155455 |
08-Feb-2006 |
phk |
Simplify system time accounting for profiling.
Rename struct thread's td_sticks to td_pticks, we will need the
other name for more appropriately named use shortly. Reduce it
from uint64_t to u_int.
Clear td_pticks whenever we enter the kernel instead of recording
its value as reference for userret(). Use the absolute value of
td->pticks in userret() and eliminate third argument.
|
| 155306 |
04-Feb-2006 |
cognet |
MFi386:
revision 1.288
date: 2006/02/04 14:11:33; author: wsalamon; state: Exp; lines: +4 -1
Hook up the audit system to system call entry and exit. System calls will
now be audited.
Obtained from: TrustedBSD Project
Approved by: rwatson (mentor)
|
| 155242 |
03-Feb-2006 |
imp |
MFp4: Small cleanup of cpu messages at boot.
|
| 155241 |
03-Feb-2006 |
imp |
Merge from p4: minor formatting nits.
|
| 154928 |
27-Jan-2006 |
cognet |
Try harder not to recurse.
|
| 154561 |
20-Jan-2006 |
cognet |
Build a minimal pagetables, with only section mappings, mapped write through,
to speed up the decompression.
|
| 154074 |
06-Jan-2006 |
jhb |
Fix various places that were testing td_critnest to see if interrupts
should remain disabled during a trap or not to check
td_md.md_spinlock_count instead.
|
| 153940 |
31-Dec-2005 |
netchild |
MI changes:
- provide an interface (macros) to the page coloring part of the VM system,
this allows to try different coloring algorithms without the need to
touch every file [1]
- make the page queue tuning values readable: sysctl vm.stats.pagequeue
- autotuning of the page coloring values based upon the cache size instead
of options in the kernel config (disabling of the page coloring as a
kernel option is still possible)
MD changes:
- detection of the cache size: only IA32 and AMD64 (untested) contains
cache size detection code, every other arch just comes with a dummy
function (this results in the use of default values like it was the
case without the autotuning of the page coloring)
- print some more info on Intel CPU's (like we do on AMD and Transmeta
CPU's)
Note to AMD owners (IA32 and AMD64): please run "sysctl vm.stats.pagequeue"
and report if the cache* values are zero (= bug in the cache detection code)
or not.
Based upon work by: Chad David <davidc@acns.ab.ca> [1]
Reviewed by: alc, arch (in 2004)
Discussed with: alc, Chad David, arch (in 2004)
|
| 153741 |
26-Dec-2005 |
sobomax |
Remove kern.elf32.can_exec_dyn sysctl. Instead extend Brandinfo structure
with flags bitfield and set BI_CAN_EXEC_DYN flag for all brands that usually
allow executing elf dynamic binaries (aka shared libraries). When it is
requested to execute ET_DYN elf image check if this flag is on after we
know the elf brand allowing execution if so.
PR: kern/87615
Submitted by: Marcin Koziej <creep@desk.pl>
|
| 153666 |
22-Dec-2005 |
jhb |
Tweak how the MD code calls the fooclock() methods some. Instead of
passing a pointer to an opaque clockframe structure and requiring the
MD code to supply CLKF_FOO() macros to extract needed values out of the
opaque structure, just pass the needed values directly. In practice this
means passing the pair (usermode, pc) to hardclock() and profclock() and
passing the boolean (usermode) to hardclock_cpu() and hardclock_process().
Other details:
- Axe clockframe and CLKF_FOO() macros on all architectures. Basically,
all the archs were taking a trapframe and converting it into a clockframe
one way or another. Now they can just extract the PC and usermode values
directly out of the trapframe and pass it to fooclock().
- Renamed hardclock_process() to hardclock_cpu() as the latter is more
accurate.
- On Alpha, we now run profclock() at hz (profhz == hz) rather than at
the slower stathz.
- On Alpha, for the TurboLaser machines that don't have an 8254
timecounter, call hardclock() directly. This removes an extra
conditional check from every clock interrupt on Alpha on the BSP.
There is probably room for even further pruning here by changing Alpha
to use the simplified timecounter we use on x86 with the lapic timer
since we don't get interrupts from the 8254 on Alpha anyway.
- On x86, clkintr() shouldn't ever be called now unless using_lapic_timer
is false, so add a KASSERT() to that affect and remove a condition
to slightly optimize the non-lapic case.
- Change prototypeof arm_handler_execute() so that it's first arg is a
trapframe pointer rather than a void pointer for clarity.
- Use KCOUNT macro in profclock() to lookup the kernel profiling bucket.
Tested on: alpha, amd64, arm, i386, ia64, sparc64
Reviewed by: bde (mostly)
|
| 153616 |
21-Dec-2005 |
cognet |
Ooops, I removed the wrong bits.
This unbreak boot from a VA which is different from the PA.
|
| 153550 |
20-Dec-2005 |
cognet |
- Disable the instruction cache very early, until it's time to enable it again.
- Revamp the code that jumps from physical to virtual address.
|
| 153549 |
20-Dec-2005 |
cognet |
Make the elf trampoline disable the MMU, and link it at physical address,
to avoid bad surprises.
|
| 153273 |
09-Dec-2005 |
cognet |
In copyout(), quad-align the source buffer, and use ldrd if possible.
|
| 153113 |
05-Dec-2005 |
cognet |
Try to use contigmalloc() even if M_NOWAIT has been specified.
|
| 153112 |
05-Dec-2005 |
cognet |
Teach the elf trampoline how to deal with gzipped kernels.
|
| 152753 |
24-Nov-2005 |
ru |
Add missing "struct" in i386/i386/machdep.c,v 1.497 by deischen@.
|
| 152743 |
24-Nov-2005 |
cognet |
Use a magic number to know we were started from the elf wrapper.
Add a dummy _start function to make the non-elf version of the wrapper work.
|
| 152723 |
23-Nov-2005 |
cognet |
MFP4: Bring in arm9 cache-related functions
Obtained from: NetBSD
|
| 152653 |
21-Nov-2005 |
cognet |
Add an alternate ID for the arm920t (the real solution is to have
per-cpu class masks, but oh well).
|
| 152630 |
20-Nov-2005 |
alc |
Eliminate pmap_init2(). It's no longer used.
|
| 152128 |
06-Nov-2005 |
cognet |
MFi386 rev 1.536 (sort of)
Move what can be moved (UMA zones creation, pv_entry_* initialization) from
pmap_init2() to pmap_init().
Create a new function, pmap_postinit(), called from cpu_startup(), to do the
L1 tables allocation.
pmap_init2() is now empty for arm as well.
|
| 151897 |
31-Oct-2005 |
rwatson |
Normalize a significant number of kernel malloc type names:
- Prefer '_' to ' ', as it results in more easily parsed results in
memory monitoring tools such as vmstat.
- Remove punctuation that is incompatible with using memory type names
as file names, such as '/' characters.
- Disambiguate some collisions by adding subsystem prefixes to some
memory types.
- Generally prefer lower case to upper case.
- If the same type is defined in multiple architecture directories,
attempt to use the same name in additional cases.
Not all instances were caught in this change, so more work is required to
finish this conversion. Similar changes are required for UMA zone names.
|
| 151658 |
25-Oct-2005 |
jhb |
Reorganize the interrupt handling code a bit to make a few things cleaner
and increase flexibility to allow various different approaches to be tried
in the future.
- Split struct ithd up into two pieces. struct intr_event holds the list
of interrupt handlers associated with interrupt sources.
struct intr_thread contains the data relative to an interrupt thread.
Currently we still provide a 1:1 relationship of events to threads
with the exception that events only have an associated thread if there
is at least one threaded interrupt handler attached to the event. This
means that on x86 we no longer have 4 bazillion interrupt threads with
no handlers. It also means that interrupt events with only INTR_FAST
handlers no longer have an associated thread either.
- Renamed struct intrhand to struct intr_handler to follow the struct
intr_foo naming convention. This did require renaming the powerpc
MD struct intr_handler to struct ppc_intr_handler.
- INTR_FAST no longer implies INTR_EXCL on all architectures except for
powerpc. This means that multiple INTR_FAST handlers can attach to the
same interrupt and that INTR_FAST and non-INTR_FAST handlers can attach
to the same interrupt. Sharing INTR_FAST handlers may not always be
desirable, but having sio(4) and uhci(4) fight over an IRQ isn't fun
either. Drivers can always still use INTR_EXCL to ask for an interrupt
exclusively. The way this sharing works is that when an interrupt
comes in, all the INTR_FAST handlers are executed first, and if any
threaded handlers exist, the interrupt thread is scheduled afterwards.
This type of layout also makes it possible to investigate using interrupt
filters ala OS X where the filter determines whether or not its companion
threaded handler should run.
- Aside from the INTR_FAST changes above, the impact on MD interrupt code
is mostly just 's/ithread/intr_event/'.
- A new MI ddb command 'show intrs' walks the list of interrupt events
dumping their state. It also has a '/v' verbose switch which dumps
info about all of the handlers attached to each event.
- We currently don't destroy an interrupt thread when the last threaded
handler is removed because it would suck for things like ppbus(8)'s
braindead behavior. The code is present, though, it is just under
#if 0 for now.
- Move the code to actually execute the threaded handlers for an interrrupt
event into a separate function so that ithread_loop() becomes more
readable. Previously this code was all in the middle of ithread_loop()
and indented halfway across the screen.
- Made struct intr_thread private to kern_intr.c and replaced td_ithd
with a thread private flag TDP_ITHREAD.
- In statclock, check curthread against idlethread directly rather than
curthread's proc against idlethread's proc. (Not really related to intr
changes)
Tested on: alpha, amd64, i386, sparc64
Tested on: arm, ia64 (older version of patch by cognet and marcel)
|
| 151596 |
23-Oct-2005 |
cognet |
Unbreak for !__XSCALE__.
|
| 151316 |
14-Oct-2005 |
davidxu |
1. Change prototype of trapsignal and sendsig to use ksiginfo_t *, most
changes in MD code are trivial, before this change, trapsignal and
sendsig use discrete parameters, now they uses member fields of
ksiginfo_t structure. For sendsig, this change allows us to pass
POSIX realtime signal value to user code.
2. Remove cpu_thread_siginfo, it is no longer needed because we now always
generate ksiginfo_t data and feed it to libpthread.
3. Add p_sigqueue to proc structure to hold shared signals which were
blocked by all threads in the proc.
4. Add td_sigqueue to thread structure to hold all signals delivered to
thread.
5. i386 and amd64 now return POSIX standard si_code, other arches will
be fixed.
6. In this sigqueue implementation, pending signal set is kept as before,
an extra siginfo list holds additional siginfo_t data for signals.
kernel code uses psignal() still behavior as before, it won't be failed
even under memory pressure, only exception is when deleting a signal,
we should call sigqueue_delete to remove signal from sigqueue but
not SIGDELSET. Current there is no kernel code will deliver a signal
with additional data, so kernel should be as stable as before,
a ksiginfo can carry more information, for example, allow signal to
be delivered but throw away siginfo data if memory is not enough.
SIGKILL and SIGSTOP have fast path in sigqueue_add, because they can
not be caught or masked.
The sigqueue() syscall allows user code to queue a signal to target
process, if resource is unavailable, EAGAIN will be returned as
specification said.
Just before thread exits, signal queue memory will be freed by
sigqueue_flush.
Current, all signals are allowed to be queued, not only realtime signals.
Earlier patch reviewed by: jhb, deischen
Tested on: i386, amd64
|
| 150996 |
06-Oct-2005 |
cognet |
Export PAGE_SIZE from genassym.c, and include assym.s in bcopy_page.S,
instead of <machine/param.h>.
|
| 150944 |
04-Oct-2005 |
cognet |
Remove a never reached RET.
|
| 150943 |
04-Oct-2005 |
cognet |
strd needs the destination to be double-word aligned, but the pointer passed
to savectx isn't always, so always use stmia, savectx isn't called enough
to need that kind of optimization.
|
| 150893 |
03-Oct-2005 |
cognet |
Bring in the good version of this file.
|
| 150871 |
03-Oct-2005 |
cognet |
Make mem.c know about the pages allocated with ARM_USE_SMALL_ALLOC.
|
| 150870 |
03-Oct-2005 |
cognet |
Export the variables needed for the copy/zero API.
|
| 150869 |
03-Oct-2005 |
cognet |
Make sure the interrupt is masked before processing it, or bad things
can happen.
|
| 150868 |
03-Oct-2005 |
cognet |
If a thread already tries to allocate a new memory range, wait for it
instead of trying to do the same.
|
| 150865 |
03-Oct-2005 |
cognet |
- Provide the kernel l1pt physical address, for userland.
- Use the new API for pmap_copy_page() and pmap_zero_page().
- Just write-back the pages in pmap_qenter(), and invalidate it in
pmap_qremove().
- Nuke the cache flushing in pmap_enter_quick(), it's not needed anymore.
|
| 150864 |
03-Oct-2005 |
cognet |
Add a new API to let platform-specific ports provide functions for big
copy/zeroing.
|
| 150863 |
03-Oct-2005 |
cognet |
Export the virtual and physical address in which the kernel was loaded,
needed for userland when reading kernel dumps.
|
| 150861 |
03-Oct-2005 |
cognet |
Import a small ELF trampoline, in which the kernel is embedded, and that
is able to load the kernel into memory, symbol table included. This is
needed to be able to access the symbol table from DDB without a boot
loader.
|
| 150860 |
03-Oct-2005 |
cognet |
*blush*
Don't try to dereference map if it's NULL.
While I'm there, increase the minimum value to write-back/invalidate the
whole dcache in bus_dmamap_sync().
|
| 150859 |
03-Oct-2005 |
cognet |
Only save the registers that are used.
|
| 150858 |
03-Oct-2005 |
cognet |
asm versions of in_cksum_hdr() and in_pseudo().
|
| 150856 |
03-Oct-2005 |
cognet |
Implement savectx().
Obtained from: NetBSD
|
| 150855 |
03-Oct-2005 |
cognet |
Kernel dump for arm, ripped from the ia64/amd64 version.
|
| 150552 |
25-Sep-2005 |
cognet |
Fix multiple abuses of __RMAN_RESOURCE_VISIBLE in the arm code.
Spotted out by: phk
|
| 149925 |
10-Sep-2005 |
marcel |
Move the prototypes of db_md_set_watchpoint(), db_md_clr_watchpoint()
and db_md_list_watchpoints() to ddb/ddb.h.
|
| 149768 |
03-Sep-2005 |
alc |
Pass a value of type vm_prot_t to pmap_enter_quick() so that it determine
whether the mapping should permit execute access.
|
| 148666 |
03-Aug-2005 |
jeff |
- Add support for saving stack traces and displaying them via printf(9)
and KTR.
Contributed by: Antoine Brodin <antoine.brodin@laposte.net>
Concept code from: Neal Fachan <neal@isilon.com>
|
| 147889 |
10-Jul-2005 |
davidxu |
Validate if the value written into {FS,GS}.base is a canonical
address, writting non-canonical address can cause kernel a panic,
by restricting base values to 0..VM_MAXUSER_ADDRESS, ensuring
only canonical values get written to the registers.
Reviewed by: peter, Josepha Koshy < joseph.koshy at gmail dot com >
Approved by: re (scottl)
|
| 147591 |
24-Jun-2005 |
cognet |
- Use a TAILQ instead of parsing the array to find a free dmamap.
- Inline busdma_alloc_dmamap, busdma_free_dmamap and bus_dmamap_sync_buf.
Approved by: re (blanket)
|
| 147544 |
23-Jun-2005 |
cognet |
Call kdb_trap() on fatal abort.
Approved by: re (blanket)
|
| 147543 |
23-Jun-2005 |
cognet |
Implement db_frame() and use it to obtain the registers value.
Approved by: re (blanket)
|
| 147542 |
23-Jun-2005 |
cognet |
Don't abuse UMA_SLAB_KMEM.
Approved by: re (blanket)
|
| 147417 |
16-Jun-2005 |
cognet |
Try harder to detect if the allocated memory for L2 PTP comes from a 1MB
section or not.
Approved by: re (blanket)
|
| 147416 |
16-Jun-2005 |
cognet |
Don't pass the kernel_pmap to pmap_fault_fixup() if the fault comes from
kernel mode, always use the curthread pmap instead. There are valid cases
were we can fault on a user address from the kernel without pcb_onfault
being set.
Approved by: re (blanket)
|
| 147249 |
10-Jun-2005 |
cognet |
Remove the last use of pmap_initialized.
|
| 147217 |
10-Jun-2005 |
alc |
Introduce a procedure, pmap_page_init(), that initializes the
vm_page's machine-dependent fields. Use this function in
vm_pageq_add_new_page() so that the vm_page's machine-dependent and
machine-independent fields are initialized at the same time.
Remove code from pmap_init() for initializing the vm_page's
machine-dependent fields.
Remove stale comments from pmap_init().
Eliminate the Boolean variable pmap_initialized from the alpha, amd64,
i386, and ia64 pmap implementations. Its use is no longer required
because of the above changes and earlier changes that result in physical
memory that is being mapped at initialization time being mapped without
pv entries.
Tested by: cognet, kensmith, marcel
|
| 147166 |
09-Jun-2005 |
cognet |
- MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32
interrupts.
- Implement teardown methods where appropriate.
|
| 147114 |
07-Jun-2005 |
cognet |
Add a new arm-specific option, ARM_USE_SMALL_ALLOC. If defined, it provides
an implementation of uma_small_alloc() which tries to preallocate memory
1MB per 1MB, and maps it into a section mapping.
|
| 146794 |
29-May-2005 |
marcel |
Create nexus in configure_first() instead of in configure(). This
makes sure that sysinit tasks that run after configure_first(),
but before configure() have a nexus to hang devices off.
|
| 146790 |
29-May-2005 |
marcel |
Call cninit_finish() and set cold to 0 in configure_final() instead
of in configure(). Call cninit_finish() before setting cold to 0.
This is how it's done for other platforms. Be alike to avoid problems.
|
| 146668 |
27-May-2005 |
cognet |
Remove pmap_deactivate(), we do not use it.
|
| 146648 |
26-May-2005 |
cognet |
Don't enable interrupts in the dispatcher, there's no need to do so.
|
| 146647 |
26-May-2005 |
cognet |
Don't call vm_page_dirty() in pmap_nuke_pv(), it's not the place to do so, and
it leads to funny things, such as pmap_remove_all() marking the page as dirty.
|
| 146619 |
25-May-2005 |
cognet |
Remove bits specific to CPUs we won't support (< armv4).
|
| 146605 |
24-May-2005 |
cognet |
MFp4: Setup arm9 to write back by default.
Obtained from: NetBSD
|
| 146604 |
24-May-2005 |
cognet |
Remove kcopy(), we don't use it.
|
| 146600 |
24-May-2005 |
cognet |
We need to decrease p->p_lock after vm_fault() has been called.
|
| 146599 |
24-May-2005 |
cognet |
Correctly setup the UND stack in cpu_set_upcall(), and the trapframe in
cpu_thread_setup(), as done in cpu_fork().
|
| 146597 |
24-May-2005 |
cognet |
- Try to avoid calling malloc() in bus_dmamap_create() and bus_dmamem_alloc()
for the dmamap by using static dmamaps.
- Don't do anything for BUS_DMASYNC_PREREAD and BUS_DMASYNC_POSTWRITE in
bus_dmamap_sync(), it's not needed anymore.
|
| 146596 |
24-May-2005 |
cognet |
Write back affected pages in pmap_qremove() as well. This removes the need
to change the DACR when switching to a kernel thread, thus making
userland thread => kernel thread => same userland thread switch cheaper by
totally avoiding data cache and TLB invalidation.
|
| 146594 |
24-May-2005 |
cognet |
Use asm versions of in_cksum() and friends.
|
| 146122 |
11-May-2005 |
cognet |
Don't forget to copy the TP when forking, or bad things will happen to the
child process if it tries to use threads.
|
| 145452 |
23-Apr-2005 |
cognet |
Don't use fusufault in casuptr(), as it assumes the current PCB will be
stored in r2, which can't be easily done with casuptr(). Introduce
casuptrfault instead.
|
| 145433 |
23-Apr-2005 |
davidxu |
Change cpu_set_kse_upcall to more generic style, so we can reuse it
in other codes. Add cpu_set_user_tls, use it to tweak user register
and setup user TLS. I ever wanted to merge it into cpu_set_kse_upcall,
but since cpu_set_kse_upcall is also used by M:N threads which may
not need this feature, so I wrote a separated cpu_set_user_tls.
|
| 145071 |
14-Apr-2005 |
cognet |
Unbreak the vector_page == 0x00000000 case. Map the vector page L1PT into the
kernel domain for each pmap, as we don't update the page table when we're
switching to a kernel thread, but we do however update the DACR.
|
| 144971 |
12-Apr-2005 |
jhb |
Use PCPU_LAZY_INC() for cnt.v_{intr,trap,syscalls} rather than atomic
operations in some places and simple non-per CPU math in others.
|
| 144967 |
12-Apr-2005 |
cognet |
We have an asm version of bcmp(), so we could use it as well.
|
| 144760 |
07-Apr-2005 |
cognet |
- Try harder to report dirty page.
- Garbage-collect pmap_update(), it became quite useless.
|
| 144637 |
04-Apr-2005 |
jhb |
Divorce critical sections from spinlocks. Critical sections as denoted by
critical_enter() and critical_exit() are now solely a mechanism for
deferring kernel preemptions. They no longer have any affect on
interrupts. This means that standalone critical sections are now very
cheap as they are simply unlocked integer increments and decrements for the
common case.
Spin mutexes now use a separate KPI implemented in MD code: spinlock_enter()
and spinlock_exit(). This KPI is responsible for providing whatever MD
guarantees are needed to ensure that a thread holding a spin lock won't
be preempted by any other code that will try to lock the same lock. For
now all archs continue to block interrupts in a "spinlock section" as they
did formerly in all critical sections. Note that I've also taken this
opportunity to push a few things into MD code rather than MI. For example,
critical_fork_exit() no longer exists. Instead, MD code ensures that new
threads have the correct state when they are created. Also, we no longer
try to fixup the idlethreads for APs in MI code. Instead, each arch sets
the initial curthread and adjusts the state of the idle thread it borrows
in order to perform the initial context switch.
This change is largely a big NOP, but the cleaner separation it provides
will allow for more efficient alternative locking schemes in other parts
of the kernel (bare critical sections rather than per-CPU spin mutexes
for per-CPU data for example).
Reviewed by: grehan, cognet, arch@, others
Tested on: i386, alpha, sparc64, powerpc, arm, possibly more
|
| 143724 |
16-Mar-2005 |
cognet |
Introduce a new function, pmap_wb_page(), which check all userland mappings for
a given page and, if the pmap is the current pmap, write back the associated
cache line.
Use pmap_wb_page in pmap_qenter() instead of inconditionally
write back/invalidating the data cache.
|
| 143682 |
16-Mar-2005 |
jmg |
MFp4: add in making fiq's work by coping to the correct page incase we have
the vectors relocated high..
|
| 143681 |
16-Mar-2005 |
jmg |
fix up white space, I had a simple comment fix, but I might as well do the
rest while I'm here...
|
| 143671 |
16-Mar-2005 |
jmg |
make bus_dmamem_alloc always allocate a new map like we are suppose to..
This was found when I tried to run the usb code on my arm board...
Approved by: cognet
|
| 143655 |
15-Mar-2005 |
jmg |
fix arm wrt to busdma...
also wrap the two macros that have bare if's w/ do {} while(0) so that
my epe driver doesn't get a warning about braces around confused else...
|
| 143294 |
08-Mar-2005 |
mux |
Fixup KTR traces.
|
| 143284 |
08-Mar-2005 |
mux |
Use __func__ in the KTR_BUSDMA traces. This avoids copy and paste
errors like in the bus_dmamap_load_mbuf_sg() case where we were wrongly
displaying the function name as bus_dmamap_load_mbuf.
|
| 143199 |
07-Mar-2005 |
mux |
Fix typo.
|
| 143193 |
06-Mar-2005 |
cognet |
Use [ldr|str]t instead of [ldr|str] when accessing ARM_TP_ADDRESS.
|
| 143192 |
06-Mar-2005 |
cognet |
Make sure ARM_TP_ADDRESS is accessible right now by calling pmap_fault_fixup,
as we can't rely on a trap happening, as it is done normally.
While I'm there, uncomment the call to cpu_dcache_wbinv_range() in
pmap_kenter_internal, as we don't call cpu_dcache_wbinv_all() there anymore.
|
| 143175 |
06-Mar-2005 |
cognet |
Unlike NetBSD's bcopy(), our bcopy allows the two strings to overlap, even in
kernel. So bring in the userland version, instead of just calling memcpy.
|
| 143116 |
03-Mar-2005 |
cognet |
Handle endianness correctly.
Spotted out by: jmg
|
| 143063 |
02-Mar-2005 |
joerg |
netchild's mega-patch to isolate compiler dependencies into a central
place.
This moves the dependency on GCC's and other compiler's features into
the central sys/cdefs.h file, while the individual source files can
then refer to #ifdef __COMPILER_FEATURE_FOO where they by now used to
refer to #if __GNUC__ > 3.1415 && __BARC__ <= 42.
By now, GCC and ICC (the Intel compiler) have been actively tested on
IA32 platforms by netchild. Extension to other compilers is supposed
to be possible, of course.
Submitted by: netchild
Reviewed by: various developers on arch@, some time ago
|
| 142955 |
01-Mar-2005 |
cognet |
In cpu_throw(), correctly calculate td->td_md.md_tp.
In cpu_switch(), set the DACR even if we're switching to a kernel thread.
|
| 142947 |
01-Mar-2005 |
cognet |
Introduce realmem.
|
| 142570 |
26-Feb-2005 |
cognet |
Instead of using sysarch() to store-retrieve the tp, add a magic address,
ARM_TP_ADDRESS, where the tp will be stored. On CPUs that support it, a cache
line will be allocated and locked for this address, so that it will never go
to RAM. On CPUs that does not, a page is allocated for it (it will be a bit
slower, and is wrong for SMP, but should be fine for UP).
The tp is still stored in the mdthread struct, and at each context switch,
ARM_TP_ADDRESS gets updated.
Suggested by: davidxu
|
| 142519 |
25-Feb-2005 |
cognet |
Implement two new sysarch for arm, ARM_GET_TP and ARM_SET_TP, to work around
the lack of tls on arm.
|
| 142518 |
25-Feb-2005 |
cognet |
Make sure casuptr() reset pcb->pcb_onfault when returning.
|
| 142145 |
20-Feb-2005 |
cognet |
MFp4: get the code that set the pc correctly to work, remove a few IQ31244
specific mappings from locore.S, re-organize iq31244_machdep.c to work with
the new locore.S
Spotted out by: jmg
|
| 142116 |
20-Feb-2005 |
cognet |
Removing the #endif as well sounds like a good idea.
|
| 142115 |
20-Feb-2005 |
cognet |
In cpufunc_control, uncomment the code responsible for returning the old
state of the control register.
|
| 142050 |
18-Feb-2005 |
cognet |
Support high vectors for arm9.
Obtained from: NetBSD
|
| 141551 |
09-Feb-2005 |
jmg |
move pmap.h after vm.h include... some of the headers from pmap.h depend
upon vm.h
|
| 141378 |
06-Feb-2005 |
njl |
Finish the job of sorting all includes and fix the build by including
malloc.h before proc.h on sparc64. Noticed by das@
Compiled on: alpha, amd64, i386, pc98, sparc64
|
| 141249 |
04-Feb-2005 |
njl |
Sort includes a little so that bus.h comes before cpu.h (for device_t).
|
| 141237 |
04-Feb-2005 |
njl |
Add an implementation of cpu_est_clockrate(9). This function estimates the
current clock frequency for the given CPU id in units of Hz.
|
| 140683 |
23-Jan-2005 |
cognet |
Make sure we can boot both with and without MMU enabled.
|
| 140682 |
23-Jan-2005 |
cognet |
Define bus_dmamap_load_buffer before bus_dmamap_load to make gcc happy.
|
| 140680 |
23-Jan-2005 |
cognet |
Fix compile for !KTR.
|
| 140478 |
19-Jan-2005 |
cognet |
Fix compile for __ARMEB__.
|
| 140462 |
19-Jan-2005 |
cognet |
MFpowerpc: Work around the problem of returning a 32 bits value from
__syscall() on a 32 bits big-endian arch.
Spotted out by: grehan
|
| 140349 |
16-Jan-2005 |
cognet |
Erm, don't forget to store the mbuf in the dmamap in bus_dmamap_load_mbuf_sg(),
so that bus_dmamap_sync() knows what to invalidate. This makes em(4) work again.
While I'm there, remove the unused "first" variable.
|
| 140313 |
15-Jan-2005 |
cognet |
Add support for KTR_BUSDMA.
|
| 140310 |
15-Jan-2005 |
cognet |
MFi386: add bus_dmamap_load_mbuf_sg().
|
| 140001 |
10-Jan-2005 |
cognet |
Add support for ptrace() and gdb breakpoints.
|
| 140000 |
10-Jan-2005 |
cognet |
Don't assume pmap_update() will cpwait for us, pmap_update will disappear soon.
|
| 139735 |
05-Jan-2005 |
imp |
Start all license statements with /*-
|
| 139241 |
23-Dec-2004 |
alc |
Modify pmap_enter_quick() so that it expects the page queues to be locked
on entry and it assumes the responsibility for releasing the page queues
lock if it must sleep.
Remove a bogus comment from pmap_enter_quick().
Using the first change, modify vm_map_pmap_enter() so that the page queues
lock is acquired and released once, rather than each time that a page
is mapped.
|
| 138897 |
15-Dec-2004 |
alc |
In the common case, pmap_enter_quick() completes without sleeping.
In such cases, the busying of the page and the unlocking of the
containing object by vm_map_pmap_enter() and vm_fault_prefault() is
unnecessary overhead. To eliminate this overhead, this change
modifies pmap_enter_quick() so that it expects the object to be locked
on entry and it assumes the responsibility for busying the page and
unlocking the object if it must sleep. Note: alpha, amd64, i386 and
ia64 are the only implementations optimized by this change; arm,
powerpc, and sparc64 still conservatively busy the page and unlock the
object within every pmap_enter_quick() call.
Additionally, this change is the first case where we synchronize
access to the page's PG_BUSY flag and busy field using the containing
object's lock rather than the global page queues lock. (Modifications
to the page's PG_BUSY flag and busy field have asserted both locks for
several weeks, enabling an incremental transition.)
|
| 138857 |
14-Dec-2004 |
cognet |
Enable interrupts once the active ones have been masked.
|
| 138856 |
14-Dec-2004 |
cognet |
Update the sp after popping the regs.
This is a good candidate for the golden pointy hat awards.
|
| 138751 |
12-Dec-2004 |
cognet |
Save a few more cycles in cpu_switch() and cpu_throw().
|
| 138710 |
11-Dec-2004 |
cognet |
Fix style.
|
| 138709 |
11-Dec-2004 |
cognet |
Add entries to trace syscalls with KTR.
|
| 138683 |
11-Dec-2004 |
cognet |
Fix compilation with INVARIANTS.
|
| 138665 |
10-Dec-2004 |
cognet |
s/RETEQ/RETeq/.
|
| 138525 |
07-Dec-2004 |
cognet |
Include <sys/signalvar.h> for trapsignal().
|
| 138415 |
05-Dec-2004 |
cognet |
Reactivate the use of the minidata cache.
|
| 138414 |
05-Dec-2004 |
cognet |
Do not change the page directory and do not flush the TLB when switching to
a kernel thread.
|
| 138328 |
02-Dec-2004 |
cognet |
Include <sys/signalvar.h> for trapsignal().
|
| 138129 |
27-Nov-2004 |
das |
Don't include sys/user.h merely for its side-effect of recursively
including other headers.
|
| 138022 |
23-Nov-2004 |
cognet |
Enable interrupts as soon as the pending interrupts have been masked.
|
| 137977 |
21-Nov-2004 |
cognet |
Cleanup.
|
| 137976 |
21-Nov-2004 |
cognet |
Set the frame pointer to 0 in fork_trampoline().
|
| 137975 |
21-Nov-2004 |
cognet |
Implement breakpoints and single stepping on arm.
Obtained from: NetBSD
|
| 137941 |
20-Nov-2004 |
cognet |
Remove useless code.
|
| 137940 |
20-Nov-2004 |
cognet |
Implement enough to be able to enter and leave DDB.
|
| 137939 |
20-Nov-2004 |
cognet |
Get the kernel stack right now that the u-area is gone.
|
| 137918 |
20-Nov-2004 |
das |
Remove some references to U area here while trying not to break
anything. Someone with ARM hardware could do a lot more to untangle
this code.
Reviewed by: arch@
|
| 137917 |
20-Nov-2004 |
das |
Remove references to U area and garbage collect includes.
Reviewed by: arch@
|
| 137903 |
20-Nov-2004 |
cognet |
Increase cnt.v_syscall and cnt.v_trap when needed.
|
| 137760 |
16-Nov-2004 |
cognet |
Simplify a bit bus_dmamap_load_buffer by removing the "first" parameter, use
nseg == -1 instead.
Obtained from: NetBSD
|
| 137758 |
15-Nov-2004 |
cognet |
MFi386:
- inlina bus_dmamap_load_buffer
- Directly pass the pmap to bus_dmamap_load_buffer, instead of the struct thread
|
| 137664 |
13-Nov-2004 |
cognet |
Don't forget to clear the PG_WRITEABLE flag when appropriate.
|
| 137663 |
13-Nov-2004 |
cognet |
Use uma_prealloc() on the l2table_zone to prevent a LOR at startup.
|
| 137629 |
12-Nov-2004 |
cognet |
Implement interrupt counting, so that vmstat -i work.
|
| 137552 |
10-Nov-2004 |
cognet |
Don't forget to include opt_vm.h.
|
| 137549 |
10-Nov-2004 |
cognet |
Invalidate the data cache in pmap_qremove() instead of in pmap_kenter(),
and in pmap_enter_quick() instead of pmap_enter().
|
| 137498 |
10-Nov-2004 |
trhodes |
Remove __P here too.
Ok'ed by: cognet
|
| 137463 |
09-Nov-2004 |
cognet |
Use the RET macro.
|
| 137372 |
08-Nov-2004 |
alc |
Introduce two new options, "CPU private" and "no wait", to sf_buf_alloc().
Change the spelling of the "catch" option to be consistent with the new
options. Implement the "no wait" option. An implementation of the "CPU
private" for i386 will be committed at a later date.
|
| 137362 |
07-Nov-2004 |
cognet |
Import md bits for mem(4) on arm.
While I'm there, cleanup a bit pmap.h.
|
| 137341 |
07-Nov-2004 |
cognet |
Remove useless code.
|
| 137275 |
05-Nov-2004 |
cognet |
Copy the syscall args in a tmp variable instead of directly using the
trapframe, as it can be modified in the syscall.
Call thread_user_enter() when appropriate.
|
| 137274 |
05-Nov-2004 |
cognet |
Save a few cycles in context switch.
Update comments to reflect reality.
|
| 137273 |
05-Nov-2004 |
cognet |
If we're still running at the physical address, jump to the virtual address
instead before calling initarm().
This removes the need to map virtual == physical in initarm().
|
| 137272 |
05-Nov-2004 |
cognet |
Be more verbose about cache capacities.
|
| 137271 |
05-Nov-2004 |
cognet |
Implement casuptr.
|
| 137270 |
05-Nov-2004 |
cognet |
Call pmap_pte_init_arm9 instead of pmap_pte_init_generic if
ARM9_CACHE_WRITE_THROUGH is defined.
|
| 137264 |
05-Nov-2004 |
cognet |
In cpu_critical_fork_exit(), make sure to set td_md.md_critnest so that
interrupts will be enabled.
Spotted out by: jhb
|
| 137215 |
04-Nov-2004 |
cognet |
Implement cpu_thread_siginfo() and set_mcontext().
Nuke getframe(), and choose which stack to use directly in sendsig().
|
| 137214 |
04-Nov-2004 |
cognet |
Implement cpu_set_upcall and cpu_set_upcall_kse.
Calculate td_frame and td_pcb the right way in cpu_thread_setup.
|
| 137211 |
04-Nov-2004 |
cognet |
Get kernel modules to work.
|
| 137117 |
01-Nov-2004 |
jhb |
- Change the ddb paging "support" to use a variable (db_lines_per_page) to
control the number of lines per page rather than a constant. The variable
can be examined and changed in ddb as '$lines'. Setting the variable to
0 will effectively turn off paging.
- Change db_putchar() to force out pending whitespace before outputting
newlines and carriage returns so that one can rub out content on the
current line via '\r \r' type strings.
- Change the simple pager to rub out the --More-- prompt explicitly when
the routine exits.
- Add some aliases to the simple pager to make it more compatible with
more(1): 'e' and 'j' do a single line. 'd' does half a page, and
'f' does a full page.
MFC after: 1 month
Inspired by: kris
|
| 136743 |
21-Oct-2004 |
cognet |
We want to ignore BUS_DMASYNC_POSTWRITE, not BUS_DMASYNC_POSTREAD.
Spotted out by: mux
Pointy hat to: cognet
|
| 135881 |
28-Sep-2004 |
cognet |
Calling fuword from fuword32 with bl and without returning after is really a bad
idea.
Any way I get a customized CVS template with "Pointy hat to: cognet"
pre-filled ?
|
| 135880 |
28-Sep-2004 |
cognet |
Always invalidate the whole data cache in pmap_enter() for now.
It should not be needed.
|
| 135879 |
28-Sep-2004 |
cognet |
Remove dead code.
|
| 135658 |
23-Sep-2004 |
cognet |
Use sf_bufs for uiomove_fromphys().
|
| 135657 |
23-Sep-2004 |
cognet |
On Xscale, use the minicache for the kernel stack.
|
| 135656 |
23-Sep-2004 |
cognet |
Make sure to call cred_update_thread() if needed.
Add partial support for KTRACE.
|
| 135655 |
23-Sep-2004 |
cognet |
Implement cpu_throw().
Obtained from: NetBSD
|
| 135654 |
23-Sep-2004 |
cognet |
Remove unused macroes.
Add user, btrap, etrap, bintr and eintrt in the GPROF case.
|
| 135653 |
23-Sep-2004 |
cognet |
Implement sigreturn().
|
| 135652 |
23-Sep-2004 |
cognet |
Add the hw.machine sysctl.
|
| 135651 |
23-Sep-2004 |
cognet |
Remove definitions related to the pmap cache state, and add TDF_NEEDRESCHED.
|
| 135650 |
23-Sep-2004 |
cognet |
Add new functions to know which irqs are pending, and to mask and unmask
interrupts, as these are CPU specific.
If the interrupt handler is not marked as INTR_FAST, don't unmask the
interrupt until it as been serviced.
|
| 135649 |
23-Sep-2004 |
cognet |
Rename macroes, as we don't need to mess with alignment faults.
Call ast() if TDF_NEEDRESCHED is set too, not just TDF_ASTPENDING.
|
| 135648 |
23-Sep-2004 |
cognet |
Use sigcode.
|
| 135647 |
23-Sep-2004 |
cognet |
In db_stack_trace_cmd, remove the "pc" variable, we don't need it.
|
| 135646 |
23-Sep-2004 |
cognet |
Use the right path for xscale files.
|
| 135645 |
23-Sep-2004 |
cognet |
Remove bus_space_vaddr(), it does not exists in FreeBSD.
|
| 135644 |
23-Sep-2004 |
cognet |
Don't attempt to manage our own segment list, and just remember the buffers
provided.
Obtained from: NetBSD
|
| 135643 |
23-Sep-2004 |
cognet |
Use the right path for the bcopyinout_xscale.S file.
|
| 135642 |
23-Sep-2004 |
cognet |
Add MD syscalls to sync the icache and to drain the write buffer.
Obtained from: NetBSD
|
| 135641 |
23-Sep-2004 |
cognet |
Implement pmap_growkernel() and pmap_extract_and_hold().
Remove the cache state logic : right now, it provides more problems than it
helps.
Add helper functions for mapping devices while bootstrapping.
Reorganize the code a bit, and remove dead code.
Obtained from: NetBSD (partially)
|
| 135640 |
23-Sep-2004 |
cognet |
Map the kernel very early if needed.
Implement sigcode.
|
| 135529 |
20-Sep-2004 |
jhb |
- Add support for "paging" in stack trace output. That is, when you do
a stack trace from ddb, the output will pause with a '--More--' prompt
every 18 lines. If you hit Enter, it will print another line and prompt
again. If you hit space it will output another page and then prompt.
If you hit 'q' or 'x' it will abort the rest of the stack trace.
- Fix the sparc64 userland stack trace to honor the total count of lines
to print. This is useful if your trace happens to walk back onto
0xdeadc0de and gets stuck in an endless loop.
MFC after: 1 month
Tested on: i386, alpha, sparc64
|
| 134934 |
08-Sep-2004 |
scottl |
Fix a problem with tag->boundary inheritence that has existed since day one
and was propagated to nearly every platform. The boundary of the child needs
to consider the boundary of the parent and pick the minimum of the two, not
the maximum. However, if either is 0 then pick the appropriate one.
This bug was exposed by a recent change to ATA, which should now be fixed by
this change. The alignment and maxsegsz tag attributes likely also need
a similar review in the near future.
This is a MT5 candidate.
Reviewed by: marcel
Submitted by: sos (in part)
|
| 133464 |
11-Aug-2004 |
marcel |
Add __elfN(dump_thread). This function is called from __elfN(coredump)
to allow dumping per-thread machine specific notes. On ia64 we use this
function to flush the dirty registers onto the backingstore before we
write out the PRSTATUS notes.
Tested on: alpha, amd64, i386, ia64 & sparc64
Not tested on: arm, powerpc
|
| 133453 |
10-Aug-2004 |
alc |
Add a comment describing pmap_extract_and_hold() noting that the protection
check still needs implementation on arm.
|
| 133237 |
06-Aug-2004 |
cognet |
Use the new prototype for the zone constructor.
|
| 133143 |
04-Aug-2004 |
alc |
- Push down the acquisition and release of Giant into pmap_enter_quick()
on those architectures without pmap locking.
- Eliminate the acquisition and release of Giant in vm_map_pmap_enter().
|
| 132899 |
30-Jul-2004 |
alc |
- Push down the acquisition and release of Giant into pmap_protect() on
those architectures without pmap locking.
- Eliminate the acquisition and release of Giant from vm_map_protect().
(Translation: mprotect(2) runs to completion without touching Giant on
alpha, amd64, i386 and ia64.)
|
| 132834 |
29-Jul-2004 |
cognet |
Don't use cast as lvalue.
|
| 132560 |
22-Jul-2004 |
alc |
MFi386 revision 1.421
- Use kmem_alloc_nofault() rather than kmem_alloc_pageable() in
pmap_mapdev(). See revision 1.140 of kern/sys_pipe.c for a detailed
rationale.
|
| 132514 |
21-Jul-2004 |
cognet |
Use the kernel pmap if no thread is provided.
|
| 132503 |
21-Jul-2004 |
cognet |
Do not use NULL as a malloc type for contigmalloc().
|
| 132482 |
21-Jul-2004 |
marcel |
Unify db_stack_trace_cmd(). All it did was look up the thread given
the thread ID and call db_trace_thread().
Since arm has all the logic in db_stack_trace_cmd(), rename the
new DB_COMMAND function to db_stack_trace to avoid conflicts on
arm.
While here, have db_stack_trace parse its own arguments so that
we can use a more natural radix for IDs. If the ID is not a thread
ID, or more precisely when no thread exists with the ID, try if
there's a process with that ID and return the first thread in it.
This makes it easier to print stack traces from the ps output.
requested by: rwatson@
tested on: amd64, i386, ia64
|
| 132474 |
20-Jul-2004 |
cognet |
Implement ptrace_set_pc().
Add a stub for ptrace_clear_single_step().
|
| 132473 |
20-Jul-2004 |
cognet |
Remove astpending, it has not been used for a long time.
|
| 132472 |
20-Jul-2004 |
cognet |
Uncomment the vector relocation code.
|
| 132471 |
20-Jul-2004 |
cognet |
Nuke disable_intr() and enable_intr(), as it already exists elsewhere.
|
| 132402 |
19-Jul-2004 |
cognet |
Make kdb_backtrace() sort of work.
|
| 132119 |
13-Jul-2004 |
cognet |
In pmap_remove_pages(), when the pv_list is entry, we want to clean the
PG_WRITEABLE flag, not the PG_REFERENCED flag.
Submitted by: alc
|
| 132082 |
13-Jul-2004 |
alc |
Push down the acquisition and release of the page queues lock into
pmap_remove_pages(). (The implementation of pmap_remove_pages() is
optional. If pmap_remove_pages() is unimplemented, the acquisition and
release of the page queues lock is unnecessary.)
Remove spl calls from the alpha, arm, and ia64 pmap_remove_pages().
|
| 132059 |
12-Jul-2004 |
cognet |
Update to kdb.
|
| 132054 |
12-Jul-2004 |
cognet |
Implement makectx().
|
| 131837 |
08-Jul-2004 |
cognet |
Define NSFBUFS and use it.
|
| 131658 |
05-Jul-2004 |
alc |
Correct pmap_extract()'s return type. It should be vm_paddr_t, not
vm_offset_t.
|
| 131496 |
02-Jul-2004 |
cognet |
ithread_schedule() now only takes one argument.
|
| 131495 |
02-Jul-2004 |
cognet |
Define __RMAN_RESOURCE_VISIBLE where appropriate.
|
| 131231 |
28-Jun-2004 |
cognet |
Remove unused includes.
Spotted out by: pjd
|
| 130745 |
19-Jun-2004 |
cognet |
Fix compilation for Xscale.
|
| 130733 |
19-Jun-2004 |
cognet |
I happened to have a sys/pool.h file in my tree, but most people do not,
so nuke this useless include.
|
| 130644 |
17-Jun-2004 |
cognet |
Nuke bus_space_mmap(), as it does not exist in FreeBSD.
|
| 130585 |
16-Jun-2004 |
phk |
Do the dreaded s/dev_t/struct cdev */
Bump __FreeBSD_version accordingly.
|
| 130164 |
06-Jun-2004 |
phk |
Remove filename+line number from panic messages.
|
| 130028 |
03-Jun-2004 |
tjr |
Remove checks for curthread == NULL - it can't happen.
|
| 130023 |
03-Jun-2004 |
tjr |
Move TDF_DEADLKTREAT into td_pflags (and rename it accordingly) to avoid
having to acquire sched_lock when manipulating it in lockmgr(), uiomove(),
and uiomove_fromphys().
Reviewed by: jhb
|
| 129750 |
26-May-2004 |
tmm |
Retire cpu_sched_exit(); it is not used any more.
|
| 129580 |
22-May-2004 |
mux |
Remove two debugging printf().
On behalf of: cognet
|
| 129282 |
16-May-2004 |
peter |
Make a small revision to the api between the elf linker core and the
elf_reloc() backends for two reasons. First, to support the possibility
of there being two elf linkers in the kernel (eg: amd64), and second, to
pass the relocbase explicitly (for relocating .o format kld files).
|
| 129254 |
14-May-2004 |
cognet |
Implement bcopy, memcpy and memcmp in support.S.
|
| 129250 |
14-May-2004 |
cognet |
Implement bzero et memset in support.S
|
| 129198 |
14-May-2004 |
cognet |
Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.
|