adapter.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/dev/cxgbe/adapter.h 330897 2018-03-14 03:19:51Z eadler $ 30 * 31 */ 32 33#ifndef __T4_ADAPTER_H__ 34#define __T4_ADAPTER_H__ 35 36#include <sys/kernel.h> 37#include <sys/bus.h> 38#include <sys/rman.h> 39#include <sys/types.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/rwlock.h> 43#include <sys/sx.h> 44#include <vm/uma.h> 45 46#include <dev/pci/pcivar.h> 47#include <dev/pci/pcireg.h> 48#include <machine/bus.h> 49#include <sys/socket.h> 50#include <sys/sysctl.h> 51#include <net/ethernet.h> 52#include <net/if.h> 53#include <net/if_var.h> 54#include <net/if_media.h> 55#include <netinet/in.h> 56#include <netinet/tcp_lro.h> 57 58#include "offload.h" 59#include "t4_ioctl.h" 60#include "common/t4_msg.h" 61#include "firmware/t4fw_interface.h" 62 63#define KTR_CXGBE KTR_SPARE3 64MALLOC_DECLARE(M_CXGBE); 65#define CXGBE_UNIMPLEMENTED(s) \ 66 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 67 68#if defined(__i386__) || defined(__amd64__) 69static __inline void 70prefetch(void *x) 71{ 72 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 73} 74#else 75#define prefetch(x) 76#endif 77 78#ifndef SYSCTL_ADD_UQUAD 79#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 80#define sysctl_handle_64 sysctl_handle_quad 81#define CTLTYPE_U64 CTLTYPE_QUAD 82#endif 83 84#if (__FreeBSD_version >= 900030) || \ 85 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 86#define SBUF_DRAIN 1 87#endif 88 89struct adapter; 90typedef struct adapter adapter_t; 91 92enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 128, 109 TX_EQ_QSIZE = 1024, 110 111#if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113#else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115#endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 122}; 123 124enum { 125 /* adapter intr_type */ 126 INTR_INTX = (1 << 0), 127 INTR_MSI = (1 << 1), 128 INTR_MSIX = (1 << 2) 129}; 130 131enum { 132 XGMAC_MTU = (1 << 0), 133 XGMAC_PROMISC = (1 << 1), 134 XGMAC_ALLMULTI = (1 << 2), 135 XGMAC_VLANEX = (1 << 3), 136 XGMAC_UCADDR = (1 << 4), 137 XGMAC_MCADDRS = (1 << 5), 138 139 XGMAC_ALL = 0xffff 140}; 141 142enum { 143 /* flags understood by begin_synchronized_op */ 144 HOLD_LOCK = (1 << 0), 145 SLEEP_OK = (1 << 1), 146 INTR_OK = (1 << 2), 147 148 /* flags understood by end_synchronized_op */ 149 LOCK_HELD = HOLD_LOCK, 150}; 151 152enum { 153 /* adapter flags */ 154 FULL_INIT_DONE = (1 << 0), 155 FW_OK = (1 << 1), 156 CHK_MBOX_ACCESS = (1 << 2), 157 MASTER_PF = (1 << 3), 158 ADAP_SYSCTL_CTX = (1 << 4), 159 /* TOM_INIT_DONE= (1 << 5), No longer used */ 160 BUF_PACKING_OK = (1 << 6), 161 IS_VF = (1 << 7), 162 163 CXGBE_BUSY = (1 << 9), 164 165 /* port flags */ 166 HAS_TRACEQ = (1 << 3), 167 168 /* VI flags */ 169 DOOMED = (1 << 0), 170 VI_INIT_DONE = (1 << 1), 171 VI_SYSCTL_CTX = (1 << 2), 172 173 /* adapter debug_flags */ 174 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 175 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 176 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 177}; 178 179#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 180#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 181#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 182#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 183#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 184 185struct vi_info { 186 device_t dev; 187 struct port_info *pi; 188 189 struct ifnet *ifp; 190 191 unsigned long flags; 192 int if_flags; 193 194 uint16_t *rss, *nm_rss; 195 int smt_idx; /* for convenience */ 196 uint16_t viid; 197 int16_t xact_addr_filt;/* index of exact MAC address filter */ 198 uint16_t rss_size; /* size of VI's RSS table slice */ 199 uint16_t rss_base; /* start of VI's RSS table slice */ 200 201 eventhandler_tag vlan_c; 202 203 int nintr; 204 int first_intr; 205 206 /* These need to be int as they are used in sysctl */ 207 int ntxq; /* # of tx queues */ 208 int first_txq; /* index of first tx queue */ 209 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 210 int nrxq; /* # of rx queues */ 211 int first_rxq; /* index of first rx queue */ 212 int nofldtxq; /* # of offload tx queues */ 213 int first_ofld_txq; /* index of first offload tx queue */ 214 int nofldrxq; /* # of offload rx queues */ 215 int first_ofld_rxq; /* index of first offload rx queue */ 216 int nnmtxq; 217 int first_nm_txq; 218 int nnmrxq; 219 int first_nm_rxq; 220 int tmr_idx; 221 int ofld_tmr_idx; 222 int pktc_idx; 223 int ofld_pktc_idx; 224 int qsize_rxq; 225 int qsize_txq; 226 227 struct timeval last_refreshed; 228 struct fw_vi_stats_vf stats; 229 230 struct callout tick; 231 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 232 233 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 234}; 235 236struct tx_ch_rl_params { 237 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 238 uint32_t maxrate; 239}; 240 241enum { 242 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */ 243 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */ 244}; 245 246struct tx_cl_rl_params { 247 int refcount; 248 u_int flags; 249 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 250 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 251 enum fw_sched_params_mode mode; /* aggr or per-flow */ 252 uint32_t maxrate; 253 uint16_t pktsize; 254}; 255 256/* Tx scheduler parameters for a channel/port */ 257struct tx_sched_params { 258 /* Channel Rate Limiter */ 259 struct tx_ch_rl_params ch_rl; 260 261 /* Class WRR */ 262 /* XXX */ 263 264 /* Class Rate Limiter */ 265 struct tx_cl_rl_params cl_rl[]; 266}; 267 268struct port_info { 269 device_t dev; 270 struct adapter *adapter; 271 272 struct vi_info *vi; 273 int nvi; 274 int up_vis; 275 int uld_vis; 276 277 struct tx_sched_params *sched_params; 278 279 struct mtx pi_lock; 280 char lockname[16]; 281 unsigned long flags; 282 283 uint8_t lport; /* associated offload logical port */ 284 int8_t mdio_addr; 285 uint8_t port_type; 286 uint8_t mod_type; 287 uint8_t port_id; 288 uint8_t tx_chan; 289 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 290 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 291 292 struct link_config link_cfg; 293 struct link_config old_link_cfg; 294 struct ifmedia media; 295 296 struct timeval last_refreshed; 297 struct port_stats stats; 298 u_int tnl_cong_drops; 299 u_int tx_parse_error; 300 301 struct callout tick; 302}; 303 304#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 305 306/* Where the cluster came from, how it has been carved up. */ 307struct cluster_layout { 308 int8_t zidx; 309 int8_t hwidx; 310 uint16_t region1; /* mbufs laid out within this region */ 311 /* region2 is the DMA region */ 312 uint16_t region3; /* cluster_metadata within this region */ 313}; 314 315struct cluster_metadata { 316 u_int refcount; 317 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 318}; 319 320struct fl_sdesc { 321 caddr_t cl; 322 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 323 struct cluster_layout cll; 324}; 325 326struct tx_desc { 327 __be64 flit[8]; 328}; 329 330struct tx_sdesc { 331 struct mbuf *m; /* m_nextpkt linked chain of frames */ 332 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 333}; 334 335 336#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 337struct iq_desc { 338 struct rss_header rss; 339 uint8_t cpl[IQ_PAD]; 340 struct rsp_ctrl rsp; 341}; 342#undef IQ_PAD 343CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 344 345enum { 346 /* iq flags */ 347 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 348 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 349 /* 1 << 2 Used to be IQ_INTR */ 350 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 351 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 352 353 /* iq state */ 354 IQS_DISABLED = 0, 355 IQS_BUSY = 1, 356 IQS_IDLE = 2, 357 358 /* netmap related flags */ 359 NM_OFF = 0, 360 NM_ON = 1, 361 NM_BUSY = 2, 362}; 363 364struct sge_iq; 365struct rss_header; 366typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 367 struct mbuf *); 368typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 369typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 370 371/* 372 * Ingress Queue: T4 is producer, driver is consumer. 373 */ 374struct sge_iq { 375 uint32_t flags; 376 volatile int state; 377 struct adapter *adapter; 378 cpl_handler_t set_tcb_rpl; 379 cpl_handler_t l2t_write_rpl; 380 struct iq_desc *desc; /* KVA of descriptor ring */ 381 int8_t intr_pktc_idx; /* packet count threshold index */ 382 uint8_t gen; /* generation bit */ 383 uint8_t intr_params; /* interrupt holdoff parameters */ 384 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 385 uint16_t qsize; /* size (# of entries) of the queue */ 386 uint16_t sidx; /* index of the entry with the status page */ 387 uint16_t cidx; /* consumer index */ 388 uint16_t cntxt_id; /* SGE context id for the iq */ 389 uint16_t abs_id; /* absolute SGE id for the iq */ 390 391 STAILQ_ENTRY(sge_iq) link; 392 393 bus_dma_tag_t desc_tag; 394 bus_dmamap_t desc_map; 395 bus_addr_t ba; /* bus address of descriptor ring */ 396}; 397 398enum { 399 EQ_CTRL = 1, 400 EQ_ETH = 2, 401 EQ_OFLD = 3, 402 403 /* eq flags */ 404 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 405 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 406 EQ_ENABLED = (1 << 3), /* open for business */ 407 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 408}; 409 410/* Listed in order of preference. Update t4_sysctls too if you change these */ 411enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 412 413/* 414 * Egress Queue: driver is producer, T4 is consumer. 415 * 416 * Note: A free list is an egress queue (driver produces the buffers and T4 417 * consumes them) but it's special enough to have its own struct (see sge_fl). 418 */ 419struct sge_eq { 420 unsigned int flags; /* MUST be first */ 421 unsigned int cntxt_id; /* SGE context id for the eq */ 422 unsigned int abs_id; /* absolute SGE id for the eq */ 423 struct mtx eq_lock; 424 425 struct tx_desc *desc; /* KVA of descriptor ring */ 426 uint16_t doorbells; 427 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 428 u_int udb_qid; /* relative qid within the doorbell page */ 429 uint16_t sidx; /* index of the entry with the status page */ 430 uint16_t cidx; /* consumer idx (desc idx) */ 431 uint16_t pidx; /* producer idx (desc idx) */ 432 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 433 uint16_t dbidx; /* pidx of the most recent doorbell */ 434 uint16_t iqid; /* iq that gets egr_update for the eq */ 435 uint8_t tx_chan; /* tx channel used by the eq */ 436 volatile u_int equiq; /* EQUIQ outstanding */ 437 438 bus_dma_tag_t desc_tag; 439 bus_dmamap_t desc_map; 440 bus_addr_t ba; /* bus address of descriptor ring */ 441 char lockname[16]; 442}; 443 444struct sw_zone_info { 445 uma_zone_t zone; /* zone that this cluster comes from */ 446 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 447 int type; /* EXT_xxx type of the cluster */ 448 int8_t head_hwidx; 449 int8_t tail_hwidx; 450}; 451 452struct hw_buf_info { 453 int8_t zidx; /* backpointer to zone; -ve means unused */ 454 int8_t next; /* next hwidx for this zone; -1 means no more */ 455 int size; 456}; 457 458enum { 459 NUM_MEMWIN = 3, 460 461 MEMWIN0_APERTURE = 2048, 462 MEMWIN0_BASE = 0x1b800, 463 464 MEMWIN1_APERTURE = 32768, 465 MEMWIN1_BASE = 0x28000, 466 467 MEMWIN2_APERTURE_T4 = 65536, 468 MEMWIN2_BASE_T4 = 0x30000, 469 470 MEMWIN2_APERTURE_T5 = 128 * 1024, 471 MEMWIN2_BASE_T5 = 0x60000, 472}; 473 474struct memwin { 475 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 476 uint32_t mw_base; /* constant after setup_memwin */ 477 uint32_t mw_aperture; /* ditto */ 478 uint32_t mw_curpos; /* protected by mw_lock */ 479}; 480 481enum { 482 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 483 FL_DOOMED = (1 << 1), /* about to be destroyed */ 484 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 485 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 486}; 487 488#define FL_RUNNING_LOW(fl) \ 489 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 490#define FL_NOT_RUNNING_LOW(fl) \ 491 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 492 493struct sge_fl { 494 struct mtx fl_lock; 495 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 496 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 497 struct cluster_layout cll_def; /* default refill zone, layout */ 498 uint16_t lowat; /* # of buffers <= this means fl needs help */ 499 int flags; 500 uint16_t buf_boundary; 501 502 /* The 16b idx all deal with hw descriptors */ 503 uint16_t dbidx; /* hw pidx after last doorbell */ 504 uint16_t sidx; /* index of status page */ 505 volatile uint16_t hw_cidx; 506 507 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 508 uint32_t cidx; /* consumer index */ 509 uint32_t pidx; /* producer index */ 510 511 uint32_t dbval; 512 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 513 volatile uint32_t *udb; 514 515 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 516 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 517 uint64_t cl_allocated; /* # of clusters allocated */ 518 uint64_t cl_recycled; /* # of clusters recycled */ 519 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 520 521 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 522 struct mbuf *m0; 523 struct mbuf **pnext; 524 u_int remaining; 525 526 uint16_t qsize; /* # of hw descriptors (status page included) */ 527 uint16_t cntxt_id; /* SGE context id for the freelist */ 528 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 529 bus_dma_tag_t desc_tag; 530 bus_dmamap_t desc_map; 531 char lockname[16]; 532 bus_addr_t ba; /* bus address of descriptor ring */ 533 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 534}; 535 536struct mp_ring; 537 538/* txq: SGE egress queue + what's needed for Ethernet NIC */ 539struct sge_txq { 540 struct sge_eq eq; /* MUST be first */ 541 542 struct ifnet *ifp; /* the interface this txq belongs to */ 543 struct mp_ring *r; /* tx software ring */ 544 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 545 struct sglist *gl; 546 __be32 cpl_ctrl0; /* for convenience */ 547 int tc_idx; /* traffic class */ 548 549 struct task tx_reclaim_task; 550 /* stats for common events first */ 551 552 uint64_t txcsum; /* # of times hardware assisted with checksum */ 553 uint64_t tso_wrs; /* # of TSO work requests */ 554 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 555 uint64_t imm_wrs; /* # of work requests with immediate data */ 556 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 557 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 558 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 559 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 560 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 561 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 562 563 /* stats for not-that-common events */ 564} __aligned(CACHE_LINE_SIZE); 565 566/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 567struct sge_rxq { 568 struct sge_iq iq; /* MUST be first */ 569 struct sge_fl fl; /* MUST follow iq */ 570 571 struct ifnet *ifp; /* the interface this rxq belongs to */ 572#if defined(INET) || defined(INET6) 573 struct lro_ctrl lro; /* LRO state */ 574#endif 575 576 /* stats for common events first */ 577 578 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 579 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 580 581 /* stats for not-that-common events */ 582 583} __aligned(CACHE_LINE_SIZE); 584 585static inline struct sge_rxq * 586iq_to_rxq(struct sge_iq *iq) 587{ 588 589 return (__containerof(iq, struct sge_rxq, iq)); 590} 591 592 593/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 594struct sge_ofld_rxq { 595 struct sge_iq iq; /* MUST be first */ 596 struct sge_fl fl; /* MUST follow iq */ 597} __aligned(CACHE_LINE_SIZE); 598 599static inline struct sge_ofld_rxq * 600iq_to_ofld_rxq(struct sge_iq *iq) 601{ 602 603 return (__containerof(iq, struct sge_ofld_rxq, iq)); 604} 605 606struct wrqe { 607 STAILQ_ENTRY(wrqe) link; 608 struct sge_wrq *wrq; 609 int wr_len; 610 char wr[] __aligned(16); 611}; 612 613struct wrq_cookie { 614 TAILQ_ENTRY(wrq_cookie) link; 615 int ndesc; 616 int pidx; 617}; 618 619/* 620 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 621 * and offload tx queues are of this type. 622 */ 623struct sge_wrq { 624 struct sge_eq eq; /* MUST be first */ 625 626 struct adapter *adapter; 627 struct task wrq_tx_task; 628 629 /* Tx desc reserved but WR not "committed" yet. */ 630 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 631 632 /* List of WRs ready to go out as soon as descriptors are available. */ 633 STAILQ_HEAD(, wrqe) wr_list; 634 u_int nwr_pending; 635 u_int ndesc_needed; 636 637 /* stats for common events first */ 638 639 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 640 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 641 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 642 643 /* stats for not-that-common events */ 644 645 /* 646 * Scratch space for work requests that wrap around after reaching the 647 * status page, and some information about the last WR that used it. 648 */ 649 uint16_t ss_pidx; 650 uint16_t ss_len; 651 uint8_t ss[SGE_MAX_WR_LEN]; 652 653} __aligned(CACHE_LINE_SIZE); 654 655 656struct sge_nm_rxq { 657 struct vi_info *vi; 658 659 struct iq_desc *iq_desc; 660 uint16_t iq_abs_id; 661 uint16_t iq_cntxt_id; 662 uint16_t iq_cidx; 663 uint16_t iq_sidx; 664 uint8_t iq_gen; 665 666 __be64 *fl_desc; 667 uint16_t fl_cntxt_id; 668 uint32_t fl_cidx; 669 uint32_t fl_pidx; 670 uint32_t fl_sidx; 671 uint32_t fl_db_val; 672 u_int fl_hwidx:4; 673 674 u_int nid; /* netmap ring # for this queue */ 675 676 /* infrequently used items after this */ 677 678 bus_dma_tag_t iq_desc_tag; 679 bus_dmamap_t iq_desc_map; 680 bus_addr_t iq_ba; 681 int intr_idx; 682 683 bus_dma_tag_t fl_desc_tag; 684 bus_dmamap_t fl_desc_map; 685 bus_addr_t fl_ba; 686} __aligned(CACHE_LINE_SIZE); 687 688struct sge_nm_txq { 689 struct tx_desc *desc; 690 uint16_t cidx; 691 uint16_t pidx; 692 uint16_t sidx; 693 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 694 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 695 uint16_t dbidx; /* pidx of the most recent doorbell */ 696 uint16_t doorbells; 697 volatile uint32_t *udb; 698 u_int udb_qid; 699 u_int cntxt_id; 700 __be32 cpl_ctrl0; /* for convenience */ 701 u_int nid; /* netmap ring # for this queue */ 702 703 /* infrequently used items after this */ 704 705 bus_dma_tag_t desc_tag; 706 bus_dmamap_t desc_map; 707 bus_addr_t ba; 708 int iqidx; 709} __aligned(CACHE_LINE_SIZE); 710 711struct sge { 712 int nrxq; /* total # of Ethernet rx queues */ 713 int ntxq; /* total # of Ethernet tx queues */ 714 int nofldrxq; /* total # of TOE rx queues */ 715 int nofldtxq; /* total # of TOE tx queues */ 716 int nnmrxq; /* total # of netmap rx queues */ 717 int nnmtxq; /* total # of netmap tx queues */ 718 int niq; /* total # of ingress queues */ 719 int neq; /* total # of egress queues */ 720 721 struct sge_iq fwq; /* Firmware event queue */ 722 struct sge_wrq mgmtq; /* Management queue (control queue) */ 723 struct sge_wrq *ctrlq; /* Control queues */ 724 struct sge_txq *txq; /* NIC tx queues */ 725 struct sge_rxq *rxq; /* NIC rx queues */ 726 struct sge_wrq *ofld_txq; /* TOE tx queues */ 727 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 728 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 729 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 730 731 uint16_t iq_start; /* first cntxt_id */ 732 uint16_t iq_base; /* first abs_id */ 733 int eq_start; /* first cntxt_id */ 734 int eq_base; /* first abs_id */ 735 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 736 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 737 738 int8_t safe_hwidx1; /* may not have room for metadata */ 739 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 740 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 741 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 742}; 743 744struct devnames { 745 const char *nexus_name; 746 const char *ifnet_name; 747 const char *vi_ifnet_name; 748 const char *pf03_drv_name; 749 const char *vf_nexus_name; 750 const char *vf_ifnet_name; 751}; 752 753struct adapter { 754 SLIST_ENTRY(adapter) link; 755 device_t dev; 756 struct cdev *cdev; 757 const struct devnames *names; 758 759 /* PCIe register resources */ 760 int regs_rid; 761 struct resource *regs_res; 762 int msix_rid; 763 struct resource *msix_res; 764 bus_space_handle_t bh; 765 bus_space_tag_t bt; 766 bus_size_t mmio_len; 767 int udbs_rid; 768 struct resource *udbs_res; 769 volatile uint8_t *udbs_base; 770 771 unsigned int pf; 772 unsigned int mbox; 773 unsigned int vpd_busy; 774 unsigned int vpd_flag; 775 776 /* Interrupt information */ 777 int intr_type; 778 int intr_count; 779 struct irq { 780 struct resource *res; 781 int rid; 782 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 783 void *tag; 784 struct sge_rxq *rxq; 785 struct sge_nm_rxq *nm_rxq; 786 } __aligned(CACHE_LINE_SIZE) *irq; 787 int sge_gts_reg; 788 int sge_kdoorbell_reg; 789 790 bus_dma_tag_t dmat; /* Parent DMA tag */ 791 792 struct sge sge; 793 int lro_timeout; 794 int sc_do_rxcopy; 795 796 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 797 struct port_info *port[MAX_NPORTS]; 798 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 799 800 void *tom_softc; /* (struct tom_data *) */ 801 struct tom_tunables tt; 802 void *iwarp_softc; /* (struct c4iw_dev *) */ 803 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 804 struct l2t_data *l2t; /* L2 table */ 805 struct tid_info tids; 806 807 uint16_t doorbells; 808 int offload_map; /* ports with IFCAP_TOE enabled */ 809 int active_ulds; /* ULDs activated on this adapter */ 810 int flags; 811 int debug_flags; 812 813 char ifp_lockname[16]; 814 struct mtx ifp_lock; 815 struct ifnet *ifp; /* tracer ifp */ 816 struct ifmedia media; 817 int traceq; /* iq used by all tracers, -1 if none */ 818 int tracer_valid; /* bitmap of valid tracers */ 819 int tracer_enabled; /* bitmap of enabled tracers */ 820 821 char fw_version[16]; 822 char tp_version[16]; 823 char er_version[16]; 824 char bs_version[16]; 825 char cfg_file[32]; 826 u_int cfcsum; 827 struct adapter_params params; 828 const struct chip_params *chip_params; 829 struct t4_virt_res vres; 830 831 uint16_t nbmcaps; 832 uint16_t linkcaps; 833 uint16_t switchcaps; 834 uint16_t niccaps; 835 uint16_t toecaps; 836 uint16_t rdmacaps; 837 uint16_t cryptocaps; 838 uint16_t iscsicaps; 839 uint16_t fcoecaps; 840 841 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 842 843 struct mtx sc_lock; 844 char lockname[16]; 845 846 /* Starving free lists */ 847 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 848 TAILQ_HEAD(, sge_fl) sfl; 849 struct callout sfl_callout; 850 851 struct mtx reg_lock; /* for indirect register access */ 852 853 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 854 855 struct mtx tc_lock; 856 struct task tc_task; 857 858 const char *last_op; 859 const void *last_op_thr; 860 int last_op_flags; 861}; 862 863#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 864#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 865#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 866#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 867 868#define ASSERT_SYNCHRONIZED_OP(sc) \ 869 KASSERT(IS_BUSY(sc) && \ 870 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 871 ("%s: operation not synchronized.", __func__)) 872 873#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 874#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 875#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 876#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 877 878#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 879#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 880#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 881#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 882#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 883 884#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 885#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 886#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 887#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 888 889#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 890#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 891#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 892#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 893#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 894 895#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 896#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 897#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 898#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 899#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 900 901#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 902 do { \ 903 if (sc->debug_flags & DF_DUMP_MBOX) { \ 904 log(LOG_NOTICE, \ 905 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 906 "%016llx %016llx %016llx %016llx\n", \ 907 device_get_nameunit(sc->dev), mbox, \ 908 (unsigned long long)t4_read_reg64(sc, data_reg), \ 909 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 910 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 911 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 912 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 913 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 914 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 915 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 916 } \ 917 } while (0) 918 919#define for_each_txq(vi, iter, q) \ 920 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 921 iter < vi->ntxq; ++iter, ++q) 922#define for_each_rxq(vi, iter, q) \ 923 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 924 iter < vi->nrxq; ++iter, ++q) 925#define for_each_ofld_txq(vi, iter, q) \ 926 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 927 iter < vi->nofldtxq; ++iter, ++q) 928#define for_each_ofld_rxq(vi, iter, q) \ 929 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 930 iter < vi->nofldrxq; ++iter, ++q) 931#define for_each_nm_txq(vi, iter, q) \ 932 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 933 iter < vi->nnmtxq; ++iter, ++q) 934#define for_each_nm_rxq(vi, iter, q) \ 935 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 936 iter < vi->nnmrxq; ++iter, ++q) 937#define for_each_vi(_pi, _iter, _vi) \ 938 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 939 ++(_iter), ++(_vi)) 940 941#define IDXINCR(idx, incr, wrap) do { \ 942 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 943} while (0) 944#define IDXDIFF(head, tail, wrap) \ 945 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 946 947/* One for errors, one for firmware events */ 948#define T4_EXTRA_INTR 2 949 950/* One for firmware events */ 951#define T4VF_EXTRA_INTR 1 952 953static inline int 954forwarding_intr_to_fwq(struct adapter *sc) 955{ 956 957 return (sc->intr_count == 1); 958} 959 960static inline uint32_t 961t4_read_reg(struct adapter *sc, uint32_t reg) 962{ 963 964 return bus_space_read_4(sc->bt, sc->bh, reg); 965} 966 967static inline void 968t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 969{ 970 971 bus_space_write_4(sc->bt, sc->bh, reg, val); 972} 973 974static inline uint64_t 975t4_read_reg64(struct adapter *sc, uint32_t reg) 976{ 977 978#ifdef __LP64__ 979 return bus_space_read_8(sc->bt, sc->bh, reg); 980#else 981 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 982 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 983 984#endif 985} 986 987static inline void 988t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 989{ 990 991#ifdef __LP64__ 992 bus_space_write_8(sc->bt, sc->bh, reg, val); 993#else 994 bus_space_write_4(sc->bt, sc->bh, reg, val); 995 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 996#endif 997} 998 999static inline void 1000t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1001{ 1002 1003 *val = pci_read_config(sc->dev, reg, 1); 1004} 1005 1006static inline void 1007t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1008{ 1009 1010 pci_write_config(sc->dev, reg, val, 1); 1011} 1012 1013static inline void 1014t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1015{ 1016 1017 *val = pci_read_config(sc->dev, reg, 2); 1018} 1019 1020static inline void 1021t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1022{ 1023 1024 pci_write_config(sc->dev, reg, val, 2); 1025} 1026 1027static inline void 1028t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1029{ 1030 1031 *val = pci_read_config(sc->dev, reg, 4); 1032} 1033 1034static inline void 1035t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1036{ 1037 1038 pci_write_config(sc->dev, reg, val, 4); 1039} 1040 1041static inline struct port_info * 1042adap2pinfo(struct adapter *sc, int idx) 1043{ 1044 1045 return (sc->port[idx]); 1046} 1047 1048static inline void 1049t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1050{ 1051 1052 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1053} 1054 1055static inline bool 1056is_10G_port(const struct port_info *pi) 1057{ 1058 1059 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1060} 1061 1062static inline bool 1063is_25G_port(const struct port_info *pi) 1064{ 1065 1066 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1067} 1068 1069static inline bool 1070is_40G_port(const struct port_info *pi) 1071{ 1072 1073 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1074} 1075 1076static inline bool 1077is_100G_port(const struct port_info *pi) 1078{ 1079 1080 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1081} 1082 1083static inline int 1084port_top_speed(const struct port_info *pi) 1085{ 1086 1087 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1088 return (100); 1089 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1090 return (40); 1091 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1092 return (25); 1093 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1094 return (10); 1095 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1096 return (1); 1097 1098 return (0); 1099} 1100 1101static inline int 1102tx_resume_threshold(struct sge_eq *eq) 1103{ 1104 1105 /* not quite the same as qsize / 4, but this will do. */ 1106 return (eq->sidx / 4); 1107} 1108 1109static inline int 1110t4_use_ldst(struct adapter *sc) 1111{ 1112 1113#ifdef notyet 1114 return (sc->flags & FW_OK || !sc->use_bd); 1115#else 1116 return (0); 1117#endif 1118} 1119 1120/* t4_main.c */ 1121extern int t4_ntxq; 1122extern int t4_nrxq; 1123extern int t4_intr_types; 1124extern int t4_tmr_idx; 1125extern int t4_pktc_idx; 1126extern unsigned int t4_qsize_rxq; 1127extern unsigned int t4_qsize_txq; 1128extern device_method_t cxgbe_methods[]; 1129 1130int t4_os_find_pci_capability(struct adapter *, int); 1131int t4_os_pci_save_state(struct adapter *); 1132int t4_os_pci_restore_state(struct adapter *); 1133void t4_os_portmod_changed(struct port_info *); 1134void t4_os_link_changed(struct port_info *); 1135void t4_iterate(void (*)(struct adapter *, void *), void *); 1136void t4_init_devnames(struct adapter *); 1137void t4_add_adapter(struct adapter *); 1138int t4_detach_common(device_t); 1139int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1140int t4_map_bars_0_and_4(struct adapter *); 1141int t4_map_bar_2(struct adapter *); 1142int t4_setup_intr_handlers(struct adapter *); 1143void t4_sysctls(struct adapter *); 1144int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1145void doom_vi(struct adapter *, struct vi_info *); 1146void end_synchronized_op(struct adapter *, int); 1147int update_mac_settings(struct ifnet *, int); 1148int adapter_full_init(struct adapter *); 1149int adapter_full_uninit(struct adapter *); 1150uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1151int vi_full_init(struct vi_info *); 1152int vi_full_uninit(struct vi_info *); 1153void vi_sysctls(struct vi_info *); 1154void vi_tick(void *); 1155 1156#ifdef DEV_NETMAP 1157/* t4_netmap.c */ 1158void cxgbe_nm_attach(struct vi_info *); 1159void cxgbe_nm_detach(struct vi_info *); 1160void t4_nm_intr(void *); 1161#endif 1162 1163/* t4_sge.c */ 1164void t4_sge_modload(void); 1165void t4_sge_modunload(void); 1166uint64_t t4_sge_extfree_refs(void); 1167void t4_tweak_chip_settings(struct adapter *); 1168int t4_read_chip_settings(struct adapter *); 1169int t4_create_dma_tag(struct adapter *); 1170void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1171 struct sysctl_oid_list *); 1172int t4_destroy_dma_tag(struct adapter *); 1173int t4_setup_adapter_queues(struct adapter *); 1174int t4_teardown_adapter_queues(struct adapter *); 1175int t4_setup_vi_queues(struct vi_info *); 1176int t4_teardown_vi_queues(struct vi_info *); 1177void t4_intr_all(void *); 1178void t4_intr(void *); 1179void t4_vi_intr(void *); 1180void t4_intr_err(void *); 1181void t4_intr_evt(void *); 1182void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1183void t4_update_fl_bufsize(struct ifnet *); 1184int parse_pkt(struct adapter *, struct mbuf **); 1185void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1186void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1187int tnl_cong(struct port_info *, int); 1188int t4_register_an_handler(an_handler_t); 1189int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1190int t4_register_cpl_handler(int, cpl_handler_t); 1191 1192/* t4_tracer.c */ 1193struct t4_tracer; 1194void t4_tracer_modload(void); 1195void t4_tracer_modunload(void); 1196void t4_tracer_port_detach(struct adapter *); 1197int t4_get_tracer(struct adapter *, struct t4_tracer *); 1198int t4_set_tracer(struct adapter *, struct t4_tracer *); 1199int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1200int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1201 1202/* t4_sched.c */ 1203int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1204int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1205int t4_init_tx_sched(struct adapter *); 1206int t4_free_tx_sched(struct adapter *); 1207void t4_update_tx_sched(struct adapter *); 1208int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1209void t4_release_cl_rl_kbps(struct adapter *, int, int); 1210 1211static inline struct wrqe * 1212alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1213{ 1214 int len = offsetof(struct wrqe, wr) + wr_len; 1215 struct wrqe *wr; 1216 1217 wr = malloc(len, M_CXGBE, M_NOWAIT); 1218 if (__predict_false(wr == NULL)) 1219 return (NULL); 1220 wr->wr_len = wr_len; 1221 wr->wrq = wrq; 1222 return (wr); 1223} 1224 1225static inline void * 1226wrtod(struct wrqe *wr) 1227{ 1228 return (&wr->wr[0]); 1229} 1230 1231static inline void 1232free_wrqe(struct wrqe *wr) 1233{ 1234 free(wr, M_CXGBE); 1235} 1236 1237static inline void 1238t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1239{ 1240 struct sge_wrq *wrq = wr->wrq; 1241 1242 TXQ_LOCK(wrq); 1243 t4_wrq_tx_locked(sc, wrq, wr); 1244 TXQ_UNLOCK(wrq); 1245} 1246 1247#endif 1248