if_txpreg.h revision 330897
1/* $OpenBSD: if_txpreg.h,v 1.34 2001/11/05 17:25:58 art Exp $ */ 2/* $FreeBSD: stable/11/sys/dev/txp/if_txpreg.h 330897 2018-03-14 03:19:51Z eadler $ */ 3 4/*- 5 * SPDX-License-Identifier: BSD-4-Clause 6 * 7 * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Aaron Campbell. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 33 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37/* 38 * Typhoon registers. 39 */ 40#define TXP_SRR 0x00 /* soft reset register */ 41#define TXP_ISR 0x04 /* interrupt status register */ 42#define TXP_IER 0x08 /* interrupt enable register */ 43#define TXP_IMR 0x0c /* interrupt mask register */ 44#define TXP_SIR 0x10 /* self interrupt register */ 45#define TXP_H2A_7 0x14 /* host->arm comm 7 */ 46#define TXP_H2A_6 0x18 /* host->arm comm 6 */ 47#define TXP_H2A_5 0x1c /* host->arm comm 5 */ 48#define TXP_H2A_4 0x20 /* host->arm comm 4 */ 49#define TXP_H2A_3 0x24 /* host->arm comm 3 */ 50#define TXP_H2A_2 0x28 /* host->arm comm 2 */ 51#define TXP_H2A_1 0x2c /* host->arm comm 1 */ 52#define TXP_H2A_0 0x30 /* host->arm comm 0 */ 53#define TXP_A2H_3 0x34 /* arm->host comm 3 */ 54#define TXP_A2H_2 0x38 /* arm->host comm 2 */ 55#define TXP_A2H_1 0x3c /* arm->host comm 1 */ 56#define TXP_A2H_0 0x40 /* arm->host comm 0 */ 57 58/* 59 * interrupt bits (IMR, ISR, IER) 60 */ 61#define TXP_INT_RESERVED 0xffff0000 62#define TXP_INT_A2H_7 0x00008000 /* arm->host comm 7 */ 63#define TXP_INT_A2H_6 0x00004000 /* arm->host comm 6 */ 64#define TXP_INT_A2H_5 0x00002000 /* arm->host comm 5 */ 65#define TXP_INT_A2H_4 0x00001000 /* arm->host comm 4 */ 66#define TXP_INT_SELF 0x00000800 /* self interrupt */ 67#define TXP_INT_PCI_TABORT 0x00000400 /* pci target abort */ 68#define TXP_INT_PCI_MABORT 0x00000200 /* pci master abort */ 69#define TXP_INT_DMA3 0x00000100 /* dma3 done */ 70#define TXP_INT_DMA2 0x00000080 /* dma2 done */ 71#define TXP_INT_DMA1 0x00000040 /* dma1 done */ 72#define TXP_INT_DMA0 0x00000020 /* dma0 done */ 73#define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */ 74#define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */ 75#define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */ 76#define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */ 77#define TXP_INT_LATCH 0x00000001 /* interrupt latch */ 78 79/* 80 * Controller periodically generates TXP_INT_A2H_3 interrupt so 81 * we don't want to see them in interrupt handler. 82 */ 83#define TXP_INTRS 0xFFFFFFEF 84#define TXP_INTR_ALL 0xFFFFFFFF 85#define TXP_INTR_NONE 0x00000000 86 87/* 88 * soft reset register (SRR) 89 */ 90#define TXP_SRR_ALL 0x0000007f /* full reset */ 91 92/* 93 * Typhoon boot commands. 94 */ 95#define TXP_BOOTCMD_NULL 0x00 96#define TXP_BOOTCMD_WAKEUP 0xfa 97#define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb 98#define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc 99#define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd 100#define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff 101 102/* 103 * Typhoon runtime commands. 104 */ 105#define TXP_CMD_GLOBAL_RESET 0x00 106#define TXP_CMD_TX_ENABLE 0x01 107#define TXP_CMD_TX_DISABLE 0x02 108#define TXP_CMD_RX_ENABLE 0x03 109#define TXP_CMD_RX_DISABLE 0x04 110#define TXP_CMD_RX_FILTER_WRITE 0x05 111#define TXP_CMD_RX_FILTER_READ 0x06 112#define TXP_CMD_READ_STATISTICS 0x07 113#define TXP_CMD_CYCLE_STATISTICS 0x08 114#define TXP_CMD_CLEAR_STATISTICS 0x09 115#define TXP_CMD_MEMORY_READ 0x0a 116#define TXP_CMD_MEMORY_WRITE_SINGLE 0x0b 117#define TXP_CMD_VARIABLE_SECTION_READ 0x0c 118#define TXP_CMD_VARIABLE_SECTION_WRITE 0x0d 119#define TXP_CMD_STATIC_SECTION_READ 0x0e 120#define TXP_CMD_STATIC_SECTION_WRITE 0x0f 121#define TXP_CMD_IMAGE_SECTION_PROGRAM 0x10 122#define TXP_CMD_NVRAM_PAGE_READ 0x11 123#define TXP_CMD_NVRAM_PAGE_WRITE 0x12 124#define TXP_CMD_XCVR_SELECT 0x13 125#define TXP_CMD_TEST_MUX 0x14 126#define TXP_CMD_PHYLOOPBACK_ENABLE 0x15 127#define TXP_CMD_PHYLOOPBACK_DISABLE 0x16 128#define TXP_CMD_MAC_CONTROL_READ 0x17 129#define TXP_CMD_MAC_CONTROL_WRITE 0x18 130#define TXP_CMD_MAX_PKT_SIZE_READ 0x19 131#define TXP_CMD_MAX_PKT_SIZE_WRITE 0x1a 132#define TXP_CMD_MEDIA_STATUS_READ 0x1b 133#define TXP_CMD_MEDIA_STATUS_WRITE 0x1c 134#define TXP_CMD_NETWORK_DIAGS_READ 0x1d 135#define TXP_CMD_NETWORK_DIAGS_WRITE 0x1e 136#define TXP_CMD_PHY_MGMT_READ 0x1f 137#define TXP_CMD_PHY_MGMT_WRITE 0x20 138#define TXP_CMD_VARIABLE_PARAMETER_READ 0x21 139#define TXP_CMD_VARIABLE_PARAMETER_WRITE 0x22 140#define TXP_CMD_GOTO_SLEEP 0x23 141#define TXP_CMD_FIREWALL_CONTROL 0x24 142#define TXP_CMD_MCAST_HASH_MASK_WRITE 0x25 143#define TXP_CMD_STATION_ADDRESS_WRITE 0x26 144#define TXP_CMD_STATION_ADDRESS_READ 0x27 145#define TXP_CMD_STATION_MASK_WRITE 0x28 146#define TXP_CMD_STATION_MASK_READ 0x29 147#define TXP_CMD_VLAN_ETHER_TYPE_READ 0x2a 148#define TXP_CMD_VLAN_ETHER_TYPE_WRITE 0x2b 149#define TXP_CMD_VLAN_MASK_READ 0x2c 150#define TXP_CMD_VLAN_MASK_WRITE 0x2d 151#define TXP_CMD_BCAST_THROTTLE_WRITE 0x2e 152#define TXP_CMD_BCAST_THROTTLE_READ 0x2f 153#define TXP_CMD_DHCP_PREVENT_WRITE 0x30 154#define TXP_CMD_DHCP_PREVENT_READ 0x31 155#define TXP_CMD_RECV_BUFFER_CONTROL 0x32 156#define TXP_CMD_SOFTWARE_RESET 0x33 157#define TXP_CMD_CREATE_SA 0x34 158#define TXP_CMD_DELETE_SA 0x35 159#define TXP_CMD_ENABLE_RX_IP_OPTION 0x36 160#define TXP_CMD_RANDOM_NUMBER_CONTROL 0x37 161#define TXP_CMD_RANDOM_NUMBER_READ 0x38 162#define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39 163#define TXP_CMD_MATRIX_DETAIL_READ 0x3a 164#define TXP_CMD_FILTER_ARRAY_READ 0x3b 165#define TXP_CMD_FILTER_DETAIL_READ 0x3c 166#define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d 167#define TXP_CMD_FILTER_TCL_WRITE 0x3e 168#define TXP_CMD_FILTER_TBL_READ 0x3f 169#define TXP_CMD_VERSIONS_READ 0x43 170#define TXP_CMD_FILTER_DEFINE 0x45 171#define TXP_CMD_ADD_WAKEUP_PKT 0x46 172#define TXP_CMD_ADD_SLEEP_PKT 0x47 173#define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48 174#define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49 175#define TXP_CMD_GET_IP_ADDRESS 0x4a 176#define TXP_CMD_READ_PCI_REG 0x4c 177#define TXP_CMD_WRITE_PCI_REG 0x4d 178#define TXP_CMD_OFFLOAD_READ 0x4e 179#define TXP_CMD_OFFLOAD_WRITE 0x4f 180#define TXP_CMD_HELLO_RESPONSE 0x57 181#define TXP_CMD_ENABLE_RX_FILTER 0x58 182#define TXP_CMD_RX_FILTER_CAPABILITY 0x59 183#define TXP_CMD_HALT 0x5d 184#define TXP_CMD_READ_IPSEC_INFO 0x54 185#define TXP_CMD_GET_IPSEC_ENABLE 0x67 186#define TXP_CMD_INVALID 0xffff 187 188#define TXP_FRAGMENT 0x0000 189#define TXP_TXFRAME 0x0001 190#define TXP_COMMAND 0x0002 191#define TXP_OPTION 0x0003 192#define TXP_RECEIVE 0x0004 193#define TXP_RESPONSE 0x0005 194 195#define TXP_TYPE_IPSEC 0x0000 196#define TXP_TYPE_TCPSEGMENT 0x0001 197 198#define TXP_PFLAG_NOCRC 0x0000 199#define TXP_PFLAG_IPCKSUM 0x0001 200#define TXP_PFLAG_TCPCKSUM 0x0002 201#define TXP_PFLAG_TCPSEGMENT 0x0004 202#define TXP_PFLAG_INSERTVLAN 0x0008 203#define TXP_PFLAG_IPSEC 0x0010 204#define TXP_PFLAG_PRIORITY 0x0020 205#define TXP_PFLAG_UDPCKSUM 0x0040 206#define TXP_PFLAG_PADFRAME 0x0080 207 208#define TXP_MISC_FIRSTDESC 0x0000 209#define TXP_MISC_LASTDESC 0x0001 210 211#define TXP_ERR_INTERNAL 0x0000 212#define TXP_ERR_FIFOUNDERRUN 0x0001 213#define TXP_ERR_BADSSD 0x0002 214#define TXP_ERR_RUNT 0x0003 215#define TXP_ERR_CRC 0x0004 216#define TXP_ERR_OVERSIZE 0x0005 217#define TXP_ERR_ALIGNMENT 0x0006 218#define TXP_ERR_DRIBBLEBIT 0x0007 219 220#define TXP_PROTO_UNKNOWN 0x0000 221#define TXP_PROTO_IP 0x0001 222#define TXP_PROTO_IPX 0x0002 223#define TXP_PROTO_RESERVED 0x0003 224 225#define TXP_STAT_PROTO 0x0001 226#define TXP_STAT_VLAN 0x0002 227#define TXP_STAT_IPFRAGMENT 0x0004 228#define TXP_STAT_IPSEC 0x0008 229#define TXP_STAT_IPCKSUMBAD 0x0010 230#define TXP_STAT_TCPCKSUMBAD 0x0020 231#define TXP_STAT_UDPCKSUMBAD 0x0040 232#define TXP_STAT_IPCKSUMGOOD 0x0080 233#define TXP_STAT_TCPCKSUMGOOD 0x0100 234#define TXP_STAT_UDPCKSUMGOOD 0x0200 235 236struct txp_tx_desc { 237 uint8_t tx_flags; /* type/descriptor flags */ 238 uint8_t tx_numdesc; /* number of descriptors */ 239 uint16_t tx_totlen; /* total packet length */ 240 uint32_t tx_addrlo; /* virt addr low word */ 241 uint32_t tx_addrhi; /* virt addr high word */ 242 uint32_t tx_pflags; /* processing flags */ 243}; 244#define TX_FLAGS_TYPE_M 0x07 /* type mask */ 245#define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 246#define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 247#define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 248#define TX_FLAGS_TYPE_OPT 0x03 /* type: options */ 249#define TX_FLAGS_TYPE_RX 0x04 /* type: command */ 250#define TX_FLAGS_TYPE_RESP 0x05 /* type: response */ 251#define TX_FLAGS_RESP 0x40 /* response requested */ 252#define TX_FLAGS_VALID 0x80 /* valid descriptor */ 253 254#define TX_PFLAGS_DNAC 0x00000001 /* do not add crc */ 255#define TX_PFLAGS_IPCKSUM 0x00000002 /* ip checksum */ 256#define TX_PFLAGS_TCPCKSUM 0x00000004 /* tcp checksum */ 257#define TX_PFLAGS_TCPSEG 0x00000008 /* tcp segmentation */ 258#define TX_PFLAGS_VLAN 0x00000010 /* insert vlan */ 259#define TX_PFLAGS_IPSEC 0x00000020 /* perform ipsec */ 260#define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */ 261#define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */ 262#define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */ 263#define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */ 264#define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */ 265#define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */ 266 267struct txp_rx_desc { 268 uint8_t rx_flags; /* type/descriptor flags */ 269 uint8_t rx_numdesc; /* number of descriptors */ 270 uint16_t rx_len; /* frame length */ 271 uint32_t rx_vaddrlo; /* virtual address, lo word */ 272 uint32_t rx_vaddrhi; /* virtual address, hi word */ 273 uint32_t rx_stat; /* status */ 274 uint16_t rx_filter; /* filter status */ 275 uint16_t rx_hash; /* hash status */ 276 uint32_t rx_vlan; /* vlan tag/priority */ 277}; 278 279/* txp_rx_desc.rx_flags */ 280#define RX_FLAGS_TYPE_M 0x07 /* type mask */ 281#define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 282#define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 283#define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 284#define RX_FLAGS_TYPE_OPT 0x03 /* type: options */ 285#define RX_FLAGS_TYPE_RX 0x04 /* type: command */ 286#define RX_FLAGS_TYPE_RESP 0x05 /* type: response */ 287#define RX_FLAGS_RCV_TYPE_M 0x18 /* rcvtype mask */ 288#define RX_FLAGS_RCV_TYPE_RX 0x00 /* rcvtype: receive */ 289#define RX_FLAGS_RCV_TYPE_RSP 0x08 /* rcvtype: response */ 290#define RX_FLAGS_ERROR 0x40 /* error in packet */ 291 292/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */ 293#define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */ 294#define RX_ERROR_FIFO 0x00000001 /* fifo underrun */ 295#define RX_ERROR_BADSSD 0x00000002 /* bad ssd */ 296#define RX_ERROR_RUNT 0x00000003 /* runt packet */ 297#define RX_ERROR_CRC 0x00000004 /* bad crc */ 298#define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */ 299#define RX_ERROR_ALIGN 0x00000006 /* alignment error */ 300#define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */ 301#define RX_ERROR_MASK 0x07 302 303/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */ 304#define RX_STAT_PROTO_M 0x00000003 /* protocol mask */ 305#define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */ 306#define RX_STAT_PROTO_IPX 0x00000001 /* IPX */ 307#define RX_STAT_PROTO_IP 0x00000002 /* IP */ 308#define RX_STAT_PROTO_RSV 0x00000003 /* reserved */ 309#define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */ 310#define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */ 311#define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */ 312#define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */ 313#define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */ 314#define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */ 315#define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */ 316#define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */ 317#define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */ 318 319 320struct txp_rxbuf_desc { 321 uint32_t rb_paddrlo; 322 uint32_t rb_paddrhi; 323 uint32_t rb_vaddrlo; 324 uint32_t rb_vaddrhi; 325}; 326 327/* Extension descriptor */ 328struct txp_ext_desc { 329 uint32_t ext_1; 330 uint32_t ext_2; 331 uint32_t ext_3; 332 uint32_t ext_4; 333}; 334 335struct txp_cmd_desc { 336 uint8_t cmd_flags; 337 uint8_t cmd_numdesc; 338 uint16_t cmd_id; 339 uint16_t cmd_seq; 340 uint16_t cmd_par1; 341 uint32_t cmd_par2; 342 uint32_t cmd_par3; 343}; 344#define CMD_FLAGS_TYPE_M 0x07 /* type mask */ 345#define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 346#define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 347#define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 348#define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */ 349#define CMD_FLAGS_TYPE_RX 0x04 /* type: command */ 350#define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */ 351#define CMD_FLAGS_RESP 0x40 /* response requested */ 352#define CMD_FLAGS_VALID 0x80 /* valid descriptor */ 353 354struct txp_rsp_desc { 355 uint8_t rsp_flags; 356 uint8_t rsp_numdesc; 357 uint16_t rsp_id; 358 uint16_t rsp_seq; 359 uint16_t rsp_par1; 360 uint32_t rsp_par2; 361 uint32_t rsp_par3; 362}; 363#define RSP_FLAGS_TYPE_M 0x07 /* type mask */ 364#define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 365#define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 366#define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 367#define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */ 368#define RSP_FLAGS_TYPE_RX 0x04 /* type: command */ 369#define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */ 370#define RSP_FLAGS_ERROR 0x40 /* response error */ 371 372struct txp_frag_desc { 373 uint8_t frag_flags; /* type/descriptor flags */ 374 uint8_t frag_rsvd1; 375 uint16_t frag_len; /* bytes in this fragment */ 376 uint32_t frag_addrlo; /* phys addr low word */ 377 uint32_t frag_addrhi; /* phys addr high word */ 378 uint32_t frag_rsvd2; 379}; 380#define FRAG_FLAGS_TYPE_M 0x07 /* type mask */ 381#define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 382#define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 383#define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 384#define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */ 385#define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */ 386#define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */ 387#define FRAG_FLAGS_VALID 0x80 /* valid descriptor */ 388 389struct txp_opt_desc { 390 uint8_t opt_desctype:3, 391 opt_rsvd:1, 392 opt_type:4; 393 394 uint8_t opt_num; 395 uint16_t opt_dep1; 396 uint32_t opt_dep2; 397 uint32_t opt_dep3; 398 uint32_t opt_dep4; 399}; 400 401struct txp_ipsec_desc { 402 uint8_t ipsec_desctpe:3, 403 ipsec_rsvd:1, 404 ipsec_type:4; 405 406 uint8_t ipsec_num; 407 uint16_t ipsec_flags; 408 uint16_t ipsec_ah1; 409 uint16_t ipsec_esp1; 410 uint16_t ipsec_ah2; 411 uint16_t ipsec_esp2; 412 uint32_t ipsec_rsvd1; 413}; 414 415struct txp_tcpseg_desc { 416 uint8_t tcpseg_type; 417 uint8_t tcpseg_num; 418 uint16_t tcpseg_mss; 419 uint32_t tcpseg_respaddr; 420 uint32_t tcpseg_txbytes; 421 uint32_t tcpseg_lss; 422}; 423#define TCPSEG_DESC_TYPE_M 0x07 /* type mask */ 424#define TCPSEG_DESC_TYPE_FRAG 0x00 /* type: fragment */ 425#define TCPSEG_DESC_TYPE_DATA 0x01 /* type: data frame */ 426#define TCPSEG_DESC_TYPE_CMD 0x02 /* type: command frame */ 427#define TCPSEG_DESC_TYPE_OPT 0x03 /* type: options */ 428#define TCPSEG_DESC_TYPE_RX 0x04 /* type: command */ 429#define TCPSEG_DESC_TYPE_RESP 0x05 /* type: response */ 430#define TCPSEG_OPT_IPSEC 0x00 431#define TCPSEG_OPT_TSO 0x10 432#define TCPSEG_MSS_MASK 0x0FFF 433#define TCPSEG_MSS_FIRST 0x1000 434#define TCPSEG_MSS_LAST 0x2000 435 436/* 437 * Transceiver types 438 */ 439#define TXP_XCVR_10_HDX 0 440#define TXP_XCVR_10_FDX 1 441#define TXP_XCVR_100_HDX 2 442#define TXP_XCVR_100_FDX 3 443#define TXP_XCVR_AUTO 4 444 445#define TXP_MEDIA_CRC 0x0004 /* crc strip disable */ 446#define TXP_MEDIA_CD 0x0010 /* collision detection */ 447#define TXP_MEDIA_CS 0x0020 /* carrier sense */ 448#define TXP_MEDIA_POL 0x0400 /* polarity reversed */ 449#define TXP_MEDIA_NOLINK 0x0800 /* 0 = link, 1 = no link */ 450 451/* 452 * receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE} 453 */ 454#define TXP_RXFILT_DIRECT 0x0001 /* directed packets */ 455#define TXP_RXFILT_ALLMULTI 0x0002 /* all multicast packets */ 456#define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */ 457#define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */ 458#define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */ 459 460/* 461 * boot record (pointers to rings) 462 */ 463struct txp_boot_record { 464 uint32_t br_hostvar_lo; /* host ring pointer */ 465 uint32_t br_hostvar_hi; 466 uint32_t br_txlopri_lo; /* tx low pri ring */ 467 uint32_t br_txlopri_hi; 468 uint32_t br_txlopri_siz; 469 uint32_t br_txhipri_lo; /* tx high pri ring */ 470 uint32_t br_txhipri_hi; 471 uint32_t br_txhipri_siz; 472 uint32_t br_rxlopri_lo; /* rx low pri ring */ 473 uint32_t br_rxlopri_hi; 474 uint32_t br_rxlopri_siz; 475 uint32_t br_rxbuf_lo; /* rx buffer ring */ 476 uint32_t br_rxbuf_hi; 477 uint32_t br_rxbuf_siz; 478 uint32_t br_cmd_lo; /* command ring */ 479 uint32_t br_cmd_hi; 480 uint32_t br_cmd_siz; 481 uint32_t br_resp_lo; /* response ring */ 482 uint32_t br_resp_hi; 483 uint32_t br_resp_siz; 484 uint32_t br_zero_lo; /* zero word */ 485 uint32_t br_zero_hi; 486 uint32_t br_rxhipri_lo; /* rx high pri ring */ 487 uint32_t br_rxhipri_hi; 488 uint32_t br_rxhipri_siz; 489}; 490 491/* 492 * hostvar structure (shared with typhoon) 493 */ 494struct txp_hostvar { 495 uint32_t hv_rx_hi_read_idx; /* host->arm */ 496 uint32_t hv_rx_lo_read_idx; /* host->arm */ 497 uint32_t hv_rx_buf_write_idx; /* host->arm */ 498 uint32_t hv_resp_read_idx; /* host->arm */ 499 uint32_t hv_tx_lo_desc_read_idx; /* arm->host */ 500 uint32_t hv_tx_hi_desc_read_idx; /* arm->host */ 501 uint32_t hv_rx_lo_write_idx; /* arm->host */ 502 uint32_t hv_rx_buf_read_idx; /* arm->host */ 503 uint32_t hv_cmd_read_idx; /* arm->host */ 504 uint32_t hv_resp_write_idx; /* arm->host */ 505 uint32_t hv_rx_hi_write_idx; /* arm->host */ 506}; 507 508/* 509 * TYPHOON status register state (in TXP_A2H_0) 510 */ 511#define STAT_ROM_CODE 0x00000001 512#define STAT_ROM_EEPROM_LOAD 0x00000002 513#define STAT_WAITING_FOR_BOOT 0x00000007 514#define STAT_RUNNING 0x00000009 515#define STAT_WAITING_FOR_HOST_REQUEST 0x0000000d 516#define STAT_WAITING_FOR_SEGMENT 0x00000010 517#define STAT_SLEEPING 0x00000011 518#define STAT_HALTED 0x00000014 519 520#define TX_ENTRIES 256 521#define RX_ENTRIES 128 522#define RXBUF_ENTRIES 256 523#define CMD_ENTRIES 32 524#define RSP_ENTRIES 32 525 526#define OFFLOAD_TCPCKSUM 0x00000002 /* tcp checksum */ 527#define OFFLOAD_UDPCKSUM 0x00000004 /* udp checksum */ 528#define OFFLOAD_IPCKSUM 0x00000008 /* ip checksum */ 529#define OFFLOAD_IPSEC 0x00000010 /* ipsec enable */ 530#define OFFLOAD_BCAST 0x00000020 /* broadcast throttle */ 531#define OFFLOAD_DHCP 0x00000040 /* dhcp prevention */ 532#define OFFLOAD_VLAN 0x00000080 /* vlan enable */ 533#define OFFLOAD_FILTER 0x00000100 /* filter enable */ 534#define OFFLOAD_TCPSEG 0x00000200 /* tcp segmentation */ 535#define OFFLOAD_MASK 0xfffffffe /* mask off low bit */ 536 537/* 538 * Macros for converting array indices to offsets within the descriptor 539 * arrays. The chip operates on offsets, but it's much easier for us 540 * to operate on indices. Assumes descriptor entries are 16 bytes. 541 */ 542#define TXP_IDX2OFFSET(idx) ((idx) << 4) 543#define TXP_OFFSET2IDX(off) ((off) >> 4) 544 545struct txp_cmd_ring { 546 struct txp_cmd_desc *base; 547 uint32_t lastwrite; 548 uint32_t size; 549}; 550 551struct txp_rsp_ring { 552 struct txp_rsp_desc *base; 553 uint32_t lastwrite; 554 uint32_t size; 555}; 556 557struct txp_tx_ring { 558 struct txp_tx_desc *r_desc; /* base address of descs */ 559 bus_dma_tag_t r_tag; 560 bus_dmamap_t r_map; 561 uint32_t r_reg; /* register to activate */ 562 uint32_t r_prod; /* producer */ 563 uint32_t r_cons; /* consumer */ 564 uint32_t r_cnt; /* # descs in use */ 565 uint32_t *r_off; /* hostvar index pointer */ 566}; 567 568struct txp_swdesc { 569 struct mbuf *sd_mbuf; 570 bus_dmamap_t sd_map; 571}; 572 573struct txp_rx_swdesc { 574 TAILQ_ENTRY(txp_rx_swdesc) sd_next; 575 struct mbuf *sd_mbuf; 576 bus_dmamap_t sd_map; 577}; 578 579struct txp_rx_ring { 580 struct txp_rx_desc *r_desc; /* base address of descs */ 581 bus_dma_tag_t r_tag; 582 bus_dmamap_t r_map; 583 uint32_t *r_roff; /* hv read offset ptr */ 584 uint32_t *r_woff; /* hv write offset ptr */ 585}; 586 587struct txp_ldata { 588 struct txp_boot_record *txp_boot; 589 bus_addr_t txp_boot_paddr; 590 struct txp_hostvar *txp_hostvar; 591 bus_addr_t txp_hostvar_paddr; 592 struct txp_tx_desc *txp_txhiring; 593 bus_addr_t txp_txhiring_paddr; 594 struct txp_tx_desc *txp_txloring; 595 bus_addr_t txp_txloring_paddr; 596 struct txp_rxbuf_desc *txp_rxbufs; 597 bus_addr_t txp_rxbufs_paddr; 598 struct txp_rx_desc *txp_rxhiring; 599 bus_addr_t txp_rxhiring_paddr; 600 struct txp_rx_desc *txp_rxloring; 601 bus_addr_t txp_rxloring_paddr; 602 struct txp_cmd_desc *txp_cmdring; 603 bus_addr_t txp_cmdring_paddr; 604 struct txp_rsp_desc *txp_rspring; 605 bus_addr_t txp_rspring_paddr; 606 uint32_t *txp_zero; 607 bus_addr_t txp_zero_paddr; 608}; 609 610struct txp_chain_data { 611 bus_dma_tag_t txp_parent_tag; 612 bus_dma_tag_t txp_boot_tag; 613 bus_dmamap_t txp_boot_map; 614 bus_dma_tag_t txp_hostvar_tag; 615 bus_dmamap_t txp_hostvar_map; 616 bus_dma_tag_t txp_txhiring_tag; 617 bus_dmamap_t txp_txhiring_map; 618 bus_dma_tag_t txp_txloring_tag; 619 bus_dmamap_t txp_txloring_map; 620 bus_dma_tag_t txp_tx_tag; 621 bus_dma_tag_t txp_rx_tag; 622 bus_dma_tag_t txp_rxbufs_tag; 623 bus_dmamap_t txp_rxbufs_map; 624 bus_dma_tag_t txp_rxhiring_tag; 625 bus_dmamap_t txp_rxhiring_map; 626 bus_dma_tag_t txp_rxloring_tag; 627 bus_dmamap_t txp_rxloring_map; 628 bus_dma_tag_t txp_cmdring_tag; 629 bus_dmamap_t txp_cmdring_map; 630 bus_dma_tag_t txp_rspring_tag; 631 bus_dmamap_t txp_rspring_map; 632 bus_dma_tag_t txp_zero_tag; 633 bus_dmamap_t txp_zero_map; 634}; 635 636struct txp_hw_stats { 637 uint32_t tx_frames; 638 uint64_t tx_bytes; 639 uint32_t tx_deferred; 640 uint32_t tx_late_colls; 641 uint32_t tx_colls; 642 uint32_t tx_carrier_lost; 643 uint32_t tx_multi_colls; 644 uint32_t tx_excess_colls; 645 uint32_t tx_fifo_underruns; 646 uint32_t tx_mcast_oflows; 647 uint32_t tx_filtered; 648 uint32_t rx_frames; 649 uint64_t rx_bytes; 650 uint32_t rx_fifo_oflows; 651 uint32_t rx_badssd; 652 uint32_t rx_crcerrs; 653 uint32_t rx_lenerrs; 654 uint32_t rx_bcast_frames; 655 uint32_t rx_mcast_frames; 656 uint32_t rx_oflows; 657 uint32_t rx_filtered; 658}; 659 660struct txp_softc { 661 struct ifnet *sc_ifp; 662 device_t sc_dev; 663 struct txp_hostvar *sc_hostvar; 664 struct txp_boot_record *sc_boot; 665 struct resource *sc_res; 666 int sc_res_id; 667 int sc_res_type; 668 struct resource *sc_irq; 669 void *sc_intrhand; 670 struct txp_chain_data sc_cdata; 671 struct txp_ldata sc_ldata; 672 int sc_rxbufprod; 673 int sc_process_limit; 674 struct txp_cmd_ring sc_cmdring; 675 struct txp_rsp_ring sc_rspring; 676 struct callout sc_tick; 677 struct ifmedia sc_ifmedia; 678 struct txp_hw_stats sc_ostats; 679 struct txp_hw_stats sc_stats; 680 struct txp_tx_ring sc_txhir, sc_txlor; 681 struct txp_swdesc sc_txd[TX_ENTRIES]; 682 struct txp_rxbuf_desc *sc_rxbufs; 683 struct txp_rx_ring sc_rxhir, sc_rxlor; 684 uint16_t sc_xcvr; 685 uint16_t sc_seq; 686 int sc_watchdog_timer; 687 int sc_if_flags; 688 int sc_flags; 689#define TXP_FLAG_DETACH 0x4000 690#define TXP_FLAG_LINK 0x8000 691 TAILQ_HEAD(, txp_rx_swdesc) sc_free_list; 692 TAILQ_HEAD(, txp_rx_swdesc) sc_busy_list; 693 struct task sc_int_task; 694 struct taskqueue *sc_tq; 695 struct mtx sc_mtx; 696}; 697 698struct txp_fw_file_header { 699 uint8_t magicid[8]; /* TYPHOON\0 */ 700 uint32_t version; 701 uint32_t nsections; 702 uint32_t addr; 703 uint32_t hmac[5]; 704}; 705 706struct txp_fw_section_header { 707 uint32_t nbytes; 708 uint16_t cksum; 709 uint16_t reserved; 710 uint32_t addr; 711}; 712 713#define TXP_MAX_SEGLEN 0xffff 714#define TXP_MAX_PKTLEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 715 716#define WRITE_REG(sc, reg, val) bus_write_4((sc)->sc_res, reg, val) 717#define READ_REG(sc, reg) bus_read_4((sc)->sc_res, reg) 718#define TXP_BARRIER(sc, o, l, f) bus_barrier((sc)->sc_res, (o), (l), (f)) 719 720#define TXP_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 721#define TXP_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 722#define TXP_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 723 724#define TXP_MAXTXSEGS 16 725#define TXP_RXBUF_ALIGN (sizeof(uint32_t)) 726 727#define TXP_PROC_MIN 16 728#define TXP_PROC_MAX RX_ENTRIES 729#define TXP_PROC_DEFAULT (RX_ENTRIES / 2) 730 731#define TXP_ADDR_HI(x) ((uint64_t)(x) >> 32) 732#define TXP_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff) 733 734/* 735 * 3Com PCI vendor ID. 736 */ 737#define TXP_VENDORID_3COM 0x10B7 738 739/* 740 * 3cR990 device IDs 741 */ 742#define TXP_DEVICEID_3CR990_TX_95 0x9902 743#define TXP_DEVICEID_3CR990_TX_97 0x9903 744#define TXP_DEVICEID_3CR990B_TXM 0x9904 745#define TXP_DEVICEID_3CR990_SRV_95 0x9908 746#define TXP_DEVICEID_3CR990_SRV_97 0x9909 747#define TXP_DEVICEID_3CR990B_SRV 0x990A 748 749struct txp_type { 750 uint16_t txp_vid; 751 uint16_t txp_did; 752 char *txp_name; 753}; 754 755#define TXP_TIMEOUT 10000 756#define TXP_CMD_NOWAIT 0 757#define TXP_CMD_WAIT 1 758#define TXP_TX_TIMEOUT 5 759 760/* 761 * Each frame requires one frame descriptor and one or more 762 * fragment descriptors. If TSO is used frame descriptor block 763 * requires one or two option frame descriptors depending on 764 * number of framents. Therefore we will consume three 765 * additional descriptors at most to use TSO for a frame and 766 * one reserved descriptor in order not to full Tx descriptor 767 * ring. 768 */ 769#define TXP_TXD_RESERVED 4 770 771#define TXP_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 772