cpucontrol.h revision 331722
1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD 29 * $FreeBSD: stable/11/sys/mips/nlm/hal/cpucontrol.h 331722 2018-03-29 02:50:57Z eadler $ 30 */ 31 32#ifndef __NLM_HAL_CPUCONTROL_H__ 33#define __NLM_HAL_CPUCONTROL_H__ 34 35#define CPU_BLOCKID_IFU 0 36#define CPU_BLOCKID_ICU 1 37#define CPU_BLOCKID_IEU 2 38#define CPU_BLOCKID_LSU 3 39#define CPU_BLOCKID_MMU 4 40#define CPU_BLOCKID_PRF 5 41#define CPU_BLOCKID_SCH 7 42#define CPU_BLOCKID_SCU 8 43#define CPU_BLOCKID_FPU 9 44#define CPU_BLOCKID_MAP 10 45 46#define LSU_DEFEATURE 0x304 47#define LSU_DEBUG_ADDR 0x305 48#define LSU_DEBUG_DATA0 0x306 49#define LSU_CERRLOG_REGID 0x09 50#define SCHED_DEFEATURE 0x700 51 52/* Offsets of interest from the 'MAP' Block */ 53#define MAP_THREADMODE 0x00 54#define MAP_EXT_EBASE_ENABLE 0x04 55#define MAP_CCDI_CONFIG 0x08 56#define MAP_THRD0_CCDI_STATUS 0x0c 57#define MAP_THRD1_CCDI_STATUS 0x10 58#define MAP_THRD2_CCDI_STATUS 0x14 59#define MAP_THRD3_CCDI_STATUS 0x18 60#define MAP_THRD0_DEBUG_MODE 0x1c 61#define MAP_THRD1_DEBUG_MODE 0x20 62#define MAP_THRD2_DEBUG_MODE 0x24 63#define MAP_THRD3_DEBUG_MODE 0x28 64#define MAP_MISC_STATE 0x60 65#define MAP_DEBUG_READ_CTL 0x64 66#define MAP_DEBUG_READ_REG0 0x68 67#define MAP_DEBUG_READ_REG1 0x6c 68 69#define MMU_SETUP 0x400 70#define MMU_LFSRSEED 0x401 71#define MMU_HPW_NUM_PAGE_LVL 0x410 72#define MMU_PGWKR_PGDBASE 0x411 73#define MMU_PGWKR_PGDSHFT 0x412 74#define MMU_PGWKR_PGDMASK 0x413 75#define MMU_PGWKR_PUDSHFT 0x414 76#define MMU_PGWKR_PUDMASK 0x415 77#define MMU_PGWKR_PMDSHFT 0x416 78#define MMU_PGWKR_PMDMASK 0x417 79#define MMU_PGWKR_PTESHFT 0x418 80#define MMU_PGWKR_PTEMASK 0x419 81 82 83#if !defined(LOCORE) && !defined(__ASSEMBLY__) 84#if defined(__mips_n64) || defined(__mips_n32) 85static __inline uint64_t 86nlm_mfcr(uint32_t reg) 87{ 88 uint64_t res; 89 90 __asm__ __volatile__( 91 ".set push\n\t" 92 ".set noreorder\n\t" 93 "move $9, %1\n\t" 94 ".word 0x71280018\n\t" /* mfcr $8, $9 */ 95 "move %0, $8\n\t" 96 ".set pop\n" 97 : "=r" (res) : "r"(reg) 98 : "$8", "$9" 99 ); 100 return (res); 101} 102 103static __inline void 104nlm_mtcr(uint32_t reg, uint64_t value) 105{ 106 __asm__ __volatile__( 107 ".set push\n\t" 108 ".set noreorder\n\t" 109 "move $8, %0\n" 110 "move $9, %1\n" 111 ".word 0x71280019\n" /* mtcr $8, $9 */ 112 ".set pop\n" 113 : 114 : "r" (value), "r" (reg) 115 : "$8", "$9" 116 ); 117} 118 119#else /* !(defined(__mips_n64) || defined(__mips_n32)) */ 120 121static __inline__ uint64_t 122nlm_mfcr(uint32_t reg) 123{ 124 uint32_t hi, lo; 125 126 __asm__ __volatile__ ( 127 ".set push\n" 128 ".set mips64\n" 129 "move $8, %2\n" 130 ".word 0x71090018\n" 131 "nop \n" 132 "dsra32 %0, $9, 0\n" 133 "sll %1, $9, 0\n" 134 ".set pop\n" 135 : "=r"(hi), "=r"(lo) 136 : "r"(reg) : "$8", "$9"); 137 138 return (((uint64_t)hi) << 32) | lo; 139} 140 141static __inline__ void 142nlm_mtcr(uint32_t reg, uint64_t val) 143{ 144 uint32_t hi, lo; 145 146 hi = val >> 32; 147 lo = val & 0xffffffff; 148 149 __asm__ __volatile__ ( 150 ".set push\n" 151 ".set mips64\n" 152 "move $9, %0\n" 153 "dsll32 $9, %1, 0\n" 154 "dsll32 $8, %0, 0\n" 155 "dsrl32 $9, $9, 0\n" 156 "or $9, $9, $8\n" 157 "move $8, %2\n" 158 ".word 0x71090019\n" 159 "nop \n" 160 ".set pop\n" 161 : :"r"(hi), "r"(lo), "r"(reg) 162 : "$8", "$9"); 163} 164#endif /* (defined(__mips_n64) || defined(__mips_n32)) */ 165 166/* hashindex_en = 1 to enable hash mode, hashindex_en=0 to disable 167 * global_mode = 1 to enable global mode, global_mode=0 to disable 168 * clk_gating = 0 to enable clock gating, clk_gating=1 to disable 169 */ 170static __inline__ void nlm_mmu_setup(int hashindex_en, int global_mode, 171 int clk_gating) 172{ 173 uint32_t mmusetup = 0; 174 175 mmusetup |= (hashindex_en << 13); 176 mmusetup |= (clk_gating << 3); 177 mmusetup |= (global_mode << 0); 178 nlm_mtcr(MMU_SETUP, mmusetup); 179} 180 181static __inline__ void nlm_mmu_lfsr_seed (int thr0_seed, int thr1_seed, 182 int thr2_seed, int thr3_seed) 183{ 184 uint32_t seed = nlm_mfcr(MMU_LFSRSEED); 185 186 seed |= ((thr3_seed & 0x7f) << 23); 187 seed |= ((thr2_seed & 0x7f) << 16); 188 seed |= ((thr1_seed & 0x7f) << 7); 189 seed |= ((thr0_seed & 0x7f) << 0); 190 nlm_mtcr(MMU_LFSRSEED, seed); 191} 192 193#endif /* __ASSEMBLY__ */ 194#endif /* __NLM_CPUCONTROL_H__ */ 195