scu_bios_definitions.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 23 * The full GNU General Public License is included in this distribution 24 * in the file called LICENSE.GPL. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 35 * * Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * * Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in 39 * the documentation and/or other materials provided with the 40 * distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 * $FreeBSD: stable/11/sys/dev/isci/scil/scu_bios_definitions.h 330897 2018-03-14 03:19:51Z eadler $ 55 */ 56#ifndef _SCU_BIOS_DEFINITIONS_H_ 57#define _SCU_BIOS_DEFINITIONS_H_ 58 59#ifdef __cplusplus 60extern "C" { 61#endif // __cplusplus 62 63/** 64 * IMPORTANT NOTE: 65 * This file can be used by an SCI Library based driver or 66 * stand-alone where the library is excluded. By excluding 67 * the SCI Library, inclusion of OS specific header files can 68 * be avoided. For example, a BIOS utility probably does not 69 * want to be bothered with inclusion of nested OS DDK include 70 * files that are not necessary for its function. 71 * 72 * To exclude the SCI Library, either uncomment the EXCLUDE_SCI_LIBRARY 73 * #define statement in environment.h or define the statement as an input 74 * to your compiler. 75 */ 76 77#include <dev/isci/environment.h> 78 79#ifndef EXCLUDE_SCI_LIBRARY 80#include <dev/isci/scil/sci_types.h> 81#include <dev/isci/scil/intel_sas.h> 82#include <dev/isci/scil/sci_controller_constants.h> 83#endif /* EXCLUDE_SCI_LIBRARY */ 84 85 86 87// For Intel Storage Controller Unit OEM Block 88#define SCI_OEM_PARAM_SIGNATURE "ISCUOEMB" 89 90#define SCI_PREBOOT_SOURCE_INIT (0x00) 91#define SCI_PREBOOT_SOURCE_OROM (0x80) 92#define SCI_PREBOOT_SOURCE_EFI (0x81) 93 94#define SCI_OEM_PARAM_VER_1_0 (0x10) 95#define SCI_OEM_PARAM_VER_1_1 (0x11) 96#define SCI_OEM_PARAM_VER_1_2 (0x12) 97#define SCI_OEM_PARAM_VER_1_3 (0x13) 98 99// current version 100#define SCI_OEM_PARAM_VER_CUR SCI_OEM_PARAM_VER_1_3 101 102// port configuration mode 103#define SCI_BIOS_MODE_MPC (0x00) 104#define SCI_BIOS_MODE_APC (0x01) 105 106 107#ifndef SCI_MAX_PHYS 108#define SCI_MAX_PHYS (4) 109#endif 110 111#ifndef SCI_MAX_PORTS 112#define SCI_MAX_PORTS (4) 113#endif 114 115 116/** 117 * @struct SCI_BIOS_OEM_PARAM_BLOCK_HDR 118 * 119 * @brief This structure defines the OEM Parameter block header. 120 */ 121typedef struct SCI_BIOS_OEM_PARAM_BLOCK_HDR 122{ 123 /** 124 * This field contains the OEM Parameter Block Signature which is 125 * used by BIOS and driver software to identify that the memory location 126 * contains valid OEM Parameter data. The value must be set to 127 * SCI_OEM_PARAM_SIGNATURE which is the string "ISCUOEMB" which 128 * stands for Intel Storage Controller Unit OEM Block. 129 */ 130 U8 signature[8]; 131 /** 132 * This field contains the size in bytes of the complete OEM 133 * Parameter Block, both header and payload hdr_length + 134 * (num_elements * element_length). 135 */ 136 U16 total_block_length; 137 /** 138 * This field contains the size in bytes of the 139 * SCI_BIOS_OEM_PARAM_BLOCK_HDR. It also indicates the offset from 140 * the beginning of this data structure to where the actual 141 * parameter data payload begins. 142 */ 143 U8 hdr_length; 144 /** 145 * This field contains the version info defining the structure 146 * of the OEM Parameter block. 147 */ 148 U8 version; 149 /** 150 * This field contains a value indicating the preboot initialization 151 * method (Option ROM or UEFI driver) so that after OS transition, 152 * the OS driver can know the preboot method. OEMs who build a single 153 * flash image where the preboot method is unknown at manufacturing 154 * time should set this field to SCI_PREBOOT_SOURCE_INIT. Then 155 * after the block is retrieved into host memory and under preboot 156 * driver control, the OROM or UEFI driver can set this field 157 * appropriately (SCI_PREBOOT_SOURCE_OROM and SCI_PREBOOT_SOURCE_EFI, 158 * respectively). 159 */ 160 U8 preboot_source; 161 /** 162 * This field contains the number of parameter descriptor elements 163 * (i.e. controller_elements) following this header. The number of 164 * elements corresponds to the number of SCU controller units contained 165 * in the platform: 166 * controller_element[0] = SCU0 167 * controller_element[1] = SCU1 168 */ 169 U8 num_elements; 170 /** 171 * This field contains the size in bytes of the descriptor element(s) 172 * in the block. 173 */ 174 U16 element_length; 175 /** 176 * Reserve fields for future use. 177 */ 178 U8 reserved[8]; 179 180} SCI_BIOS_OEM_PARAM_BLOCK_HDR_T; 181 182 183/** 184 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.0 185 * 186 * @brief This structure delineates the various OEM parameters that must 187 * be set for the Intel SAS Storage Controller Unit (SCU). 188 */ 189typedef struct SCI_BIOS_OEM_PARAM_ELEMENT 190{ 191 /** 192 * Per SCU Controller Data 193 */ 194 struct 195 { 196 /** 197 * This field indicates the port configuration mode for 198 * this controller: 199 * Automatic Port Configuration(APC) or 200 * Manual Port Configuration (MPC). 201 * 202 * APC means the Platform OEM expects SCI to configure 203 * SAS Ports automatically according to the discovered SAS 204 * Address pairs of the endpoints, wide and/or narrow. 205 * 206 * MPC means the Platform OEM manually defines wide or narrow 207 * connectors by apriori assigning PHYs to SAS Ports. 208 * 209 * By default, the mode type is APC 210 * in APC mode, if ANY of the phy mask is non-zero, 211 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 212 * from scic_oem_parameters_set AND the default oem 213 * configuration will be applied 214 * in MPC mode, if ALL of the phy masks are zero, 215 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 216 * from scic_oem_parameters_set AND the default oem 217 * configuration will be applied 218 */ 219 U8 mode_type; 220 221 /** 222 * This field specifies the maximum number of direct attached 223 * devices the OEM will allow to have powered up simultaneously 224 * on this controller. This allows the OEM to avoid exceeding 225 * power supply limits for this platform. A value of zero 226 * indicates there are no restrictions. 227 */ 228 U8 max_number_concurrent_device_spin_up; 229 230 /** 231 * This field indicates OEM's desired default 232 * Spread Spectrum Clocking (SSC) setting for Tx: 233 * enabled = 1 234 * disabled = 0 235 */ 236 U8 do_enable_ssc; 237 238 U8 reserved; 239 240 } controller; 241 242 /** 243 * Per SAS Port data. 244 */ 245 struct 246 { 247 /** 248 * This field specifies the phys to be contained inside a port. 249 * The bit position in the mask specifies the index of the phy 250 * to be contained in the port. Multiple bits (i.e. phys) 251 * can be contained in a single port: 252 * Bit 0 = This controller's PHY index 0 (0x01) 253 * Bit 1 = This controller's PHY index 1 (0x02) 254 * Bit 2 = This controller's PHY index 2 (0x04) 255 * Bit 3 = This controller's PHY index 3 (0x08) 256 * 257 * Refer to the mode_type field for rules regarding APC and MPC mode. 258 * General rule: For APC mode phy_mask = 0 259 */ 260 U8 phy_mask; 261 262 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 263 264 /** 265 * Per PHY Parameter data. 266 */ 267 struct 268 { 269 /** 270 * This field indicates the SAS Address that will be transmitted on 271 * this PHY index. The field is defined as a union, however, the 272 * OEM should use the U8 array definition when encoding it to ensure 273 * correct byte ordering. 274 * 275 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 276 * SAS Addresses for all PHYs within a controller group SHALL be the 277 * same. 278 */ 279 union 280 { 281 /** 282 * The array should be stored in little endian order. For example, 283 * if the desired SAS Address is 0x50010B90_0003538D, then it 284 * should be stored in the following manner: 285 * array[0] = 0x90 286 * array[1] = 0x0B 287 * array[2] = 0x01 288 * array[3] = 0x50 289 * array[4] = 0x8D 290 * array[5] = 0x53 291 * array[6] = 0x03 292 * array[7] = 0x00 293 */ 294 U8 array[8]; 295 /** 296 * This is the typedef'd version of the SAS Address used in 297 * the SCI Library. 298 */ 299 SCI_SAS_ADDRESS_T sci_format; 300 301 } sas_address; 302 303 /** 304 * These are the per PHY equalization settings associated with the 305 * AFE XCVR Tx Amplitude and Equalization Control Register Set 306 * (0 thru 3). 307 * 308 * Operational Note: The following Look-Up-Table registers are engaged 309 * by the AFE block after the following: 310 * - Software programs the Link Layer AFE Look Up Table Control 311 * Registers (AFE_LUTCR). 312 * - Software sets AFE XCVR Tx Control Register Tx Equalization 313 * Enable bit. 314 */ 315 /** 316 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 317 * LUTSel=00b. It contains the Tx Equalization settings that will be 318 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 319 */ 320 U32 afe_tx_amp_control0; 321 322 /** 323 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 324 * LUTSel=01b. It contains the Tx Equalization settings that will 325 * be used if a SATA 6.0Gbs device is direct-attached. 326 */ 327 U32 afe_tx_amp_control1; 328 329 /** 330 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 331 * LUTSel=10b. It contains the Tx Equalization settings that will 332 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 333 */ 334 U32 afe_tx_amp_control2; 335 336 /** 337 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 338 * LUTSel=11b. It contains the Tx Equalization settings that will 339 * be used if a SAS 6.0Gbs device is direct-attached. 340 */ 341 U32 afe_tx_amp_control3; 342 343 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 344 345} SCI_BIOS_OEM_PARAM_ELEMENT_T; 346 347/** 348 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.1 349 * 350 * @brief This structure delineates the various OEM parameters that must 351 * be set for the Intel SAS Storage Controller Unit (SCU). 352 */ 353typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1 354{ 355 /** 356 * Per SCU Controller Data 357 */ 358 struct 359 { 360 /** 361 * This field indicates the port configuration mode for 362 * this controller: 363 * Automatic Port Configuration(APC) or 364 * Manual Port Configuration (MPC). 365 * 366 * APC means the Platform OEM expects SCI to configure 367 * SAS Ports automatically according to the discovered SAS 368 * Address pairs of the endpoints, wide and/or narrow. 369 * 370 * MPC means the Platform OEM manually defines wide or narrow 371 * connectors by apriori assigning PHYs to SAS Ports. 372 * 373 * By default, the mode type is APC 374 * in APC mode, if ANY of the phy mask is non-zero, 375 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 376 * from scic_oem_parameters_set AND the default oem 377 * configuration will be applied 378 * in MPC mode, if ALL of the phy masks are zero, 379 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 380 * from scic_oem_parameters_set AND the default oem 381 * configuration will be applied 382 */ 383 U8 mode_type; 384 385 /** 386 * This field specifies the maximum number of direct attached 387 * devices the OEM will allow to have powered up simultaneously 388 * on this controller. This allows the OEM to avoid exceeding 389 * power supply limits for this platform. A value of zero 390 * indicates there are no restrictions. 391 */ 392 U8 max_number_concurrent_device_spin_up; 393 394 /** 395 * This bitfield indicates the OEM's desired default Tx 396 * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 397 * NOTE: Default SSC Modulation Frequency is 31.5KHz. 398 *--------------------------------------------------------------------*/ 399 /** 400 * NOTE: Max spread for SATA is +0 / -5000 PPM. 401 * Down-spreading SSC (only method allowed for SATA): 402 * SATA SSC Tx Disabled = 0x0 403 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 404 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 405 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 406 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 407 */ 408 U8 ssc_sata_tx_spread_level : 4; 409 410 /** 411 * SAS SSC Tx Disabled = 0x0 412 * 413 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM 414 * Down-spreading SSC: 415 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 416 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 417 * 418 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM 419 * Center-spreading SSC: 420 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 421 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 422 */ 423 U8 ssc_sas_tx_spread_level : 3; 424 /** 425 * NOTE: Refer to the SSC section of the SAS 2.x Specification 426 * for proper setting of this field. For standard SAS Initiator 427 * SAS PHY operation it should be 0 for Down-spreading. 428 * SAS SSC Tx spread type: 429 * Down-spreading SSC = 0 430 * Center-spreading SSC = 1 431 */ 432 U8 ssc_sas_tx_type : 1; 433 /*--------------------------------------------------------------------*/ 434 435 U8 reserved; 436 437 } controller; 438 439 /** 440 * Per SAS Port data. 441 */ 442 struct 443 { 444 /** 445 * This field specifies the phys to be contained inside a port. 446 * The bit position in the mask specifies the index of the phy 447 * to be contained in the port. Multiple bits (i.e. phys) 448 * can be contained in a single port: 449 * Bit 0 = This controller's PHY index 0 (0x01) 450 * Bit 1 = This controller's PHY index 1 (0x02) 451 * Bit 2 = This controller's PHY index 2 (0x04) 452 * Bit 3 = This controller's PHY index 3 (0x08) 453 * 454 * Refer to the mode_type field for rules regarding APC and MPC mode. 455 * General rule: For APC mode phy_mask = 0 456 */ 457 U8 phy_mask; 458 459 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 460 461 /** 462 * Per PHY Parameter data. 463 */ 464 struct 465 { 466 /** 467 * This field indicates the SAS Address that will be transmitted on 468 * this PHY index. The field is defined as a union, however, the 469 * OEM should use the U8 array definition when encoding it to ensure 470 * correct byte ordering. 471 * 472 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 473 * SAS Addresses for all PHYs within a controller group SHALL be the 474 * same. 475 */ 476 union 477 { 478 /** 479 * The array should be stored in little endian order. For example, 480 * if the desired SAS Address is 0x50010B90_0003538D, then it 481 * should be stored in the following manner: 482 * array[0] = 0x90 483 * array[1] = 0x0B 484 * array[2] = 0x01 485 * array[3] = 0x50 486 * array[4] = 0x8D 487 * array[5] = 0x53 488 * array[6] = 0x03 489 * array[7] = 0x00 490 */ 491 U8 array[8]; 492 /** 493 * This is the typedef'd version of the SAS Address used in 494 * the SCI Library. 495 */ 496 SCI_SAS_ADDRESS_T sci_format; 497 498 } sas_address; 499 500 /** 501 * These are the per PHY equalization settings associated with the 502 * AFE XCVR Tx Amplitude and Equalization Control Register Set 503 * (0 thru 3). 504 * 505 * Operational Note: The following Look-Up-Table registers are engaged 506 * by the AFE block after the following: 507 * - Software programs the Link Layer AFE Look Up Table Control 508 * Registers (AFE_LUTCR). 509 * - Software sets AFE XCVR Tx Control Register Tx Equalization 510 * Enable bit. 511 */ 512 /** 513 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 514 * LUTSel=00b. It contains the Tx Equalization settings that will be 515 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 516 */ 517 U32 afe_tx_amp_control0; 518 519 /** 520 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 521 * LUTSel=01b. It contains the Tx Equalization settings that will 522 * be used if a SATA 6.0Gbs device is direct-attached. 523 */ 524 U32 afe_tx_amp_control1; 525 526 /** 527 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 528 * LUTSel=10b. It contains the Tx Equalization settings that will 529 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 530 */ 531 U32 afe_tx_amp_control2; 532 533 /** 534 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 535 * LUTSel=11b. It contains the Tx Equalization settings that will 536 * be used if a SAS 6.0Gbs device is direct-attached. 537 */ 538 U32 afe_tx_amp_control3; 539 540 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 541 542} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1_T; 543 544/** 545 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.2 546 * 547 * @brief This structure delineates the various OEM parameters that must 548 * be set for the Intel SAS Storage Controller Unit (SCU). 549 */ 550typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2 551{ 552 /** 553 * Per SCU Controller Data 554 */ 555 struct 556 { 557 /** 558 * This field indicates the port configuration mode for 559 * this controller: 560 * Automatic Port Configuration(APC) or 561 * Manual Port Configuration (MPC). 562 * 563 * APC means the Platform OEM expects SCI to configure 564 * SAS Ports automatically according to the discovered SAS 565 * Address pairs of the endpoints, wide and/or narrow. 566 * 567 * MPC means the Platform OEM manually defines wide or narrow 568 * connectors by apriori assigning PHYs to SAS Ports. 569 * 570 * By default, the mode type is APC 571 * in APC mode, if ANY of the phy mask is non-zero, 572 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 573 * from scic_oem_parameters_set AND the default oem 574 * configuration will be applied 575 * in MPC mode, if ALL of the phy masks are zero, 576 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 577 * from scic_oem_parameters_set AND the default oem 578 * configuration will be applied 579 */ 580 U8 mode_type; 581 582 /** 583 * This field specifies the maximum number of direct attached 584 * devices the OEM will allow to have powered up simultaneously 585 * on this controller. This allows the OEM to avoid exceeding 586 * power supply limits for this platform. A value of zero 587 * indicates there are no restrictions. 588 */ 589 U8 max_number_concurrent_device_spin_up; 590 591 /** 592 * This bitfield indicates the OEM's desired default Tx 593 * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 594 * NOTE: Default SSC Modulation Frequency is 31.5KHz. 595 *--------------------------------------------------------------------*/ 596 /** 597 * NOTE: Max spread for SATA is +0 / -5000 PPM. 598 * Down-spreading SSC (only method allowed for SATA): 599 * SATA SSC Tx Disabled = 0x0 600 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 601 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 602 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 603 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 604 */ 605 U8 ssc_sata_tx_spread_level : 4; 606 607 /** 608 * SAS SSC Tx Disabled = 0x0 609 * 610 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM 611 * Down-spreading SSC: 612 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 613 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 614 * 615 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM 616 * Center-spreading SSC: 617 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 618 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 619 */ 620 U8 ssc_sas_tx_spread_level : 3; 621 /** 622 * NOTE: Refer to the SSC section of the SAS 2.x Specification 623 * for proper setting of this field. For standard SAS Initiator 624 * SAS PHY operation it should be 0 for Down-spreading. 625 * SAS SSC Tx spread type: 626 * Down-spreading SSC = 0 627 * Center-spreading SSC = 1 628 */ 629 U8 ssc_sas_tx_type : 1; 630 631 /** 632 * This field indicates length of the SAS/SATA cable between 633 * host and device. 634 * This field is used make relationship between analog parameters of 635 * the phy in the silicon and length of the cable. 636 * Supported length: "short"- up to 3m, "long"- more than 3m 637 * This is bit mask field: 638 * 639 * BIT: 7 6 5 4 3 2 1 0 (LSB) 640 * ASSIGNMENT: <-><-><-><-><phy3><phy2><phy1><phy0> 641 * 642 * For short cable corresponding bit shall be reset, 643 * for long cable shall be set. 644 */ 645 U8 long_cable_selection_mask; 646 647 } controller; 648 649 /** 650 * Per SAS Port data. 651 */ 652 struct 653 { 654 /** 655 * This field specifies the phys to be contained inside a port. 656 * The bit position in the mask specifies the index of the phy 657 * to be contained in the port. Multiple bits (i.e. phys) 658 * can be contained in a single port: 659 * Bit 0 = This controller's PHY index 0 (0x01) 660 * Bit 1 = This controller's PHY index 1 (0x02) 661 * Bit 2 = This controller's PHY index 2 (0x04) 662 * Bit 3 = This controller's PHY index 3 (0x08) 663 * 664 * Refer to the mode_type field for rules regarding APC and MPC mode. 665 * General rule: For APC mode phy_mask = 0 666 */ 667 U8 phy_mask; 668 669 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 670 671 /** 672 * Per PHY Parameter data. 673 */ 674 struct 675 { 676 /** 677 * This field indicates the SAS Address that will be transmitted on 678 * this PHY index. The field is defined as a union, however, the 679 * OEM should use the U8 array definition when encoding it to ensure 680 * correct byte ordering. 681 * 682 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 683 * SAS Addresses for all PHYs within a controller group SHALL be the 684 * same. 685 */ 686 union 687 { 688 /** 689 * The array should be stored in little endian order. For example, 690 * if the desired SAS Address is 0x50010B90_0003538D, then it 691 * should be stored in the following manner: 692 * array[0] = 0x90 693 * array[1] = 0x0B 694 * array[2] = 0x01 695 * array[3] = 0x50 696 * array[4] = 0x8D 697 * array[5] = 0x53 698 * array[6] = 0x03 699 * array[7] = 0x00 700 */ 701 U8 array[8]; 702 /** 703 * This is the typedef'd version of the SAS Address used in 704 * the SCI Library. 705 */ 706 SCI_SAS_ADDRESS_T sci_format; 707 708 } sas_address; 709 710 /** 711 * These are the per PHY equalization settings associated with the 712 * AFE XCVR Tx Amplitude and Equalization Control Register Set 713 * (0 thru 3). 714 * 715 * Operational Note: The following Look-Up-Table registers are engaged 716 * by the AFE block after the following: 717 * - Software programs the Link Layer AFE Look Up Table Control 718 * Registers (AFE_LUTCR). 719 * - Software sets AFE XCVR Tx Control Register Tx Equalization 720 * Enable bit. 721 */ 722 /** 723 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 724 * LUTSel=00b. It contains the Tx Equalization settings that will be 725 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 726 */ 727 U32 afe_tx_amp_control0; 728 729 /** 730 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 731 * LUTSel=01b. It contains the Tx Equalization settings that will 732 * be used if a SATA 6.0Gbs device is direct-attached. 733 */ 734 U32 afe_tx_amp_control1; 735 736 /** 737 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 738 * LUTSel=10b. It contains the Tx Equalization settings that will 739 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 740 */ 741 U32 afe_tx_amp_control2; 742 743 /** 744 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 745 * LUTSel=11b. It contains the Tx Equalization settings that will 746 * be used if a SAS 6.0Gbs device is direct-attached. 747 */ 748 U32 afe_tx_amp_control3; 749 750 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 751 752} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2_T; 753 754/** 755 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.3 756 * 757 * @brief This structure delineates the various OEM parameters that must 758 * be set for the Intel SAS Storage Controller Unit (SCU). 759 */ 760typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3 761{ 762 /** 763 * Per SCU Controller Data 764 */ 765 struct 766 { 767 /** 768 * This field indicates the port configuration mode for 769 * this controller: 770 * Automatic Port Configuration(APC) or 771 * Manual Port Configuration (MPC). 772 * 773 * APC means the Platform OEM expects SCI to configure 774 * SAS Ports automatically according to the discovered SAS 775 * Address pairs of the endpoints, wide and/or narrow. 776 * 777 * MPC means the Platform OEM manually defines wide or narrow 778 * connectors by apriori assigning PHYs to SAS Ports. 779 * 780 * By default, the mode type is APC 781 * in APC mode, if ANY of the phy mask is non-zero, 782 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 783 * from scic_oem_parameters_set AND the default oem 784 * configuration will be applied 785 * in MPC mode, if ALL of the phy masks are zero, 786 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 787 * from scic_oem_parameters_set AND the default oem 788 * configuration will be applied 789 */ 790 U8 mode_type; 791 792 /** 793 * This field specifies the maximum number of direct attached 794 * devices the OEM will allow to have powered up simultaneously 795 * on this controller. This allows the OEM to avoid exceeding 796 * power supply limits for this platform. A value of zero 797 * indicates there are no restrictions. 798 */ 799 U8 max_number_concurrent_device_spin_up; 800 801 /** 802 * This bitfield indicates the OEM's desired default Tx 803 * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 804 * NOTE: Default SSC Modulation Frequency is 31.5KHz. 805 *--------------------------------------------------------------------*/ 806 /** 807 * NOTE: Max spread for SATA is +0 / -5000 PPM. 808 * Down-spreading SSC (only method allowed for SATA): 809 * SATA SSC Tx Disabled = 0x0 810 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 811 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 812 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 813 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 814 */ 815 U8 ssc_sata_tx_spread_level : 4; 816 817 /** 818 * SAS SSC Tx Disabled = 0x0 819 * 820 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM 821 * Down-spreading SSC: 822 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 823 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 824 * 825 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM 826 * Center-spreading SSC: 827 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 828 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 829 */ 830 U8 ssc_sas_tx_spread_level : 3; 831 /** 832 * NOTE: Refer to the SSC section of the SAS 2.x Specification 833 * for proper setting of this field. For standard SAS Initiator 834 * SAS PHY operation it should be 0 for Down-spreading. 835 * SAS SSC Tx spread type: 836 * Down-spreading SSC = 0 837 * Center-spreading SSC = 1 838 */ 839 U8 ssc_sas_tx_type : 1; 840 841 /** 842 * This field indicates length of the SAS/SATA cable between 843 * host and device. 844 * This field is used make relationship between analog parameters of 845 * the phy in the silicon and length of the cable. 846 * Supported cable attenuation levels: 847 * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than 6m 848 * This is bit mask field: 849 * 850 * BIT: (MSB) 7 6 5 4 851 * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Medium cable length assignment 852 * BIT: 3 2 1 0 (LSB) 853 * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Long cable length assignment 854 * 855 * BITS 7-4 are set when the cable length is assigned to medium 856 * BITS 3-0 are set when the cable length is assigned to long 857 * The BIT positions are clear when the cable length is assigned to short 858 * Setting the bits for both long and medium cable length is undefined. 859 * 860 * A value of 0x84 would assign 861 * phy3 - medium 862 * phy2 - long 863 * phy1 - short 864 * phy0 - short 865 */ 866 U8 cable_selection_mask; 867 868 } controller; 869 870 /** 871 * Per SAS Port data. 872 */ 873 struct 874 { 875 /** 876 * This field specifies the phys to be contained inside a port. 877 * The bit position in the mask specifies the index of the phy 878 * to be contained in the port. Multiple bits (i.e. phys) 879 * can be contained in a single port: 880 * Bit 0 = This controller's PHY index 0 (0x01) 881 * Bit 1 = This controller's PHY index 1 (0x02) 882 * Bit 2 = This controller's PHY index 2 (0x04) 883 * Bit 3 = This controller's PHY index 3 (0x08) 884 * 885 * Refer to the mode_type field for rules regarding APC and MPC mode. 886 * General rule: For APC mode phy_mask = 0 887 */ 888 U8 phy_mask; 889 890 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 891 892 /** 893 * Per PHY Parameter data. 894 */ 895 struct 896 { 897 /** 898 * This field indicates the SAS Address that will be transmitted on 899 * this PHY index. The field is defined as a union, however, the 900 * OEM should use the U8 array definition when encoding it to ensure 901 * correct byte ordering. 902 * 903 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 904 * SAS Addresses for all PHYs within a controller group SHALL be the 905 * same. 906 */ 907 union 908 { 909 /** 910 * The array should be stored in little endian order. For example, 911 * if the desired SAS Address is 0x50010B90_0003538D, then it 912 * should be stored in the following manner: 913 * array[0] = 0x90 914 * array[1] = 0x0B 915 * array[2] = 0x01 916 * array[3] = 0x50 917 * array[4] = 0x8D 918 * array[5] = 0x53 919 * array[6] = 0x03 920 * array[7] = 0x00 921 */ 922 U8 array[8]; 923 /** 924 * This is the typedef'd version of the SAS Address used in 925 * the SCI Library. 926 */ 927 SCI_SAS_ADDRESS_T sci_format; 928 929 } sas_address; 930 931 /** 932 * These are the per PHY equalization settings associated with the 933 * AFE XCVR Tx Amplitude and Equalization Control Register Set 934 * (0 thru 3). 935 * 936 * Operational Note: The following Look-Up-Table registers are engaged 937 * by the AFE block after the following: 938 * - Software programs the Link Layer AFE Look Up Table Control 939 * Registers (AFE_LUTCR). 940 * - Software sets AFE XCVR Tx Control Register Tx Equalization 941 * Enable bit. 942 */ 943 /** 944 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 945 * LUTSel=00b. It contains the Tx Equalization settings that will be 946 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 947 */ 948 U32 afe_tx_amp_control0; 949 950 /** 951 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 952 * LUTSel=01b. It contains the Tx Equalization settings that will 953 * be used if a SATA 6.0Gbs device is direct-attached. 954 */ 955 U32 afe_tx_amp_control1; 956 957 /** 958 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 959 * LUTSel=10b. It contains the Tx Equalization settings that will 960 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 961 */ 962 U32 afe_tx_amp_control2; 963 964 /** 965 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 966 * LUTSel=11b. It contains the Tx Equalization settings that will 967 * be used if a SAS 6.0Gbs device is direct-attached. 968 */ 969 U32 afe_tx_amp_control3; 970 971 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 972 973} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3_T; 974 975/** 976 * @struct SCI_BIOS_OEM_PARAM_BLOCK 977 * 978 * @brief This structure defines the OEM Parameter block as it will be stored 979 * in the last 512 bytes of the PDR region in the SPI flash. It must be 980 * unpacked or pack(1). 981 */ 982typedef struct SCI_BIOS_OEM_PARAM_BLOCK 983{ 984 /** 985 * OEM Parameter Block header. 986 */ 987 SCI_BIOS_OEM_PARAM_BLOCK_HDR_T header; 988 989 /** 990 * Per controller element descriptor containing the controller's 991 * parameter data. The prototype defines just one of these descriptors, 992 * however, the actual runtime number is determined by the num_elements 993 * field in the header. 994 */ 995 SCI_BIOS_OEM_PARAM_ELEMENT_T controller_element[1]; 996 997} SCI_BIOS_OEM_PARAM_BLOCK_T; 998 999#ifdef __cplusplus 1000} 1001#endif // __cplusplus 1002 1003#endif // _SCU_BIOS_DEFINITIONS_H_ 1004 1005