mpc85xx.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
5 * Copyright 2006 by Juniper Networks.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: stable/11/sys/powerpc/mpc85xx/mpc85xx.h 330897 2018-03-14 03:19:51Z eadler $
30 */
31
32#ifndef _MPC85XX_H_
33#define _MPC85XX_H_
34
35#include <machine/platformvar.h>
36
37/*
38 * Configuration control and status registers
39 */
40extern vm_offset_t		ccsrbar_va;
41#define CCSRBAR_VA		ccsrbar_va
42#define	OCP85XX_CCSRBAR		(CCSRBAR_VA + 0x0)
43#define	OCP85XX_BPTR		(CCSRBAR_VA + 0x20)
44
45#define	OCP85XX_BSTRH		(CCSRBAR_VA + 0x20)
46#define	OCP85XX_BSTRL		(CCSRBAR_VA + 0x24)
47#define	OCP85XX_BSTAR		(CCSRBAR_VA + 0x28)
48
49#define	OCP85XX_COREDISR	(CCSRBAR_VA + 0xE0094)
50#define	OCP85XX_BRR		(CCSRBAR_VA + 0xE00E4)
51
52/*
53 * Run Control and Power Management registers
54 */
55#define CCSR_CTBENR		(CCSRBAR_VA + 0xE2084)
56#define CCSR_CTBCKSELR		(CCSRBAR_VA + 0xE208C)
57#define CCSR_CTBCHLTCR		(CCSRBAR_VA + 0xE2094)
58
59/*
60 * DDR Memory controller.
61 */
62#define	OCP85XX_DDR1_CS0_CONFIG		(CCSRBAR_VA + 0x8080)
63
64/*
65 * E500 Coherency Module registers
66 */
67#define	OCP85XX_EEBPCR		(CCSRBAR_VA + 0x1010)
68
69/*
70 * Local access registers
71 */
72/* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */
73#define	OCP85XX_LAWBARH(n)	(CCSRBAR_VA + 0xc00 + 0x10 * (n))
74#define	OCP85XX_LAWBARL(n)	(CCSRBAR_VA + 0xc04 + 0x10 * (n))
75#define	OCP85XX_LAWSR_QORIQ(n)	(CCSRBAR_VA + 0xc08 + 0x10 * (n))
76#define	OCP85XX_LAWBAR(n)	(CCSRBAR_VA + 0xc08 + 0x10 * (n))
77#define	OCP85XX_LAWSR_85XX(n)	(CCSRBAR_VA + 0xc10 + 0x10 * (n))
78#define	OCP85XX_LAWSR(n)	(mpc85xx_is_qoriq() ? OCP85XX_LAWSR_QORIQ(n) : \
79				 OCP85XX_LAWSR_85XX(n))
80
81/* Attribute register */
82#define	OCP85XX_ENA_MASK	0x80000000
83#define	OCP85XX_DIS_MASK	0x7fffffff
84
85#define	OCP85XX_TGTIF_LBC_QORIQ	0x1f
86#define	OCP85XX_TGTIF_RAM_INTL_QORIQ	0x14
87#define	OCP85XX_TGTIF_RAM1_QORIQ	0x10
88#define	OCP85XX_TGTIF_RAM2_QORIQ	0x11
89#define	OCP85XX_TGTIF_BMAN		0x18
90#define	OCP85XX_TGTIF_DCSR		0x1D
91#define	OCP85XX_TGTIF_QMAN		0x3C
92#define	OCP85XX_TRGT_SHIFT_QORIQ	20
93
94#define	OCP85XX_TGTIF_LBC_85XX	0x04
95#define	OCP85XX_TGTIF_RAM_INTL_85XX	0x0b
96#define	OCP85XX_TGTIF_RIO_85XX	0x0c
97#define	OCP85XX_TGTIF_RAM1_85XX	0x0f
98#define	OCP85XX_TGTIF_RAM2_85XX	0x16
99
100#define	OCP85XX_TGTIF_LBC	\
101    (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_LBC_QORIQ : OCP85XX_TGTIF_LBC_85XX)
102#define	OCP85XX_TGTIF_RAM_INTL	\
103     (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM_INTL_QORIQ : OCP85XX_TGTIF_RAM_INTL_85XX)
104#define	OCP85XX_TGTIF_RIO	\
105      (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RIO_QORIQ : OCP85XX_TGTIF_RIO_85XX)
106#define	OCP85XX_TGTIF_RAM1	\
107       (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM1_QORIQ : OCP85XX_TGTIF_RAM1_85XX)
108#define	OCP85XX_TGTIF_RAM2	\
109	(mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM2_QORIQ : OCP85XX_TGTIF_RAM2_85XX)
110
111/*
112 * L2 cache registers
113 */
114#define OCP85XX_L2CTL		(CCSRBAR_VA + 0x20000)
115
116/*
117 * L3 CoreNet platform cache (CPC) registers
118 */
119#define	OCP85XX_CPC_CSR0		(CCSRBAR_VA + 0x10000)
120#define	  OCP85XX_CPC_CSR0_CE		  0x80000000
121#define	  OCP85XX_CPC_CSR0_PE		  0x40000000
122#define	  OCP85XX_CPC_CSR0_FI		  0x00200000
123#define	  OCP85XX_CPC_CSR0_WT		  0x00080000
124#define	  OCP85XX_CPC_CSR0_FL		  0x00000800
125#define	  OCP85XX_CPC_CSR0_LFC		  0x00000400
126#define	OCP85XX_CPC_CFG0		(CCSRBAR_VA + 0x10008)
127#define	  OCP85XX_CPC_CFG_SZ_MASK	  0x00003fff
128#define	  OCP85XX_CPC_CFG0_SZ_K(x)	  (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6)
129
130/*
131 * Power-On Reset configuration
132 */
133#define	OCP85XX_PORDEVSR	(CCSRBAR_VA + 0xe000c)
134#define OCP85XX_PORDEVSR_IO_SEL	0x00780000
135#define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
136
137#define	OCP85XX_PORDEVSR2	(CCSRBAR_VA + 0xe0014)
138
139/*
140 * Status Registers.
141 */
142#define	OCP85XX_RSTCR		(CCSRBAR_VA + 0xe00b0)
143
144/*
145 * Run Control/Power Management Registers.
146 */
147#define	OCP85XX_RCPM_CDOZSR	(CCSRBAR_VA + 0xe2004)
148#define	OCP85XX_RCPM_CDOZCR	(CCSRBAR_VA + 0xe200c)
149
150/*
151 * Prototypes.
152 */
153uint32_t ccsr_read4(uintptr_t addr);
154void ccsr_write4(uintptr_t addr, uint32_t val);
155int law_enable(int trgt, uint64_t bar, uint32_t size);
156int law_disable(int trgt, uint64_t bar, uint32_t size);
157int law_getmax(void);
158int law_pci_target(struct resource *, int *, int *);
159
160DECLARE_CLASS(mpc85xx_platform);
161int mpc85xx_attach(platform_t);
162
163void mpc85xx_enable_l3_cache(void);
164void mpc85xx_fix_errata(vm_offset_t);
165void dataloss_erratum_access(vm_offset_t, uint32_t);
166int mpc85xx_is_qoriq(void);
167
168#endif /* _MPC85XX_H_ */
169