at91_usartreg.h revision 331722
1123474Swpaul/*- 2123474Swpaul * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3123474Swpaul * 4123474Swpaul * Redistribution and use in source and binary forms, with or without 5123474Swpaul * modification, are permitted provided that the following conditions 6123474Swpaul * are met: 7123474Swpaul * 1. Redistributions of source code must retain the above copyright 8123474Swpaul * notice, this list of conditions and the following disclaimer. 9123474Swpaul * 2. Redistributions in binary form must reproduce the above copyright 10123474Swpaul * notice, this list of conditions and the following disclaimer in the 11123474Swpaul * documentation and/or other materials provided with the distribution. 12123474Swpaul * 13123474Swpaul * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14123474Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15123474Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16123474Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17123474Swpaul * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18123474Swpaul * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19123474Swpaul * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20123474Swpaul * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21123474Swpaul * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22123474Swpaul * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23123474Swpaul * SUCH DAMAGE. 24123474Swpaul */ 25123474Swpaul 26123474Swpaul/* $FreeBSD: stable/11/sys/arm/at91/at91_usartreg.h 331722 2018-03-29 02:50:57Z eadler $ */ 27123474Swpaul 28123474Swpaul#ifndef AT91USARTREG_H_ 29123474Swpaul#define AT91USARTREG_H_ 30123474Swpaul 31123474Swpaul#define USART_CR 0x00 /* Control register */ 32123474Swpaul#define USART_CR_RSTRX (1UL << 2) /* Reset Receiver */ 33123474Swpaul#define USART_CR_RSTTX (1UL << 3) /* Reset Transmitter */ 34123474Swpaul#define USART_CR_RXEN (1UL << 4) /* Receiver Enable */ 35123474Swpaul#define USART_CR_RXDIS (1UL << 5) /* Receiver Disable */ 36123474Swpaul#define USART_CR_TXEN (1UL << 6) /* Transmitter Enable */ 37123474Swpaul#define USART_CR_TXDIS (1UL << 7) /* Transmitter Disable */ 38123474Swpaul#define USART_CR_RSTSTA (1UL << 8) /* Reset Status Bits */ 39123474Swpaul#define USART_CR_STTBRK (1UL << 9) /* Start Break */ 40123474Swpaul#define USART_CR_STPBRK (1UL << 10) /* Stop Break */ 41123474Swpaul#define USART_CR_STTTO (1UL << 11) /* Start Time-out */ 42123474Swpaul#define USART_CR_SENDA (1UL << 12) /* Send Address */ 43123474Swpaul#define USART_CR_RSTIT (1UL << 13) /* Reset Iterations */ 44123474Swpaul#define USART_CR_RSTNACK (1UL << 14) /* Reset Non Acknowledge */ 45123474Swpaul#define USART_CR_RETTO (1UL << 15) /* Rearm Time-out */ 46123474Swpaul#define USART_CR_DTREN (1UL << 16) /* Data Terminal ready Enable */ 47123474Swpaul#define USART_CR_DTRDIS (1UL << 17) /* Data Terminal ready Disable */ 48123474Swpaul#define USART_CR_RTSEN (1UL << 18) /* Request to Send enable */ 49123474Swpaul#define USART_CR_RTSDIS (1UL << 19) /* Request to Send Disable */ 50123474Swpaul 51123474Swpaul#define USART_MR 0x04 /* Mode register */ 52123474Swpaul#define USART_MR_MODE_NORMAL 0 /* Normal/Async/3-wire rs-232 */ 53123474Swpaul#define USART_MR_MODE_RS485 1 /* RS485 */ 54123474Swpaul#define USART_MR_MODE_HWFLOW 2 /* Hardware flow control/handshake */ 55123474Swpaul#define USART_MR_MODE_MODEM 3 /* Full modem protocol */ 56123474Swpaul#define USART_MR_MODE_ISO7816T0 4 /* ISO7816 T=0 */ 57123474Swpaul#define USART_MR_MODE_ISO7816T1 6 /* ISO7816 T=1 */ 58123474Swpaul#define USART_MR_MODE_IRDA 8 /* IrDA mode */ 59123474Swpaul#define USART_MR_USCLKS_MCK (0U << 4) /* use MCK for baudclock */ 60123474Swpaul#define USART_MR_USCLKS_MCKDIV (1U << 4) /* use MCK/DIV for baudclock */ 61123474Swpaul#define USART_MR_USCLKS_SCK (3U << 4) /* use SCK (ext) for baudclock */ 62123474Swpaul#define USART_MR_CHRL_5BITS (0U << 6) 63123474Swpaul#define USART_MR_CHRL_6BITS (1U << 6) 64123504Swpaul#define USART_MR_CHRL_7BITS (2U << 6) 65123848Swpaul#define USART_MR_CHRL_8BITS (3U << 6) 66124122Swpaul#define USART_MR_SYNC (1U << 8) /* 1 -> sync 0 -> async */ 67124272Swpaul#define USART_MR_PAR_EVEN (0U << 9) 68125377Swpaul#define USART_MR_PAR_ODD (1U << 9) 69124272Swpaul#define USART_MR_PAR_SPACE (2U << 9) 70124272Swpaul#define USART_MR_PAR_MARK (3U << 9) 71124272Swpaul#define USART_MR_PAR_NONE (4U << 9) 72125551Swpaul#define USART_MR_PAR_MULTIDROP (6U << 9) 73123474Swpaul#define USART_MR_NBSTOP_1 (0U << 12) 74123474Swpaul#define USART_MR_NBSTOP_1_5 (1U << 12) 75123474Swpaul#define USART_MR_NBSTOP_2 (2U << 12) 76123474Swpaul#define USART_MR_CHMODE_NORMAL (0U << 14) 77123474Swpaul#define USART_MR_CHMODE_ECHO (1U << 14) 78123474Swpaul#define USART_MR_CHMODE_LOOP (2U << 14) 79123474Swpaul#define USART_MR_CHMODE_REMLOOP (3U << 14) 80124203Swpaul#define USART_MR_MSBF (1U << 16) 81123474Swpaul#define USART_MR_MODE9 (1U << 17) 82123474Swpaul#define USART_MR_CKLO_SCK (1U << 18) 83123474Swpaul#define USART_MR_OVER16 0 84123474Swpaul#define USART_MR_OVER8 (1U << 19) 85123474Swpaul#define USART_MR_INACK (1U << 20) /* Inhibit NACK generation */ 86123474Swpaul#define USART_MR_DSNACK (1U << 21) /* Disable Successive NACK */ 87123474Swpaul#define USART_MR_MAXITERATION(x) ((x) << 24) 88123474Swpaul#define USART_MR_FILTER (1U << 28) /* Filters for Ir lines */ 89123474Swpaul 90123474Swpaul#define USART_IER 0x08 /* Interrupt enable register */ 91123695Swpaul#define USART_IDR 0x0c /* Interrupt disable register */ 92123695Swpaul#define USART_IMR 0x10 /* Interrupt mask register */ 93123695Swpaul#define USART_CSR 0x14 /* Channel status register */ 94123474Swpaul 95123474Swpaul#define USART_CSR_RXRDY (1UL << 0) /* Receiver ready */ 96123474Swpaul#define USART_CSR_TXRDY (1UL << 1) /* Transmitter ready */ 97123474Swpaul#define USART_CSR_RXBRK (1UL << 2) /* Break received */ 98123474Swpaul#define USART_CSR_ENDRX (1UL << 3) /* End of Transfer RX from PDC */ 99123512Swpaul#define USART_CSR_ENDTX (1UL << 4) /* End of Transfer TX from PDC */ 100123474Swpaul#define USART_CSR_OVRE (1UL << 5) /* Overrun error */ 101123474Swpaul#define USART_CSR_FRAME (1UL << 6) /* Framing error */ 102123474Swpaul#define USART_CSR_PARE (1UL << 7) /* Parity Error */ 103123474Swpaul#define USART_CSR_TIMEOUT (1UL << 8) /* Timeout since start-timeout */ 104123474Swpaul#define USART_CSR_TXEMPTY (1UL << 9) /* Transmitter empty */ 105123474Swpaul#define USART_CSR_ITERATION (1UL << 10) /* max repetitions since RSIT */ 106124409Swpaul#define USART_CSR_TXBUFE (1UL << 11) /* Buffer empty from PDC */ 107124272Swpaul#define USART_CSR_RXBUFF (1UL << 12) /* Buffer full from PDC */ 108124409Swpaul#define USART_CSR_NACK (1UL << 13) /* NACK since last RSTNACK */ 109125057Swpaul#define USART_CSR_RIIC (1UL << 16) /* RI delta since last csr read */ 110123474Swpaul#define USART_CSR_DSRIC (1UL << 17) /* DSR delta */ 111124272Swpaul#define USART_CSR_DCDIC (1UL << 18) /* DCD delta */ 112124272Swpaul#define USART_CSR_CTSIC (1UL << 19) /* CTS delta */ 113124272Swpaul#define USART_CSR_RI (1UL << 20) /* RI status */ 114125551Swpaul#define USART_CSR_DSR (1UL << 21) /* DSR status */ 115125551Swpaul#define USART_CSR_DCD (1UL << 22) /* DCD status */ 116123474Swpaul#define USART_CSR_CTS (1UL << 23) /* CTS status */ 117123474Swpaul 118123474Swpaul#define USART_RHR 0x18 /* Receiver holding register */ 119123474Swpaul#define USART_THR 0x1c /* Transmitter holding register */ 120123474Swpaul#define USART_BRGR 0x20 /* Baud rate generator register */ 121123474Swpaul#define USART_RTOR 0x24 /* Receiver time-out register */ 122123474Swpaul#define USART_TTR 0x28 /* Transmitter timeguard register */ 123123474Swpaul/* 0x2c to 0x3c reserved */ 124123474Swpaul#define USART_FDRR 0x40 /* FI DI ratio register */ 125123526Swpaul#define USART_NER 0x44 /* Number of errors register */ 126123526Swpaul/* 0x48 reserved */ 127123526Swpaul#define USART_IFR 0x48 /* IrDA filter register */ 128123526Swpaul 129123474Swpaul#endif /* AT91RM92REG_H_ */ 130123474Swpaul