cs4231.h revision 331722 
1/*	$FreeBSD: stable/11/sys/dev/sound/sbus/cs4231.h 331722 2018-03-29 02:50:57Z eadler $	*/
2/*-
3 * Copyright (c) 1996 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Ken Hornstein and John Kohl.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/**
32 * Register defs for Crystal Semiconductor CS4231 Audio Codec/mixer
33 * chip, used on Gravis UltraSound MAX cards.
34 *
35 * Block diagram:
36 *             +----------------------------------------------------+
37 *             |						    |
38 *             |   +----------------------------------------------+ |
39 *	       |   |mixed in       +-+  		          | |
40 *	       |   +------------>--| |  		          | |
41 *             | mic in            | |			          | |
42 *   Mic --+-->| --------- GAIN ->-| |			          | |
43 *         |   | AUX 1 in          |M|				  | |
44 *   GF1 --)-->| -------------+-->-|U|				  | |
45 *	   |   | Line in      |	   |X|---- GAIN ----------+	  | |
46 *  Line --)-->| ---------+---)-->-| |			  |	  | |
47 *	   |   |	  |   |    | |			  |	  | |
48 *	   |   |	  |   |    +-+		         ADC 	  | |
49 *	   |   |	  |   |      		          | 	  | |
50 *	   |   |	  |   |				  |	  | |
51 *	   |   |	  |   +--- L/M --\		  |	  | | AMP-->
52 *	   |   |	  |   	   	  \		  |	  | |  |
53 *	   |   |	  |   	   	   \	          |	  | |  |
54 *	   |   |	  +---- L/M -------O-->--+--------)-------+-|--+-> line
55 *	   |   |   mono in	       	  /|     |        |	    |
56 *	   +---|-->------------ L/M -----/ |     |        |	    |
57 *	       |   AUX 2 in		   |     |        |	    |
58 *  CD --------|-->------------ L/M -------+    L/M       |	    |
59 *	       |				 |        v	    |
60 *	       |				 |        |	    |
61 *	       |				DAC       |	    |
62 *	       |				 |        |	    |
63 *             +----------------------------------------------------+
64 *	       					 |        |
65 *						 |        |
66 *						 v        v
67 *     	       	       	       	       	       	  Pc BUS (DISK) ???
68 *
69 * Documentation for this chip can be found at:
70 *	http://www.cirrus.com/products/overviews/cs4231.html
71 */
72
73/*
74 * This file was merged from two header files.(ad1848reg.h and cs4231reg.h)
75 * And the suffix AD1848 and SP was changed to CS4231 and CS respectively.
76 */
77/* CS4231 direct registers */
78#define CS4231_IADDR		0x00
79#define CS4231_IDATA		0x01
80#define CS4231_STATUS		0x02
81#define CS4231_PIO		0x03
82
83/* Index address register */
84#define CS_IN_INIT		0x80
85#define MODE_CHANGE_ENABLE	0x40
86#define TRANSFER_DISABLE	0x20
87#define ADDRESS_MASK		0xe0
88
89/* Status bits */
90#define INTERRUPT_STATUS	0x01
91#define PLAYBACK_READY		0x02
92#define PLAYBACK_LEFT		0x04
93/* pbright is not left */
94#define PLAYBACK_UPPER		0x08
95/* bplower is not upper */
96#define SAMPLE_ERROR		0x10
97#define CAPTURE_READY		0x20
98#define CAPTURE_LEFT		0x40
99/* cpright is not left */
100#define CAPTURE_UPPER		0x80
101/* cplower is not upper */
102
103/* CS4231 indirect mapped registers */
104#define CS_LEFT_INPUT_CONTROL	0x00
105#define CS_RIGHT_INPUT_CONTROL	0x01
106#define CS_LEFT_AUX1_CONTROL	0x02
107#define CS_RIGHT_AUX1_CONTROL	0x03
108#define CS_LEFT_AUX2_CONTROL	0x04
109#define CS_RIGHT_AUX2_CONTROL	0x05
110#define CS_LEFT_OUTPUT_CONTROL	0x06
111#define CS_RIGHT_OUTPUT_CONTROL	0x07
112#define CS_CLOCK_DATA_FORMAT	0x08
113#define CS_INTERFACE_CONFIG	0x09
114#define CS_PIN_CONTROL		0x0a
115#define CS_TEST_AND_INIT	0x0b
116#define CS_MISC_INFO		0x0c
117#define CS_DIGITAL_MIX		0x0d
118#define CS_UPPER_BASE_COUNT	0x0e
119#define CS_LOWER_BASE_COUNT	0x0f
120/* CS4231/AD1845 mode2 registers; added to AD1848 registers */
121#define CS_ALT_FEATURE1		0x10
122#define CS_ALT_FEATURE2		0x11
123#define CS_LEFT_LINE_CONTROL	0x12
124#define CS_RIGHT_LINE_CONTROL	0x13
125#define CS_TIMER_LOW		0x14
126#define CS_TIMER_HIGH		0x15
127#define CS_UPPER_FREQUENCY_SEL	0x16
128#define CS_LOWER_FREQUENCY_SEL	0x17
129#define CS_IRQ_STATUS		0x18
130#define CS_VERSION_ID		0x19
131#define CS_MONO_IO_CONTROL	0x1a
132#define CS_POWERDOWN_CONTROL	0x1b
133#define CS_REC_FORMAT		0x1c
134#define CS_XTAL_SELECT		0x1d
135#define CS_UPPER_REC_CNT	0x1e
136#define CS_LOWER_REC_CNT	0x1f
137#define CS_REG_NONE		0xff
138
139#define CS_IN_MASK		0x2f
140#define CS_IN_LINE		0x00
141#define CS_IN_AUX1		0x40
142#define CS_IN_MIC		0x80
143#define CS_IN_DAC		0xc0
144#define CS_MIC_GAIN_ENABLE	0x20
145#define CS_IN_GAIN_MASK		0xf0
146
147/* ADC input control - registers I0 (channel 1,left); I1 (channel 1,right) */
148#define ADC_INPUT_ATTEN_BITS	0x0f
149#define ADC_INPUT_GAIN_ENABLE	0x20
150
151/* Aux input control - registers I2 (channel 1,left); I3 (channel 1,right)
152				 I4 (channel 2,left); I5 (channel 2,right) */
153#define AUX_INPUT_ATTEN_BITS	0x1f
154#define AUX_INPUT_ATTEN_MASK	0xe0
155#define AUX_INPUT_MUTE		0x80
156
157/* Output bits - registers I6,I7*/
158#define OUTPUT_MUTE		0x80
159#define OUTPUT_ATTEN_BITS	0x3f
160#define OUTPUT_ATTEN_MASK	(~OUTPUT_ATTEN_BITS & 0xff)
161
162/* Clock and Data format reg bits (some also Capture Data format) - reg I8 */
163#define CS_CLOCK_DATA_FORMAT_MASK 0x0f
164#define CLOCK_XTAL1		0x00
165#define CLOCK_XTAL2		0x01
166#define CLOCK_FREQ_MASK		0xf1
167#define CS_AFMT_STEREO		0x10
168#define CS_AFMT_U8		0x00
169#define CS_AFMT_MU_LAW		0x20
170#define CS_AFMT_S16_LE		0x40
171#define CS_AFMT_A_LAW		0x60
172#define CS_AFMT_IMA_ADPCM	0xa0
173#define CS_AFMT_S16_BE		0xc0
174
175/* Interface Configuration reg bits - register I9 */
176#define PLAYBACK_ENABLE		0x01
177#define CAPTURE_ENABLE		0x02
178#define DUAL_DMA		0x00
179#define SINGLE_DMA		0x04
180#define AUTO_CAL_ENABLE		0x08
181#define PLAYBACK_PIO_ENABLE	0x40
182#define CAPTURE_PIO_ENABLE	0x80
183
184/* Pin control bits - register I10 */
185#define INTERRUPT_ENABLE	0x02
186#define XCTL0_ENABLE		0x40
187#define XCTL1_ENABLE		0x80
188
189/* Test and init reg bits - register I11 (read-only) */
190#define OVERRANGE_LEFT_MASK	0xfc
191#define OVERRANGE_RIGHT_MASK	0xf3
192#define DATA_REQUEST_STATUS	0x10
193#define AUTO_CAL_IN_PROG	0x20
194#define PLAYBACK_UNDERRUN	0x40
195#define CAPTURE_OVERRUN		0x80
196
197/* Miscellaneous Control reg bits - register I12 */
198#define CS_ID_MASK		0x70
199#define CS_MODE2		0x40
200#define CS_CODEC_ID_MASK	0x0f
201
202/* Digital Mix Control reg bits - register I13 */
203#define DIGITAL_MIX1_ENABLE	0x01
204#define MIX_ATTEN_MASK		0x03
205
206/* Alternate Feature Enable I - register I16 */
207#define CS_DAC_ZERO		0x01
208#define CS_PMC_ENABLE		0x10
209#define CS_CMC_ENABLE		0x20
210#define CS_OUTPUT_LVL		0x80
211
212/* Alternate Feature Enable II - register I17 */
213#define CS_HPF_ENABLE		0x01
214#define DUAL_XTAL_ENABLE	0x02
215
216/* alternate feature status(I24) */
217#define CS_AFS_TI		0x40		/* timer interrupt */
218#define CS_AFS_CI		0x20		/* capture interrupt */
219#define CS_AFS_PI		0x10		/* playback interrupt */
220#define CS_AFS_CU		0x08		/* capture underrun */
221#define CS_AFS_CO		0x04		/* capture overrun */
222#define CS_AFS_PO		0x02		/* playback overrun */
223#define CS_AFS_PU		0x01		/* playback underrun */
224
225/* Version - register I25 */
226#define CS_VERSION_NUMBER	0xe0
227#define CS_VERSION_CHIPID	0x07
228
229/* Miscellaneous Control reg bits */
230#define CS_MODE2		0x40
231
232#define MONO_INPUT_ATTEN_BITS	0x0f
233#define MONO_INPUT_ATTEN_MASK	0xf0
234#define MONO_OUTPUT_MUTE	0x40
235#define MONO_INPUT_MUTE		0x80
236#define MONO_INPUT_MUTE_MASK	0x7f
237
238#define LINE_INPUT_ATTEN_BITS	0x1f
239#define LINE_INPUT_ATTEN_MASK	0xe0
240#define LINE_INPUT_MUTE		0x80
241#define LINE_INPUT_MUTE_MASK	0x7f
242