if_bmreg.h revision 330897
1/*- 2 * Copyright 1991-1998 by Open Software Foundation, Inc. 3 * All Rights Reserved 4 * 5 * Permission to use, copy, modify, and distribute this software and 6 * its documentation for any purpose and without fee is hereby granted, 7 * provided that the above copyright notice appears in all copies and 8 * that both the copyright notice and this permission notice appear in 9 * supporting documentation. 10 * 11 * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 12 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 13 * FOR A PARTICULAR PURPOSE. 14 * 15 * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 16 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 17 * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 18 * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 19 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21/*- 22 * SPDX-License-Identifier: BSD-3-Clause 23 * 24 * Copyright 2003 by Peter Grehan. All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. The name of the author may not be used to endorse or promote products 35 * derived from this software without specific prior written permission. 36 * 37 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 38 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 39 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 40 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 42 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 44 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 46 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 47 * SUCH DAMAGE. 48 * 49 * $FreeBSD: stable/11/sys/dev/bm/if_bmreg.h 330897 2018-03-14 03:19:51Z eadler $ 50 */ 51 52/* 53 * BMAC resource indices 54 */ 55 56#define BM_MAIN_REGISTERS 0 57#define BM_TXDMA_REGISTERS 1 58#define BM_RXDMA_REGISTERS 2 59 60#define BM_MAIN_INTERRUPT 0 61#define BM_TXDMA_INTERRUPT 1 62#define BM_RXDMA_INTERRUPT 2 63 64/* 65 * BMAC/BMAC+ register offsets 66 */ 67 68#define BM_TX_IFC 0x0000 /* interface control */ 69#define BM_TXFIFO_CSR 0x0100 /* TX FIFO control/status */ 70#define BM_TX_THRESH 0x0110 /* TX threshold */ 71#define BM_RXFIFO_CSR 0x0120 /* receive FIFO control/status */ 72#define BM_MEMADD 0x0130 /* unused */ 73#define BM_MEMDATA_HI 0x0140 /* unused */ 74#define BM_MEMDATA_LO 0x0150 /* unused */ 75#define BM_XCVR 0x0160 /* transceiver control register */ 76#define BM_CHIPID 0x0170 /* chip ID */ 77#define BM_MII_CSR 0x0180 /* MII control register */ 78#define BM_SROM_CSR 0x0190 /* unused, OFW provides enet addr */ 79#define BM_TX_PTR 0x01A0 /* unused */ 80#define BM_RX_PTR 0x01B0 /* unused */ 81#define BM_STATUS 0x01C0 /* status register */ 82#define BM_INTR_DISABLE 0x0200 /* interrupt control register */ 83#define BM_TX_RESET 0x0420 /* TX reset */ 84#define BM_TX_CONFIG 0x0430 /* TX config */ 85#define BM_IPG1 0x0440 /* inter-packet gap hi */ 86#define BM_IPG2 0x0450 /* inter-packet gap lo */ 87#define BM_TX_ALIMIT 0x0460 /* TX attempt limit */ 88#define BM_TX_STIME 0x0470 /* TX slot time */ 89#define BM_TX_PASIZE 0x0480 /* TX preamble size */ 90#define BM_TX_PAPAT 0x0490 /* TX preamble pattern */ 91#define BM_TX_SFD 0x04A0 /* TX start-frame delimiter */ 92#define BM_JAMSIZE 0x04B0 /* collision jam size */ 93#define BM_TX_MAXLEN 0x04C0 /* max TX packet length */ 94#define BM_TX_MINLEN 0x04D0 /* min TX packet length */ 95#define BM_TX_PEAKCNT 0x04E0 /* TX peak attempts count */ 96#define BM_TX_DCNT 0x04F0 /* TX defer timer */ 97#define BM_TX_NCCNT 0x0500 /* TX normal collision cnt */ 98#define BM_TX_FCCNT 0x0510 /* TX first collision cnt */ 99#define BM_TX_EXCNT 0x0520 /* TX excess collision cnt */ 100#define BM_TX_LTCNT 0x0530 /* TX late collision cnt */ 101#define BM_TX_RANDSEED 0x0540 /* TX random seed */ 102#define BM_TXSM 0x0550 /* TX state machine */ 103#define BM_RX_RESET 0x0620 /* RX reset */ 104#define BM_RX_CONFIG 0x0630 /* RX config */ 105#define BM_RX_MAXLEN 0x0640 /* max RX packet length */ 106#define BM_RX_MINLEN 0x0650 /* min RX packet length */ 107#define BM_MACADDR2 0x0660 /* MAC address */ 108#define BM_MACADDR1 0x0670 109#define BM_MACADDR0 0x0680 110#define BM_RX_FRCNT 0x0690 /* RX frame count */ 111#define BM_RX_LECNT 0x06A0 /* RX too-long frame count */ 112#define BM_RX_AECNT 0x06B0 /* RX misaligned frame count */ 113#define BM_RX_FECNT 0x06C0 /* RX CRC error count */ 114#define BM_RXSM 0x06D0 /* RX state machine */ 115#define BM_RXCV 0x06E0 /* RX code violations */ 116#define BM_HASHTAB3 0x0700 /* Address hash table */ 117#define BM_HASHTAB2 0x0710 118#define BM_HASHTAB1 0x0720 119#define BM_HASHTAB0 0x0730 120#define BM_AFILTER2 0x0740 /* Address filter */ 121#define BM_AFILTER1 0x0750 122#define BM_AFILTER0 0x0760 123#define BM_AFILTER_MASK 0x0770 124 125/* 126 * MII control register bits 127 */ 128#define BM_MII_CLK 0x0001 /* MDIO clock */ 129#define BM_MII_DATAOUT 0x0002 /* MDIO data out */ 130#define BM_MII_OENABLE 0x0004 /* MDIO output enable */ 131#define BM_MII_DATAIN 0x0008 /* MDIO data in */ 132 133/* 134 * Various flags 135 */ 136 137#define BM_ENABLE 0x0001 138 139#define BM_CRC_ENABLE 0x0100 140#define BM_HASH_FILTER_ENABLE 0x0200 141#define BM_REJECT_OWN_PKTS 0x0800 142#define BM_PROMISC 0x0040 143 144#define BM_TX_FULLDPX 0x0200 145#define BM_TX_IGNORECOLL 0x0040 146 147#define BM_INTR_PKT_RX 0x0001 148#define BM_INTR_PKT_TX 0x0100 149#define BM_INTR_TX_UNDERRUN 0x0200 150 151#define BM_INTR_NORMAL ~(BM_INTR_PKT_TX | BM_INTR_TX_UNDERRUN) 152#define BM_INTR_NONE 0xffff 153 154/* 155 * register space access macros 156 */ 157#define CSR_WRITE_4(sc, reg, val) \ 158 bus_write_4(sc->sc_memr, reg, val) 159#define CSR_WRITE_2(sc, reg, val) \ 160 bus_write_2(sc->sc_memr, reg, val) 161#define CSR_WRITE_1(sc, reg, val) \ 162 bus_write_1(sc->sc_memr, reg, val) 163 164#define CSR_READ_4(sc, reg) \ 165 bus_read_4(sc->sc_memr, reg) 166#define CSR_READ_2(sc, reg) \ 167 bus_read_2(sc->sc_memr, reg) 168#define CSR_READ_1(sc, reg) \ 169 bus_read_1(sc->sc_memr, reg) 170 171#define CSR_BARRIER(sc, reg, length, flags) \ 172 bus_barrier(sc->sc_memr, reg, length, flags) 173