arswitch_phy.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011-2012 Stefan Bethke. 5 * Copyright (c) 2012 Adrian Chadd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/dev/etherswitch/arswitch/arswitch_phy.c 330897 2018-03-14 03:19:51Z eadler $ 30 */ 31 32#include <sys/param.h> 33#include <sys/bus.h> 34#include <sys/errno.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/module.h> 38#include <sys/mutex.h> 39#include <sys/socket.h> 40#include <sys/sockio.h> 41#include <sys/sysctl.h> 42#include <sys/systm.h> 43 44#include <net/if.h> 45#include <net/if_media.h> 46 47#include <machine/bus.h> 48#include <dev/iicbus/iic.h> 49#include <dev/iicbus/iiconf.h> 50#include <dev/iicbus/iicbus.h> 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53#include <dev/mdio/mdio.h> 54 55#include <dev/etherswitch/etherswitch.h> 56 57#include <dev/etherswitch/arswitch/arswitchreg.h> 58#include <dev/etherswitch/arswitch/arswitchvar.h> 59 60#include <dev/etherswitch/arswitch/arswitch_reg.h> 61#include <dev/etherswitch/arswitch/arswitch_phy.h> 62 63#include "mdio_if.h" 64#include "miibus_if.h" 65#include "etherswitch_if.h" 66 67#if defined(DEBUG) 68static SYSCTL_NODE(_debug, OID_AUTO, arswitch, CTLFLAG_RD, 0, "arswitch"); 69#endif 70 71/* 72 * Access PHYs integrated into the switch by going direct 73 * to the PHY space itself, rather than through the switch 74 * MDIO register. 75 */ 76int 77arswitch_readphy_external(device_t dev, int phy, int reg) 78{ 79 int ret; 80 struct arswitch_softc *sc; 81 82 sc = device_get_softc(dev); 83 84 ARSWITCH_LOCK(sc); 85 ret = (MDIO_READREG(device_get_parent(dev), phy, reg)); 86 ARSWITCH_UNLOCK(sc); 87 88 return (ret); 89} 90 91int 92arswitch_writephy_external(device_t dev, int phy, int reg, int data) 93{ 94 struct arswitch_softc *sc; 95 96 sc = device_get_softc(dev); 97 98 ARSWITCH_LOCK(sc); 99 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 100 reg, data); 101 ARSWITCH_UNLOCK(sc); 102 103 return (0); 104} 105 106/* 107 * Access PHYs integrated into the switch chip through the switch's MDIO 108 * control register. 109 */ 110int 111arswitch_readphy_internal(device_t dev, int phy, int reg) 112{ 113 struct arswitch_softc *sc; 114 uint32_t data = 0, ctrl; 115 int err, timeout; 116 uint32_t a; 117 118 sc = device_get_softc(dev); 119 ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); 120 121 if (phy < 0 || phy >= 32) 122 return (ENXIO); 123 if (reg < 0 || reg >= 32) 124 return (ENXIO); 125 126 if (AR8X16_IS_SWITCH(sc, AR8327)) 127 a = AR8327_REG_MDIO_CTRL; 128 else 129 a = AR8X16_REG_MDIO_CTRL; 130 131 ARSWITCH_LOCK(sc); 132 err = arswitch_writereg_msb(dev, a, 133 AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN | 134 AR8X16_MDIO_CTRL_CMD_READ | 135 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) | 136 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT)); 137 DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg); 138 if (err != 0) 139 goto fail; 140 for (timeout = 100; timeout--; ) { 141 ctrl = arswitch_readreg_msb(dev, a); 142 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0) 143 break; 144 } 145 if (timeout < 0) { 146 DPRINTF(dev, "arswitch_readphy(): phy=%d.%02x; timeout=%d\n", phy, reg, timeout); 147 goto fail; 148 } 149 data = arswitch_readreg_lsb(dev, a) & 150 AR8X16_MDIO_CTRL_DATA_MASK; 151 ARSWITCH_UNLOCK(sc); 152 return (data); 153 154fail: 155 ARSWITCH_UNLOCK(sc); 156 return (-1); 157} 158 159int 160arswitch_writephy_internal(device_t dev, int phy, int reg, int data) 161{ 162 struct arswitch_softc *sc; 163 uint32_t ctrl; 164 int err, timeout; 165 uint32_t a; 166 167 sc = device_get_softc(dev); 168 ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); 169 170 if (reg < 0 || reg >= 32) 171 return (ENXIO); 172 173 if (AR8X16_IS_SWITCH(sc, AR8327)) 174 a = AR8327_REG_MDIO_CTRL; 175 else 176 a = AR8X16_REG_MDIO_CTRL; 177 178 ARSWITCH_LOCK(sc); 179 err = arswitch_writereg(dev, a, 180 AR8X16_MDIO_CTRL_BUSY | 181 AR8X16_MDIO_CTRL_MASTER_EN | 182 AR8X16_MDIO_CTRL_CMD_WRITE | 183 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) | 184 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT) | 185 (data & AR8X16_MDIO_CTRL_DATA_MASK)); 186 if (err != 0) 187 goto out; 188 for (timeout = 100; timeout--; ) { 189 ctrl = arswitch_readreg(dev, a); 190 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0) 191 break; 192 } 193 if (timeout < 0) 194 err = EIO; 195out: 196 DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg); 197 ARSWITCH_UNLOCK(sc); 198 return (err); 199} 200