if_axgereg.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013-2014 Kevin Lo
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: stable/11/sys/dev/usb/net/if_axgereg.h 330897 2018-03-14 03:19:51Z eadler $
29 */
30
31#define	AXGE_ACCESS_MAC			0x01
32#define	AXGE_ACCESS_PHY			0x02
33#define	AXGE_ACCESS_WAKEUP		0x03
34#define	AXGE_ACCESS_EEPROM		0x04
35#define	AXGE_ACCESS_EFUSE		0x05
36#define	AXGE_RELOAD_EEPROM_EFUSE	0x06
37#define	AXGE_WRITE_EFUSE_EN		0x09
38#define	AXGE_WRITE_EFUSE_DIS		0x0A
39#define	AXGE_ACCESS_MFAB		0x10
40
41/* Physical link status register */
42#define	AXGE_PLSR			0x02
43#define	PLSR_USB_FS			0x01
44#define	PLSR_USB_HS			0x02
45#define	PLSR_USB_SS			0x04
46
47/* EEPROM address register */
48#define	AXGE_EAR			0x07
49
50/* EEPROM data low register */
51#define	AXGE_EDLR			0x08
52
53/* EEPROM data high register */
54#define	AXGE_EDHR			0x09
55
56/* EEPROM command register */
57#define	AXGE_ECR			0x0a
58
59/* Rx control register */
60#define	AXGE_RCR			0x0b
61#define	RCR_STOP			0x0000
62#define	RCR_PRO				0x0001
63#define	RCR_AMALL			0x0002
64#define	RCR_AB				0x0008
65#define	RCR_AM				0x0010
66#define	RCR_AP				0x0020
67#define	RCR_SO				0x0080
68#define	RCR_DROP_CRCE			0x0100
69#define	RCR_IPE				0x0200
70#define	RCR_TX_CRC_PAD			0x0400
71
72/* Node id register */
73#define	AXGE_NIDR			0x10
74
75/* Multicast filter array */
76#define	AXGE_MFA			0x16
77
78/* Medium status register */
79#define	AXGE_MSR			0x22
80#define	MSR_GM				0x0001
81#define	MSR_FD				0x0002
82#define	MSR_EN_125MHZ			0x0008
83#define	MSR_RFC				0x0010
84#define	MSR_TFC				0x0020
85#define	MSR_RE				0x0100
86#define	MSR_PS				0x0200
87
88/* Monitor mode status register */
89#define	AXGE_MMSR			0x24
90#define	MMSR_RWLC			0x02
91#define	MMSR_RWMP			0x04
92#define	MMSR_RWWF			0x08
93#define	MMSR_RW_FLAG			0x10
94#define	MMSR_PME_POL			0x20
95#define	MMSR_PME_TYPE			0x40
96#define	MMSR_PME_IND			0x80
97
98/* GPIO control/status register */
99#define	AXGE_GPIOCR			0x25
100
101/* Ethernet PHY power & reset control register */
102#define	AXGE_EPPRCR			0x26
103#define	EPPRCR_BZ			0x0010
104#define	EPPRCR_IPRL			0x0020
105#define	EPPRCR_AUTODETACH		0x1000
106
107#define	AXGE_RX_BULKIN_QCTRL		0x2e
108
109#define	AXGE_CLK_SELECT			0x33
110#define	AXGE_CLK_SELECT_BCS		0x01
111#define	AXGE_CLK_SELECT_ACS		0x02
112#define	AXGE_CLK_SELECT_ACSREQ		0x10
113#define	AXGE_CLK_SELECT_ULR		0x08
114
115/* COE Rx control register */
116#define	AXGE_CRCR			0x34
117#define	CRCR_IP				0x01
118#define	CRCR_TCP			0x02
119#define	CRCR_UDP			0x04
120#define	CRCR_ICMP			0x08
121#define	CRCR_IGMP			0x10
122#define	CRCR_TCPV6			0x20
123#define	CRCR_UDPV6			0x40
124#define	CRCR_ICMPV6			0x80
125
126/* COE Tx control register */
127#define	AXGE_CTCR			0x35
128#define	CTCR_IP				0x01
129#define	CTCR_TCP			0x02
130#define	CTCR_UDP			0x04
131#define	CTCR_ICMP			0x08
132#define	CTCR_IGMP			0x10
133#define	CTCR_TCPV6			0x20
134#define	CTCR_UDPV6			0x40
135#define	CTCR_ICMPV6			0x80
136
137/* Pause water level high register */
138#define	AXGE_PWLHR			0x54
139
140/* Pause water level low register */
141#define	AXGE_PWLLR			0x55
142
143#define	AXGE_CONFIG_IDX			0	/* config number 1 */
144#define	AXGE_IFACE_IDX			0
145
146#define	AXGE_RXHDR_L4_TYPE_MASK		0x1c
147#define	AXGE_RXHDR_L4CSUM_ERR		1
148#define	AXGE_RXHDR_L3CSUM_ERR		2
149#define	AXGE_RXHDR_L4_TYPE_UDP		4
150#define	AXGE_RXHDR_L4_TYPE_TCP		16
151#define	AXGE_RXHDR_CRC_ERR		0x20000000
152#define	AXGE_RXHDR_DROP_ERR		0x80000000
153
154#define	GET_MII(sc)		uether_getmii(&(sc)->sc_ue)
155
156/* The interrupt endpoint is currently unused by the ASIX part. */
157enum {
158	AXGE_BULK_DT_WR,
159	AXGE_BULK_DT_RD,
160	AXGE_N_TRANSFER,
161};
162
163struct axge_softc {
164	struct usb_ether	sc_ue;
165	struct mtx		sc_mtx;
166	struct usb_xfer		*sc_xfer[AXGE_N_TRANSFER];
167	int			sc_phyno;
168
169	int			sc_flags;
170#define	AXGE_FLAG_LINK		0x0001	/* got a link */
171};
172
173#define	AXGE_LOCK(_sc)			mtx_lock(&(_sc)->sc_mtx)
174#define	AXGE_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
175#define	AXGE_LOCK_ASSERT(_sc, t)	mtx_assert(&(_sc)->sc_mtx, t)
176