siena_phy.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/11/sys/dev/sfxge/common/siena_phy.c 330897 2018-03-14 03:19:51Z eadler $"); 35 36#include "efx.h" 37#include "efx_impl.h" 38 39#if EFSYS_OPT_SIENA 40 41static void 42siena_phy_decode_cap( 43 __in uint32_t mcdi_cap, 44 __out uint32_t *maskp) 45{ 46 uint32_t mask; 47 48 mask = 0; 49 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN)) 50 mask |= (1 << EFX_PHY_CAP_10HDX); 51 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN)) 52 mask |= (1 << EFX_PHY_CAP_10FDX); 53 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN)) 54 mask |= (1 << EFX_PHY_CAP_100HDX); 55 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN)) 56 mask |= (1 << EFX_PHY_CAP_100FDX); 57 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN)) 58 mask |= (1 << EFX_PHY_CAP_1000HDX); 59 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) 60 mask |= (1 << EFX_PHY_CAP_1000FDX); 61 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) 62 mask |= (1 << EFX_PHY_CAP_10000FDX); 63 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) 64 mask |= (1 << EFX_PHY_CAP_PAUSE); 65 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) 66 mask |= (1 << EFX_PHY_CAP_ASYM); 67 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 68 mask |= (1 << EFX_PHY_CAP_AN); 69 70 *maskp = mask; 71} 72 73static void 74siena_phy_decode_link_mode( 75 __in efx_nic_t *enp, 76 __in uint32_t link_flags, 77 __in unsigned int speed, 78 __in unsigned int fcntl, 79 __out efx_link_mode_t *link_modep, 80 __out unsigned int *fcntlp) 81{ 82 boolean_t fd = !!(link_flags & 83 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN)); 84 boolean_t up = !!(link_flags & 85 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN)); 86 87 _NOTE(ARGUNUSED(enp)) 88 89 if (!up) 90 *link_modep = EFX_LINK_DOWN; 91 else if (speed == 10000 && fd) 92 *link_modep = EFX_LINK_10000FDX; 93 else if (speed == 1000) 94 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX; 95 else if (speed == 100) 96 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX; 97 else if (speed == 10) 98 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX; 99 else 100 *link_modep = EFX_LINK_UNKNOWN; 101 102 if (fcntl == MC_CMD_FCNTL_OFF) 103 *fcntlp = 0; 104 else if (fcntl == MC_CMD_FCNTL_RESPOND) 105 *fcntlp = EFX_FCNTL_RESPOND; 106 else if (fcntl == MC_CMD_FCNTL_BIDIR) 107 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 108 else { 109 EFSYS_PROBE1(mc_pcol_error, int, fcntl); 110 *fcntlp = 0; 111 } 112} 113 114 void 115siena_phy_link_ev( 116 __in efx_nic_t *enp, 117 __in efx_qword_t *eqp, 118 __out efx_link_mode_t *link_modep) 119{ 120 efx_port_t *epp = &(enp->en_port); 121 unsigned int link_flags; 122 unsigned int speed; 123 unsigned int fcntl; 124 efx_link_mode_t link_mode; 125 uint32_t lp_cap_mask; 126 127 /* 128 * Convert the LINKCHANGE speed enumeration into mbit/s, in the 129 * same way as GET_LINK encodes the speed 130 */ 131 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) { 132 case MCDI_EVENT_LINKCHANGE_SPEED_100M: 133 speed = 100; 134 break; 135 case MCDI_EVENT_LINKCHANGE_SPEED_1G: 136 speed = 1000; 137 break; 138 case MCDI_EVENT_LINKCHANGE_SPEED_10G: 139 speed = 10000; 140 break; 141 default: 142 speed = 0; 143 break; 144 } 145 146 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS); 147 siena_phy_decode_link_mode(enp, link_flags, speed, 148 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL), 149 &link_mode, &fcntl); 150 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP), 151 &lp_cap_mask); 152 153 /* 154 * It's safe to update ep_lp_cap_mask without the driver's port lock 155 * because presumably any concurrently running efx_port_poll() is 156 * only going to arrive at the same value. 157 * 158 * ep_fcntl has two meanings. It's either the link common fcntl 159 * (if the PHY supports AN), or it's the forced link state. If 160 * the former, it's safe to update the value for the same reason as 161 * for ep_lp_cap_mask. If the latter, then just ignore the value, 162 * because we can race with efx_mac_fcntl_set(). 163 */ 164 epp->ep_lp_cap_mask = lp_cap_mask; 165 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) 166 epp->ep_fcntl = fcntl; 167 168 *link_modep = link_mode; 169} 170 171 __checkReturn efx_rc_t 172siena_phy_power( 173 __in efx_nic_t *enp, 174 __in boolean_t power) 175{ 176 efx_rc_t rc; 177 178 if (!power) 179 return (0); 180 181 /* Check if the PHY is a zombie */ 182 if ((rc = siena_phy_verify(enp)) != 0) 183 goto fail1; 184 185 enp->en_reset_flags |= EFX_RESET_PHY; 186 187 return (0); 188 189fail1: 190 EFSYS_PROBE1(fail1, efx_rc_t, rc); 191 192 return (rc); 193} 194 195 __checkReturn efx_rc_t 196siena_phy_get_link( 197 __in efx_nic_t *enp, 198 __out siena_link_state_t *slsp) 199{ 200 efx_mcdi_req_t req; 201 uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN, 202 MC_CMD_GET_LINK_OUT_LEN)]; 203 efx_rc_t rc; 204 205 (void) memset(payload, 0, sizeof (payload)); 206 req.emr_cmd = MC_CMD_GET_LINK; 207 req.emr_in_buf = payload; 208 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN; 209 req.emr_out_buf = payload; 210 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN; 211 212 efx_mcdi_execute(enp, &req); 213 214 if (req.emr_rc != 0) { 215 rc = req.emr_rc; 216 goto fail1; 217 } 218 219 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) { 220 rc = EMSGSIZE; 221 goto fail2; 222 } 223 224 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP), 225 &slsp->sls_adv_cap_mask); 226 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP), 227 &slsp->sls_lp_cap_mask); 228 229 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS), 230 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED), 231 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL), 232 &slsp->sls_link_mode, &slsp->sls_fcntl); 233 234#if EFSYS_OPT_LOOPBACK 235 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */ 236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); 237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); 238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); 239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); 240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); 241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); 242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); 243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); 244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); 245 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); 246 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR); 247 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR); 248 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR); 249 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR); 250 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY); 251 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS); 252 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS); 253 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD); 254 255 slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE); 256#endif /* EFSYS_OPT_LOOPBACK */ 257 258 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0; 259 260 return (0); 261 262fail2: 263 EFSYS_PROBE(fail2); 264fail1: 265 EFSYS_PROBE1(fail1, efx_rc_t, rc); 266 267 return (rc); 268} 269 270 __checkReturn efx_rc_t 271siena_phy_reconfigure( 272 __in efx_nic_t *enp) 273{ 274 efx_port_t *epp = &(enp->en_port); 275 efx_mcdi_req_t req; 276 uint8_t payload[MAX(MAX(MC_CMD_SET_ID_LED_IN_LEN, 277 MC_CMD_SET_ID_LED_OUT_LEN), 278 MAX(MC_CMD_SET_LINK_IN_LEN, 279 MC_CMD_SET_LINK_OUT_LEN))]; 280 uint32_t cap_mask; 281 unsigned int led_mode; 282 unsigned int speed; 283 efx_rc_t rc; 284 285 (void) memset(payload, 0, sizeof (payload)); 286 req.emr_cmd = MC_CMD_SET_LINK; 287 req.emr_in_buf = payload; 288 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN; 289 req.emr_out_buf = payload; 290 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN; 291 292 cap_mask = epp->ep_adv_cap_mask; 293 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP, 294 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1, 295 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1, 296 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1, 297 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1, 298 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1, 299 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1, 300 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1, 301 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1, 302 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1, 303 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1); 304 305#if EFSYS_OPT_LOOPBACK 306 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, 307 epp->ep_loopback_type); 308 switch (epp->ep_loopback_link_mode) { 309 case EFX_LINK_100FDX: 310 speed = 100; 311 break; 312 case EFX_LINK_1000FDX: 313 speed = 1000; 314 break; 315 case EFX_LINK_10000FDX: 316 speed = 10000; 317 break; 318 default: 319 speed = 0; 320 } 321#else 322 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE); 323 speed = 0; 324#endif /* EFSYS_OPT_LOOPBACK */ 325 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed); 326 327#if EFSYS_OPT_PHY_FLAGS 328 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags); 329#else 330 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0); 331#endif /* EFSYS_OPT_PHY_FLAGS */ 332 333 efx_mcdi_execute(enp, &req); 334 335 if (req.emr_rc != 0) { 336 rc = req.emr_rc; 337 goto fail1; 338 } 339 340 /* And set the blink mode */ 341 (void) memset(payload, 0, sizeof (payload)); 342 req.emr_cmd = MC_CMD_SET_ID_LED; 343 req.emr_in_buf = payload; 344 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN; 345 req.emr_out_buf = payload; 346 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN; 347 348#if EFSYS_OPT_PHY_LED_CONTROL 349 switch (epp->ep_phy_led_mode) { 350 case EFX_PHY_LED_DEFAULT: 351 led_mode = MC_CMD_LED_DEFAULT; 352 break; 353 case EFX_PHY_LED_OFF: 354 led_mode = MC_CMD_LED_OFF; 355 break; 356 case EFX_PHY_LED_ON: 357 led_mode = MC_CMD_LED_ON; 358 break; 359 default: 360 EFSYS_ASSERT(0); 361 led_mode = MC_CMD_LED_DEFAULT; 362 } 363 364 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode); 365#else 366 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT); 367#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 368 369 efx_mcdi_execute(enp, &req); 370 371 if (req.emr_rc != 0) { 372 rc = req.emr_rc; 373 goto fail2; 374 } 375 376 return (0); 377 378fail2: 379 EFSYS_PROBE(fail2); 380fail1: 381 EFSYS_PROBE1(fail1, efx_rc_t, rc); 382 383 return (rc); 384} 385 386 __checkReturn efx_rc_t 387siena_phy_verify( 388 __in efx_nic_t *enp) 389{ 390 efx_mcdi_req_t req; 391 uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN, 392 MC_CMD_GET_PHY_STATE_OUT_LEN)]; 393 uint32_t state; 394 efx_rc_t rc; 395 396 (void) memset(payload, 0, sizeof (payload)); 397 req.emr_cmd = MC_CMD_GET_PHY_STATE; 398 req.emr_in_buf = payload; 399 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN; 400 req.emr_out_buf = payload; 401 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN; 402 403 efx_mcdi_execute(enp, &req); 404 405 if (req.emr_rc != 0) { 406 rc = req.emr_rc; 407 goto fail1; 408 } 409 410 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) { 411 rc = EMSGSIZE; 412 goto fail2; 413 } 414 415 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE); 416 if (state != MC_CMD_PHY_STATE_OK) { 417 if (state != MC_CMD_PHY_STATE_ZOMBIE) 418 EFSYS_PROBE1(mc_pcol_error, int, state); 419 rc = ENOTACTIVE; 420 goto fail3; 421 } 422 423 return (0); 424 425fail3: 426 EFSYS_PROBE(fail3); 427fail2: 428 EFSYS_PROBE(fail2); 429fail1: 430 EFSYS_PROBE1(fail1, efx_rc_t, rc); 431 432 return (rc); 433} 434 435 __checkReturn efx_rc_t 436siena_phy_oui_get( 437 __in efx_nic_t *enp, 438 __out uint32_t *ouip) 439{ 440 _NOTE(ARGUNUSED(enp, ouip)) 441 442 return (ENOTSUP); 443} 444 445#if EFSYS_OPT_PHY_STATS 446 447#define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 448 _mc_record, _efx_record) \ 449 if ((_vmask) & (1ULL << (_mc_record))) { \ 450 (_smask) |= (1ULL << (_efx_record)); \ 451 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \ 452 efx_dword_t dword; \ 453 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\ 454 (_stat)[_efx_record] = \ 455 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \ 456 } \ 457 } 458 459#define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \ 460 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 461 MC_CMD_ ## _record, \ 462 EFX_PHY_STAT_ ## _record) 463 464 void 465siena_phy_decode_stats( 466 __in efx_nic_t *enp, 467 __in uint32_t vmask, 468 __in_opt efsys_mem_t *esmp, 469 __out_opt uint64_t *smaskp, 470 __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat) 471{ 472 uint64_t smask = 0; 473 474 _NOTE(ARGUNUSED(enp)) 475 476 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI); 477 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP); 478 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT); 479 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT); 480 481 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) { 482 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) | 483 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) | 484 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) | 485 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D)); 486 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 487 efx_dword_t dword; 488 uint32_t sig; 489 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL, 490 &dword); 491 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 492 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1; 493 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1; 494 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1; 495 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1; 496 } 497 } 498 499 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A, 500 EFX_PHY_STAT_SNR_A); 501 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B, 502 EFX_PHY_STAT_SNR_B); 503 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C, 504 EFX_PHY_STAT_SNR_C); 505 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D, 506 EFX_PHY_STAT_SNR_D); 507 508 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP); 509 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT); 510 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT); 511 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER); 512 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS); 513 514 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP, 515 EFX_PHY_STAT_PHY_XS_LINK_UP); 516 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT, 517 EFX_PHY_STAT_PHY_XS_RX_FAULT); 518 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT, 519 EFX_PHY_STAT_PHY_XS_TX_FAULT); 520 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN, 521 EFX_PHY_STAT_PHY_XS_ALIGN); 522 523 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) { 524 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) | 525 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) | 526 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) | 527 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D)); 528 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 529 efx_dword_t dword; 530 uint32_t sync; 531 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword); 532 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 533 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1; 534 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1; 535 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1; 536 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1; 537 } 538 } 539 540 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP); 541 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE); 542 543 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP, 544 EFX_PHY_STAT_CL22EXT_LINK_UP); 545 546 if (smaskp != NULL) 547 *smaskp = smask; 548} 549 550 __checkReturn efx_rc_t 551siena_phy_stats_update( 552 __in efx_nic_t *enp, 553 __in efsys_mem_t *esmp, 554 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) 555{ 556 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 557 uint32_t vmask = encp->enc_mcdi_phy_stat_mask; 558 uint64_t smask; 559 efx_mcdi_req_t req; 560 uint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN, 561 MC_CMD_PHY_STATS_OUT_DMA_LEN)]; 562 efx_rc_t rc; 563 564 (void) memset(payload, 0, sizeof (payload)); 565 req.emr_cmd = MC_CMD_PHY_STATS; 566 req.emr_in_buf = payload; 567 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN; 568 req.emr_out_buf = payload; 569 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN; 570 571 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO, 572 EFSYS_MEM_ADDR(esmp) & 0xffffffff); 573 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI, 574 EFSYS_MEM_ADDR(esmp) >> 32); 575 576 efx_mcdi_execute(enp, &req); 577 578 if (req.emr_rc != 0) { 579 rc = req.emr_rc; 580 goto fail1; 581 } 582 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN); 583 584 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat); 585 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask); 586 587 return (0); 588 589fail1: 590 EFSYS_PROBE1(fail1, efx_rc_t, rc); 591 592 return (0); 593} 594 595#endif /* EFSYS_OPT_PHY_STATS */ 596 597#if EFSYS_OPT_BIST 598 599 __checkReturn efx_rc_t 600siena_phy_bist_start( 601 __in efx_nic_t *enp, 602 __in efx_bist_type_t type) 603{ 604 efx_rc_t rc; 605 606 if ((rc = efx_mcdi_bist_start(enp, type)) != 0) 607 goto fail1; 608 609 return (0); 610 611fail1: 612 EFSYS_PROBE1(fail1, efx_rc_t, rc); 613 614 return (rc); 615} 616 617static __checkReturn unsigned long 618siena_phy_sft9001_bist_status( 619 __in uint16_t code) 620{ 621 switch (code) { 622 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY: 623 return (EFX_PHY_CABLE_STATUS_BUSY); 624 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT: 625 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT); 626 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT: 627 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT); 628 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN: 629 return (EFX_PHY_CABLE_STATUS_OPEN); 630 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK: 631 return (EFX_PHY_CABLE_STATUS_OK); 632 default: 633 return (EFX_PHY_CABLE_STATUS_INVALID); 634 } 635} 636 637 __checkReturn efx_rc_t 638siena_phy_bist_poll( 639 __in efx_nic_t *enp, 640 __in efx_bist_type_t type, 641 __out efx_bist_result_t *resultp, 642 __out_opt __drv_when(count > 0, __notnull) 643 uint32_t *value_maskp, 644 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 645 unsigned long *valuesp, 646 __in size_t count) 647{ 648 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 649 uint8_t payload[MAX(MC_CMD_POLL_BIST_IN_LEN, 650 MCDI_CTL_SDU_LEN_MAX)]; 651 uint32_t value_mask = 0; 652 efx_mcdi_req_t req; 653 uint32_t result; 654 efx_rc_t rc; 655 656 (void) memset(payload, 0, sizeof (payload)); 657 req.emr_cmd = MC_CMD_POLL_BIST; 658 req.emr_in_buf = payload; 659 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN; 660 req.emr_out_buf = payload; 661 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX; 662 663 efx_mcdi_execute(enp, &req); 664 665 if (req.emr_rc != 0) { 666 rc = req.emr_rc; 667 goto fail1; 668 } 669 670 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) { 671 rc = EMSGSIZE; 672 goto fail2; 673 } 674 675 if (count > 0) 676 (void) memset(valuesp, '\0', count * sizeof (unsigned long)); 677 678 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT); 679 680 /* Extract PHY specific results */ 681 if (result == MC_CMD_POLL_BIST_PASSED && 682 encp->enc_phy_type == EFX_PHY_SFT9001B && 683 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN && 684 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT || 685 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) { 686 uint16_t word; 687 688 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) { 689 if (valuesp != NULL) 690 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] = 691 MCDI_OUT_DWORD(req, 692 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A); 693 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A); 694 } 695 696 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) { 697 if (valuesp != NULL) 698 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] = 699 MCDI_OUT_DWORD(req, 700 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B); 701 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B); 702 } 703 704 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) { 705 if (valuesp != NULL) 706 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] = 707 MCDI_OUT_DWORD(req, 708 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C); 709 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C); 710 } 711 712 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) { 713 if (valuesp != NULL) 714 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] = 715 MCDI_OUT_DWORD(req, 716 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D); 717 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D); 718 } 719 720 if (count > EFX_BIST_PHY_CABLE_STATUS_A) { 721 if (valuesp != NULL) { 722 word = MCDI_OUT_WORD(req, 723 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A); 724 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] = 725 siena_phy_sft9001_bist_status(word); 726 } 727 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A); 728 } 729 730 if (count > EFX_BIST_PHY_CABLE_STATUS_B) { 731 if (valuesp != NULL) { 732 word = MCDI_OUT_WORD(req, 733 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B); 734 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] = 735 siena_phy_sft9001_bist_status(word); 736 } 737 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B); 738 } 739 740 if (count > EFX_BIST_PHY_CABLE_STATUS_C) { 741 if (valuesp != NULL) { 742 word = MCDI_OUT_WORD(req, 743 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C); 744 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] = 745 siena_phy_sft9001_bist_status(word); 746 } 747 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C); 748 } 749 750 if (count > EFX_BIST_PHY_CABLE_STATUS_D) { 751 if (valuesp != NULL) { 752 word = MCDI_OUT_WORD(req, 753 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D); 754 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] = 755 siena_phy_sft9001_bist_status(word); 756 } 757 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D); 758 } 759 760 } else if (result == MC_CMD_POLL_BIST_FAILED && 761 encp->enc_phy_type == EFX_PHY_QLX111V && 762 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN && 763 count > EFX_BIST_FAULT_CODE) { 764 if (valuesp != NULL) 765 valuesp[EFX_BIST_FAULT_CODE] = 766 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST); 767 value_mask |= 1 << EFX_BIST_FAULT_CODE; 768 } 769 770 if (value_maskp != NULL) 771 *value_maskp = value_mask; 772 773 EFSYS_ASSERT(resultp != NULL); 774 if (result == MC_CMD_POLL_BIST_RUNNING) 775 *resultp = EFX_BIST_RESULT_RUNNING; 776 else if (result == MC_CMD_POLL_BIST_PASSED) 777 *resultp = EFX_BIST_RESULT_PASSED; 778 else 779 *resultp = EFX_BIST_RESULT_FAILED; 780 781 return (0); 782 783fail2: 784 EFSYS_PROBE(fail2); 785fail1: 786 EFSYS_PROBE1(fail1, efx_rc_t, rc); 787 788 return (rc); 789} 790 791 void 792siena_phy_bist_stop( 793 __in efx_nic_t *enp, 794 __in efx_bist_type_t type) 795{ 796 /* There is no way to stop BIST on Siena */ 797 _NOTE(ARGUNUSED(enp, type)) 798} 799 800#endif /* EFSYS_OPT_BIST */ 801 802#endif /* EFSYS_OPT_SIENA */ 803