if_alc.c revision 331722
1/*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/sys/dev/alc/if_alc.c 331722 2018-03-29 02:50:57Z eadler $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/mbuf.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44#include <sys/queue.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/taskqueue.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_llc.h> 57#include <net/if_media.h> 58#include <net/if_types.h> 59#include <net/if_vlan_var.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/ip.h> 64#include <netinet/tcp.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <machine/bus.h> 73#include <machine/in_cksum.h> 74 75#include <dev/alc/if_alcreg.h> 76#include <dev/alc/if_alcvar.h> 77 78/* "device miibus" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80#undef ALC_USE_CUSTOM_CSUM 81 82#ifdef ALC_USE_CUSTOM_CSUM 83#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84#else 85#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86#endif 87 88MODULE_DEPEND(alc, pci, 1, 1, 1); 89MODULE_DEPEND(alc, ether, 1, 1, 1); 90MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92/* Tunables. */ 93static int msi_disable = 0; 94static int msix_disable = 0; 95TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 96TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 97 98/* 99 * Devices supported by this driver. 100 */ 101static struct alc_ident alc_ident_table[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 103 "Atheros AR8131 PCIe Gigabit Ethernet" }, 104 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 105 "Atheros AR8132 PCIe Fast Ethernet" }, 106 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 107 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 109 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 111 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 113 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 115 "Atheros AR8161 PCIe Gigabit Ethernet" }, 116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 117 "Atheros AR8162 PCIe Fast Ethernet" }, 118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 119 "Atheros AR8171 PCIe Gigabit Ethernet" }, 120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 121 "Atheros AR8172 PCIe Fast Ethernet" }, 122 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 123 "Killer E2200 Gigabit Ethernet" }, 124 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 125 "Killer E2400 Gigabit Ethernet" }, 126 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 127 "Killer E2500 Gigabit Ethernet" }, 128 { 0, 0, 0, NULL} 129}; 130 131static void alc_aspm(struct alc_softc *, int, int); 132static void alc_aspm_813x(struct alc_softc *, int); 133static void alc_aspm_816x(struct alc_softc *, int); 134static int alc_attach(device_t); 135static int alc_check_boundary(struct alc_softc *); 136static void alc_config_msi(struct alc_softc *); 137static int alc_detach(device_t); 138static void alc_disable_l0s_l1(struct alc_softc *); 139static int alc_dma_alloc(struct alc_softc *); 140static void alc_dma_free(struct alc_softc *); 141static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 142static void alc_dsp_fixup(struct alc_softc *, int); 143static int alc_encap(struct alc_softc *, struct mbuf **); 144static struct alc_ident * 145 alc_find_ident(device_t); 146#ifndef __NO_STRICT_ALIGNMENT 147static struct mbuf * 148 alc_fixup_rx(struct ifnet *, struct mbuf *); 149#endif 150static void alc_get_macaddr(struct alc_softc *); 151static void alc_get_macaddr_813x(struct alc_softc *); 152static void alc_get_macaddr_816x(struct alc_softc *); 153static void alc_get_macaddr_par(struct alc_softc *); 154static void alc_init(void *); 155static void alc_init_cmb(struct alc_softc *); 156static void alc_init_locked(struct alc_softc *); 157static void alc_init_rr_ring(struct alc_softc *); 158static int alc_init_rx_ring(struct alc_softc *); 159static void alc_init_smb(struct alc_softc *); 160static void alc_init_tx_ring(struct alc_softc *); 161static void alc_int_task(void *, int); 162static int alc_intr(void *); 163static int alc_ioctl(struct ifnet *, u_long, caddr_t); 164static void alc_mac_config(struct alc_softc *); 165static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 166static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 167static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 168static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 169static int alc_miibus_readreg(device_t, int, int); 170static void alc_miibus_statchg(device_t); 171static int alc_miibus_writereg(device_t, int, int, int); 172static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 173static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 174static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 175static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 176static int alc_mediachange(struct ifnet *); 177static int alc_mediachange_locked(struct alc_softc *); 178static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 179static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 180static void alc_osc_reset(struct alc_softc *); 181static void alc_phy_down(struct alc_softc *); 182static void alc_phy_reset(struct alc_softc *); 183static void alc_phy_reset_813x(struct alc_softc *); 184static void alc_phy_reset_816x(struct alc_softc *); 185static int alc_probe(device_t); 186static void alc_reset(struct alc_softc *); 187static int alc_resume(device_t); 188static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 189static int alc_rxintr(struct alc_softc *, int); 190static void alc_rxfilter(struct alc_softc *); 191static void alc_rxvlan(struct alc_softc *); 192static void alc_setlinkspeed(struct alc_softc *); 193static void alc_setwol(struct alc_softc *); 194static void alc_setwol_813x(struct alc_softc *); 195static void alc_setwol_816x(struct alc_softc *); 196static int alc_shutdown(device_t); 197static void alc_start(struct ifnet *); 198static void alc_start_locked(struct ifnet *); 199static void alc_start_queue(struct alc_softc *); 200static void alc_stats_clear(struct alc_softc *); 201static void alc_stats_update(struct alc_softc *); 202static void alc_stop(struct alc_softc *); 203static void alc_stop_mac(struct alc_softc *); 204static void alc_stop_queue(struct alc_softc *); 205static int alc_suspend(device_t); 206static void alc_sysctl_node(struct alc_softc *); 207static void alc_tick(void *); 208static void alc_txeof(struct alc_softc *); 209static void alc_watchdog(struct alc_softc *); 210static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 211static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 212static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 213 214static device_method_t alc_methods[] = { 215 /* Device interface. */ 216 DEVMETHOD(device_probe, alc_probe), 217 DEVMETHOD(device_attach, alc_attach), 218 DEVMETHOD(device_detach, alc_detach), 219 DEVMETHOD(device_shutdown, alc_shutdown), 220 DEVMETHOD(device_suspend, alc_suspend), 221 DEVMETHOD(device_resume, alc_resume), 222 223 /* MII interface. */ 224 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 225 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 226 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 227 228 { NULL, NULL } 229}; 230 231static driver_t alc_driver = { 232 "alc", 233 alc_methods, 234 sizeof(struct alc_softc) 235}; 236 237static devclass_t alc_devclass; 238 239DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 240DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 241 242static struct resource_spec alc_res_spec_mem[] = { 243 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 244 { -1, 0, 0 } 245}; 246 247static struct resource_spec alc_irq_spec_legacy[] = { 248 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 249 { -1, 0, 0 } 250}; 251 252static struct resource_spec alc_irq_spec_msi[] = { 253 { SYS_RES_IRQ, 1, RF_ACTIVE }, 254 { -1, 0, 0 } 255}; 256 257static struct resource_spec alc_irq_spec_msix[] = { 258 { SYS_RES_IRQ, 1, RF_ACTIVE }, 259 { -1, 0, 0 } 260}; 261 262static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 263 264static int 265alc_miibus_readreg(device_t dev, int phy, int reg) 266{ 267 struct alc_softc *sc; 268 int v; 269 270 sc = device_get_softc(dev); 271 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 272 v = alc_mii_readreg_816x(sc, phy, reg); 273 else 274 v = alc_mii_readreg_813x(sc, phy, reg); 275 return (v); 276} 277 278static uint32_t 279alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 280{ 281 uint32_t v; 282 int i; 283 284 /* 285 * For AR8132 fast ethernet controller, do not report 1000baseT 286 * capability to mii(4). Even though AR8132 uses the same 287 * model/revision number of F1 gigabit PHY, the PHY has no 288 * ability to establish 1000baseT link. 289 */ 290 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 291 reg == MII_EXTSR) 292 return (0); 293 294 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 295 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 296 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 297 DELAY(5); 298 v = CSR_READ_4(sc, ALC_MDIO); 299 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 300 break; 301 } 302 303 if (i == 0) { 304 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 305 return (0); 306 } 307 308 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 309} 310 311static uint32_t 312alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 313{ 314 uint32_t clk, v; 315 int i; 316 317 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 318 clk = MDIO_CLK_25_128; 319 else 320 clk = MDIO_CLK_25_4; 321 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 322 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 323 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 324 DELAY(5); 325 v = CSR_READ_4(sc, ALC_MDIO); 326 if ((v & MDIO_OP_BUSY) == 0) 327 break; 328 } 329 330 if (i == 0) { 331 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 332 return (0); 333 } 334 335 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 336} 337 338static int 339alc_miibus_writereg(device_t dev, int phy, int reg, int val) 340{ 341 struct alc_softc *sc; 342 int v; 343 344 sc = device_get_softc(dev); 345 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 346 v = alc_mii_writereg_816x(sc, phy, reg, val); 347 else 348 v = alc_mii_writereg_813x(sc, phy, reg, val); 349 return (v); 350} 351 352static uint32_t 353alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 354{ 355 uint32_t v; 356 int i; 357 358 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 359 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 360 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 361 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 362 DELAY(5); 363 v = CSR_READ_4(sc, ALC_MDIO); 364 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 365 break; 366 } 367 368 if (i == 0) 369 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 370 371 return (0); 372} 373 374static uint32_t 375alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 376{ 377 uint32_t clk, v; 378 int i; 379 380 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 381 clk = MDIO_CLK_25_128; 382 else 383 clk = MDIO_CLK_25_4; 384 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 385 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 386 MDIO_SUP_PREAMBLE | clk); 387 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 388 DELAY(5); 389 v = CSR_READ_4(sc, ALC_MDIO); 390 if ((v & MDIO_OP_BUSY) == 0) 391 break; 392 } 393 394 if (i == 0) 395 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 396 397 return (0); 398} 399 400static void 401alc_miibus_statchg(device_t dev) 402{ 403 struct alc_softc *sc; 404 struct mii_data *mii; 405 struct ifnet *ifp; 406 uint32_t reg; 407 408 sc = device_get_softc(dev); 409 410 mii = device_get_softc(sc->alc_miibus); 411 ifp = sc->alc_ifp; 412 if (mii == NULL || ifp == NULL || 413 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 414 return; 415 416 sc->alc_flags &= ~ALC_FLAG_LINK; 417 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 418 (IFM_ACTIVE | IFM_AVALID)) { 419 switch (IFM_SUBTYPE(mii->mii_media_active)) { 420 case IFM_10_T: 421 case IFM_100_TX: 422 sc->alc_flags |= ALC_FLAG_LINK; 423 break; 424 case IFM_1000_T: 425 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 426 sc->alc_flags |= ALC_FLAG_LINK; 427 break; 428 default: 429 break; 430 } 431 } 432 /* Stop Rx/Tx MACs. */ 433 alc_stop_mac(sc); 434 435 /* Program MACs with resolved speed/duplex/flow-control. */ 436 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 437 alc_start_queue(sc); 438 alc_mac_config(sc); 439 /* Re-enable Tx/Rx MACs. */ 440 reg = CSR_READ_4(sc, ALC_MAC_CFG); 441 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 442 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 443 } 444 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 445 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 446} 447 448static uint32_t 449alc_miidbg_readreg(struct alc_softc *sc, int reg) 450{ 451 452 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 453 reg); 454 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 455 ALC_MII_DBG_DATA)); 456} 457 458static uint32_t 459alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 460{ 461 462 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 463 reg); 464 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 465 ALC_MII_DBG_DATA, val)); 466} 467 468static uint32_t 469alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 470{ 471 uint32_t clk, v; 472 int i; 473 474 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 475 EXT_MDIO_DEVADDR(devaddr)); 476 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 477 clk = MDIO_CLK_25_128; 478 else 479 clk = MDIO_CLK_25_4; 480 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 481 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 482 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 483 DELAY(5); 484 v = CSR_READ_4(sc, ALC_MDIO); 485 if ((v & MDIO_OP_BUSY) == 0) 486 break; 487 } 488 489 if (i == 0) { 490 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 491 devaddr, reg); 492 return (0); 493 } 494 495 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 496} 497 498static uint32_t 499alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 500{ 501 uint32_t clk, v; 502 int i; 503 504 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 505 EXT_MDIO_DEVADDR(devaddr)); 506 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 507 clk = MDIO_CLK_25_128; 508 else 509 clk = MDIO_CLK_25_4; 510 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 511 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 512 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 513 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 514 DELAY(5); 515 v = CSR_READ_4(sc, ALC_MDIO); 516 if ((v & MDIO_OP_BUSY) == 0) 517 break; 518 } 519 520 if (i == 0) 521 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 522 devaddr, reg); 523 524 return (0); 525} 526 527static void 528alc_dsp_fixup(struct alc_softc *sc, int media) 529{ 530 uint16_t agc, len, val; 531 532 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 533 return; 534 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 535 return; 536 537 /* 538 * Vendor PHY magic. 539 * 1000BT/AZ, wrong cable length 540 */ 541 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 542 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 543 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 544 EXT_CLDCTL6_CAB_LEN_MASK; 545 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 546 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 547 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 548 agc > DBG_AGC_LONG1G_LIMT) || 549 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 550 agc > DBG_AGC_LONG1G_LIMT)) { 551 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 552 DBG_AZ_ANADECT_LONG); 553 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 554 MII_EXT_ANEG_AFE); 555 val |= ANEG_AFEE_10BT_100M_TH; 556 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 557 val); 558 } else { 559 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 560 DBG_AZ_ANADECT_DEFAULT); 561 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 562 MII_EXT_ANEG_AFE); 563 val &= ~ANEG_AFEE_10BT_100M_TH; 564 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 565 val); 566 } 567 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 568 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 569 if (media == IFM_1000_T) { 570 /* 571 * Giga link threshold, raise the tolerance of 572 * noise 50%. 573 */ 574 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 575 val &= ~DBG_MSE20DB_TH_MASK; 576 val |= (DBG_MSE20DB_TH_HI << 577 DBG_MSE20DB_TH_SHIFT); 578 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 579 } else if (media == IFM_100_TX) 580 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 581 DBG_MSE16DB_UP); 582 } 583 } else { 584 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 585 val &= ~ANEG_AFEE_10BT_100M_TH; 586 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 587 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 588 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 589 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 590 DBG_MSE16DB_DOWN); 591 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 592 val &= ~DBG_MSE20DB_TH_MASK; 593 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 594 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 595 } 596 } 597} 598 599static void 600alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 601{ 602 struct alc_softc *sc; 603 struct mii_data *mii; 604 605 sc = ifp->if_softc; 606 ALC_LOCK(sc); 607 if ((ifp->if_flags & IFF_UP) == 0) { 608 ALC_UNLOCK(sc); 609 return; 610 } 611 mii = device_get_softc(sc->alc_miibus); 612 613 mii_pollstat(mii); 614 ifmr->ifm_status = mii->mii_media_status; 615 ifmr->ifm_active = mii->mii_media_active; 616 ALC_UNLOCK(sc); 617} 618 619static int 620alc_mediachange(struct ifnet *ifp) 621{ 622 struct alc_softc *sc; 623 int error; 624 625 sc = ifp->if_softc; 626 ALC_LOCK(sc); 627 error = alc_mediachange_locked(sc); 628 ALC_UNLOCK(sc); 629 630 return (error); 631} 632 633static int 634alc_mediachange_locked(struct alc_softc *sc) 635{ 636 struct mii_data *mii; 637 struct mii_softc *miisc; 638 int error; 639 640 ALC_LOCK_ASSERT(sc); 641 642 mii = device_get_softc(sc->alc_miibus); 643 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 644 PHY_RESET(miisc); 645 error = mii_mediachg(mii); 646 647 return (error); 648} 649 650static struct alc_ident * 651alc_find_ident(device_t dev) 652{ 653 struct alc_ident *ident; 654 uint16_t vendor, devid; 655 656 vendor = pci_get_vendor(dev); 657 devid = pci_get_device(dev); 658 for (ident = alc_ident_table; ident->name != NULL; ident++) { 659 if (vendor == ident->vendorid && devid == ident->deviceid) 660 return (ident); 661 } 662 663 return (NULL); 664} 665 666static int 667alc_probe(device_t dev) 668{ 669 struct alc_ident *ident; 670 671 ident = alc_find_ident(dev); 672 if (ident != NULL) { 673 device_set_desc(dev, ident->name); 674 return (BUS_PROBE_DEFAULT); 675 } 676 677 return (ENXIO); 678} 679 680static void 681alc_get_macaddr(struct alc_softc *sc) 682{ 683 684 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 685 alc_get_macaddr_816x(sc); 686 else 687 alc_get_macaddr_813x(sc); 688} 689 690static void 691alc_get_macaddr_813x(struct alc_softc *sc) 692{ 693 uint32_t opt; 694 uint16_t val; 695 int eeprom, i; 696 697 eeprom = 0; 698 opt = CSR_READ_4(sc, ALC_OPT_CFG); 699 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 700 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 701 /* 702 * EEPROM found, let TWSI reload EEPROM configuration. 703 * This will set ethernet address of controller. 704 */ 705 eeprom++; 706 switch (sc->alc_ident->deviceid) { 707 case DEVICEID_ATHEROS_AR8131: 708 case DEVICEID_ATHEROS_AR8132: 709 if ((opt & OPT_CFG_CLK_ENB) == 0) { 710 opt |= OPT_CFG_CLK_ENB; 711 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 712 CSR_READ_4(sc, ALC_OPT_CFG); 713 DELAY(1000); 714 } 715 break; 716 case DEVICEID_ATHEROS_AR8151: 717 case DEVICEID_ATHEROS_AR8151_V2: 718 case DEVICEID_ATHEROS_AR8152_B: 719 case DEVICEID_ATHEROS_AR8152_B2: 720 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 721 ALC_MII_DBG_ADDR, 0x00); 722 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 723 ALC_MII_DBG_DATA); 724 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 725 ALC_MII_DBG_DATA, val & 0xFF7F); 726 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 727 ALC_MII_DBG_ADDR, 0x3B); 728 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 729 ALC_MII_DBG_DATA); 730 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 731 ALC_MII_DBG_DATA, val | 0x0008); 732 DELAY(20); 733 break; 734 } 735 736 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 737 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 738 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 739 CSR_READ_4(sc, ALC_WOL_CFG); 740 741 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 742 TWSI_CFG_SW_LD_START); 743 for (i = 100; i > 0; i--) { 744 DELAY(1000); 745 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 746 TWSI_CFG_SW_LD_START) == 0) 747 break; 748 } 749 if (i == 0) 750 device_printf(sc->alc_dev, 751 "reloading EEPROM timeout!\n"); 752 } else { 753 if (bootverbose) 754 device_printf(sc->alc_dev, "EEPROM not found!\n"); 755 } 756 if (eeprom != 0) { 757 switch (sc->alc_ident->deviceid) { 758 case DEVICEID_ATHEROS_AR8131: 759 case DEVICEID_ATHEROS_AR8132: 760 if ((opt & OPT_CFG_CLK_ENB) != 0) { 761 opt &= ~OPT_CFG_CLK_ENB; 762 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 763 CSR_READ_4(sc, ALC_OPT_CFG); 764 DELAY(1000); 765 } 766 break; 767 case DEVICEID_ATHEROS_AR8151: 768 case DEVICEID_ATHEROS_AR8151_V2: 769 case DEVICEID_ATHEROS_AR8152_B: 770 case DEVICEID_ATHEROS_AR8152_B2: 771 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 772 ALC_MII_DBG_ADDR, 0x00); 773 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 774 ALC_MII_DBG_DATA); 775 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 776 ALC_MII_DBG_DATA, val | 0x0080); 777 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 778 ALC_MII_DBG_ADDR, 0x3B); 779 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_DATA); 781 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_DATA, val & 0xFFF7); 783 DELAY(20); 784 break; 785 } 786 } 787 788 alc_get_macaddr_par(sc); 789} 790 791static void 792alc_get_macaddr_816x(struct alc_softc *sc) 793{ 794 uint32_t reg; 795 int i, reloaded; 796 797 reloaded = 0; 798 /* Try to reload station address via TWSI. */ 799 for (i = 100; i > 0; i--) { 800 reg = CSR_READ_4(sc, ALC_SLD); 801 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 802 break; 803 DELAY(1000); 804 } 805 if (i != 0) { 806 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 807 for (i = 100; i > 0; i--) { 808 DELAY(1000); 809 reg = CSR_READ_4(sc, ALC_SLD); 810 if ((reg & SLD_START) == 0) 811 break; 812 } 813 if (i != 0) 814 reloaded++; 815 else if (bootverbose) 816 device_printf(sc->alc_dev, 817 "reloading station address via TWSI timed out!\n"); 818 } 819 820 /* Try to reload station address from EEPROM or FLASH. */ 821 if (reloaded == 0) { 822 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 823 if ((reg & (EEPROM_LD_EEPROM_EXIST | 824 EEPROM_LD_FLASH_EXIST)) != 0) { 825 for (i = 100; i > 0; i--) { 826 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 827 if ((reg & (EEPROM_LD_PROGRESS | 828 EEPROM_LD_START)) == 0) 829 break; 830 DELAY(1000); 831 } 832 if (i != 0) { 833 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 834 EEPROM_LD_START); 835 for (i = 100; i > 0; i--) { 836 DELAY(1000); 837 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 838 if ((reg & EEPROM_LD_START) == 0) 839 break; 840 } 841 } else if (bootverbose) 842 device_printf(sc->alc_dev, 843 "reloading EEPROM/FLASH timed out!\n"); 844 } 845 } 846 847 alc_get_macaddr_par(sc); 848} 849 850static void 851alc_get_macaddr_par(struct alc_softc *sc) 852{ 853 uint32_t ea[2]; 854 855 ea[0] = CSR_READ_4(sc, ALC_PAR0); 856 ea[1] = CSR_READ_4(sc, ALC_PAR1); 857 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 858 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 859 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 860 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 861 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 862 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 863} 864 865static void 866alc_disable_l0s_l1(struct alc_softc *sc) 867{ 868 uint32_t pmcfg; 869 870 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 871 /* Another magic from vendor. */ 872 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 873 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 874 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 875 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 876 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 877 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 878 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 879 } 880} 881 882static void 883alc_phy_reset(struct alc_softc *sc) 884{ 885 886 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 887 alc_phy_reset_816x(sc); 888 else 889 alc_phy_reset_813x(sc); 890} 891 892static void 893alc_phy_reset_813x(struct alc_softc *sc) 894{ 895 uint16_t data; 896 897 /* Reset magic from Linux. */ 898 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 899 CSR_READ_2(sc, ALC_GPHY_CFG); 900 DELAY(10 * 1000); 901 902 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 903 GPHY_CFG_SEL_ANA_RESET); 904 CSR_READ_2(sc, ALC_GPHY_CFG); 905 DELAY(10 * 1000); 906 907 /* DSP fixup, Vendor magic. */ 908 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 909 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 910 ALC_MII_DBG_ADDR, 0x000A); 911 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 912 ALC_MII_DBG_DATA); 913 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 914 ALC_MII_DBG_DATA, data & 0xDFFF); 915 } 916 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 917 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 918 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 919 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 920 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 921 ALC_MII_DBG_ADDR, 0x003B); 922 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 923 ALC_MII_DBG_DATA); 924 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 925 ALC_MII_DBG_DATA, data & 0xFFF7); 926 DELAY(20 * 1000); 927 } 928 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 929 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 930 ALC_MII_DBG_ADDR, 0x0029); 931 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 932 ALC_MII_DBG_DATA, 0x929D); 933 } 934 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 935 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 936 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 937 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 938 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 939 ALC_MII_DBG_ADDR, 0x0029); 940 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 941 ALC_MII_DBG_DATA, 0xB6DD); 942 } 943 944 /* Load DSP codes, vendor magic. */ 945 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 946 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 947 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 948 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 949 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 950 ALC_MII_DBG_DATA, data); 951 952 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 953 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 954 ANA_SERDES_EN_LCKDT; 955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 956 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 957 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 958 ALC_MII_DBG_DATA, data); 959 960 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 961 ANA_LONG_CABLE_TH_100_MASK) | 962 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 963 ANA_SHORT_CABLE_TH_100_SHIFT) | 964 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 965 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 966 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 967 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 968 ALC_MII_DBG_DATA, data); 969 970 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 971 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 972 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 973 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 974 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 975 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 976 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 977 ALC_MII_DBG_DATA, data); 978 979 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 980 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 981 ANA_OEN_125M; 982 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 983 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 984 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 985 ALC_MII_DBG_DATA, data); 986 DELAY(1000); 987 988 /* Disable hibernation. */ 989 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 990 0x0029); 991 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 992 ALC_MII_DBG_DATA); 993 data &= ~0x8000; 994 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 995 data); 996 997 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 998 0x000B); 999 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1000 ALC_MII_DBG_DATA); 1001 data &= ~0x8000; 1002 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1003 data); 1004} 1005 1006static void 1007alc_phy_reset_816x(struct alc_softc *sc) 1008{ 1009 uint32_t val; 1010 1011 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1012 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1013 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1014 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1015 val |= GPHY_CFG_SEL_ANA_RESET; 1016#ifdef notyet 1017 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1018#else 1019 /* Disable PHY hibernation. */ 1020 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1021#endif 1022 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1023 DELAY(10); 1024 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1025 DELAY(800); 1026 1027 /* Vendor PHY magic. */ 1028#ifdef notyet 1029 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1030 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1031 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1032 EXT_VDRVBIAS_DEFAULT); 1033#else 1034 /* Disable PHY hibernation. */ 1035 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1036 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1037 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1038 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1039 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1040#endif 1041 1042 /* XXX Disable EEE. */ 1043 val = CSR_READ_4(sc, ALC_LPI_CTL); 1044 val &= ~LPI_CTL_ENB; 1045 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1046 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1047 1048 /* PHY power saving. */ 1049 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1050 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1051 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1052 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1053 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1054 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1055 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1056 1057 /* RTL8139C, 120m issue. */ 1058 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1059 ANEG_NLP78_120M_DEFAULT); 1060 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1061 ANEG_S3DIG10_DEFAULT); 1062 1063 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1064 /* Turn off half amplitude. */ 1065 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1066 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1067 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1068 /* Turn off Green feature. */ 1069 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1070 val |= DBG_GREENCFG2_BP_GREEN; 1071 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1072 /* Turn off half bias. */ 1073 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1074 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1075 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1076 } 1077} 1078 1079static void 1080alc_phy_down(struct alc_softc *sc) 1081{ 1082 uint32_t gphy; 1083 1084 switch (sc->alc_ident->deviceid) { 1085 case DEVICEID_ATHEROS_AR8161: 1086 case DEVICEID_ATHEROS_E2200: 1087 case DEVICEID_ATHEROS_E2400: 1088 case DEVICEID_ATHEROS_E2500: 1089 case DEVICEID_ATHEROS_AR8162: 1090 case DEVICEID_ATHEROS_AR8171: 1091 case DEVICEID_ATHEROS_AR8172: 1092 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1093 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1094 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1095 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1096 GPHY_CFG_SEL_ANA_RESET; 1097 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1098 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1099 break; 1100 case DEVICEID_ATHEROS_AR8151: 1101 case DEVICEID_ATHEROS_AR8151_V2: 1102 case DEVICEID_ATHEROS_AR8152_B: 1103 case DEVICEID_ATHEROS_AR8152_B2: 1104 /* 1105 * GPHY power down caused more problems on AR8151 v2.0. 1106 * When driver is reloaded after GPHY power down, 1107 * accesses to PHY/MAC registers hung the system. Only 1108 * cold boot recovered from it. I'm not sure whether 1109 * AR8151 v1.0 also requires this one though. I don't 1110 * have AR8151 v1.0 controller in hand. 1111 * The only option left is to isolate the PHY and 1112 * initiates power down the PHY which in turn saves 1113 * more power when driver is unloaded. 1114 */ 1115 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1116 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1117 break; 1118 default: 1119 /* Force PHY down. */ 1120 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1121 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1122 GPHY_CFG_PWDOWN_HW); 1123 DELAY(1000); 1124 break; 1125 } 1126} 1127 1128static void 1129alc_aspm(struct alc_softc *sc, int init, int media) 1130{ 1131 1132 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1133 alc_aspm_816x(sc, init); 1134 else 1135 alc_aspm_813x(sc, media); 1136} 1137 1138static void 1139alc_aspm_813x(struct alc_softc *sc, int media) 1140{ 1141 uint32_t pmcfg; 1142 uint16_t linkcfg; 1143 1144 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1145 return; 1146 1147 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1148 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1149 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1150 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1151 PCIER_LINK_CTL); 1152 else 1153 linkcfg = 0; 1154 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1155 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1156 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1157 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1158 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1159 1160 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1161 /* Disable extended sync except AR8152 B v1.0 */ 1162 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1163 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1164 sc->alc_rev == ATHEROS_AR8152_B_V10) 1165 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1166 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1167 linkcfg); 1168 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1169 PM_CFG_HOTRST); 1170 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1171 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1172 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1173 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1174 PM_CFG_PM_REQ_TIMER_SHIFT); 1175 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1176 } 1177 1178 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1179 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1180 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1181 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1182 pmcfg |= PM_CFG_ASPM_L1_ENB; 1183 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1184 if (sc->alc_ident->deviceid == 1185 DEVICEID_ATHEROS_AR8152_B) 1186 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1187 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1188 PM_CFG_SERDES_PLL_L1_ENB | 1189 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1190 pmcfg |= PM_CFG_CLK_SWH_L1; 1191 if (media == IFM_100_TX || media == IFM_1000_T) { 1192 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1193 switch (sc->alc_ident->deviceid) { 1194 case DEVICEID_ATHEROS_AR8152_B: 1195 pmcfg |= (7 << 1196 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1197 break; 1198 case DEVICEID_ATHEROS_AR8152_B2: 1199 case DEVICEID_ATHEROS_AR8151_V2: 1200 pmcfg |= (4 << 1201 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1202 break; 1203 default: 1204 pmcfg |= (15 << 1205 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1206 break; 1207 } 1208 } 1209 } else { 1210 pmcfg |= PM_CFG_SERDES_L1_ENB | 1211 PM_CFG_SERDES_PLL_L1_ENB | 1212 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1213 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1214 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1215 } 1216 } else { 1217 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1218 PM_CFG_SERDES_PLL_L1_ENB); 1219 pmcfg |= PM_CFG_CLK_SWH_L1; 1220 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1221 pmcfg |= PM_CFG_ASPM_L1_ENB; 1222 } 1223 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1224} 1225 1226static void 1227alc_aspm_816x(struct alc_softc *sc, int init) 1228{ 1229 uint32_t pmcfg; 1230 1231 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1232 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1233 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1234 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1235 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1236 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1237 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1238 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1239 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1240 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1241 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1242 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1243 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1244 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1245 (sc->alc_rev & 0x01) != 0) 1246 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1247 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1248 /* Link up, enable both L0s, L1s. */ 1249 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1250 PM_CFG_MAC_ASPM_CHK; 1251 } else { 1252 if (init != 0) 1253 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1254 PM_CFG_MAC_ASPM_CHK; 1255 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1256 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1257 } 1258 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1259} 1260 1261static void 1262alc_init_pcie(struct alc_softc *sc) 1263{ 1264 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1265 uint32_t cap, ctl, val; 1266 int state; 1267 1268 /* Clear data link and flow-control protocol error. */ 1269 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1270 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1271 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1272 1273 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1274 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1275 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1276 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1277 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1278 PCIE_PHYMISC_FORCE_RCV_DET); 1279 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1280 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1281 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1282 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1283 PCIE_PHYMISC2_SERDES_TH_MASK); 1284 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1285 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1286 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1287 } 1288 /* Disable ASPM L0S and L1. */ 1289 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1290 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1291 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1292 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1293 sc->alc_rcb = DMA_CFG_RCB_128; 1294 if (bootverbose) 1295 device_printf(sc->alc_dev, "RCB %u bytes\n", 1296 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1297 state = ctl & PCIEM_LINK_CTL_ASPMC; 1298 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1299 sc->alc_flags |= ALC_FLAG_L0S; 1300 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1301 sc->alc_flags |= ALC_FLAG_L1S; 1302 if (bootverbose) 1303 device_printf(sc->alc_dev, "ASPM %s %s\n", 1304 aspm_state[state], 1305 state == 0 ? "disabled" : "enabled"); 1306 alc_disable_l0s_l1(sc); 1307 } else { 1308 if (bootverbose) 1309 device_printf(sc->alc_dev, 1310 "no ASPM support\n"); 1311 } 1312 } else { 1313 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1314 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1315 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1316 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1317 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1318 (sc->alc_rev & 0x01) != 0) { 1319 if ((val & MASTER_WAKEN_25M) == 0 || 1320 (val & MASTER_CLK_SEL_DIS) == 0) { 1321 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1322 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1323 } 1324 } else { 1325 if ((val & MASTER_WAKEN_25M) == 0 || 1326 (val & MASTER_CLK_SEL_DIS) != 0) { 1327 val |= MASTER_WAKEN_25M; 1328 val &= ~MASTER_CLK_SEL_DIS; 1329 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1330 } 1331 } 1332 } 1333 alc_aspm(sc, 1, IFM_UNKNOWN); 1334} 1335 1336static void 1337alc_config_msi(struct alc_softc *sc) 1338{ 1339 uint32_t ctl, mod; 1340 1341 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1342 /* 1343 * It seems interrupt moderation is controlled by 1344 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1345 * Driver uses RX interrupt moderation parameter to 1346 * program ALC_MSI_RETRANS_TIMER register. 1347 */ 1348 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1349 ctl &= ~MSI_RETRANS_TIMER_MASK; 1350 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1351 mod = ALC_USECS(sc->alc_int_rx_mod); 1352 if (mod == 0) 1353 mod = 1; 1354 ctl |= mod; 1355 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1356 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1357 MSI_RETRANS_MASK_SEL_STD); 1358 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1359 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1360 MSI_RETRANS_MASK_SEL_LINE); 1361 else 1362 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1363 } 1364} 1365 1366static int 1367alc_attach(device_t dev) 1368{ 1369 struct alc_softc *sc; 1370 struct ifnet *ifp; 1371 int base, error, i, msic, msixc; 1372 uint16_t burst; 1373 1374 error = 0; 1375 sc = device_get_softc(dev); 1376 sc->alc_dev = dev; 1377 sc->alc_rev = pci_get_revid(dev); 1378 1379 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1380 MTX_DEF); 1381 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1382 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1383 sc->alc_ident = alc_find_ident(dev); 1384 1385 /* Map the device. */ 1386 pci_enable_busmaster(dev); 1387 sc->alc_res_spec = alc_res_spec_mem; 1388 sc->alc_irq_spec = alc_irq_spec_legacy; 1389 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1390 if (error != 0) { 1391 device_printf(dev, "cannot allocate memory resources.\n"); 1392 goto fail; 1393 } 1394 1395 /* Set PHY address. */ 1396 sc->alc_phyaddr = ALC_PHY_ADDR; 1397 1398 /* 1399 * One odd thing is AR8132 uses the same PHY hardware(F1 1400 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1401 * the PHY supports 1000Mbps but that's not true. The PHY 1402 * used in AR8132 can't establish gigabit link even if it 1403 * shows the same PHY model/revision number of AR8131. 1404 */ 1405 switch (sc->alc_ident->deviceid) { 1406 case DEVICEID_ATHEROS_E2200: 1407 case DEVICEID_ATHEROS_E2400: 1408 case DEVICEID_ATHEROS_E2500: 1409 sc->alc_flags |= ALC_FLAG_E2X00; 1410 /* FALLTHROUGH */ 1411 case DEVICEID_ATHEROS_AR8161: 1412 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1413 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1414 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1415 /* FALLTHROUGH */ 1416 case DEVICEID_ATHEROS_AR8171: 1417 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1418 break; 1419 case DEVICEID_ATHEROS_AR8162: 1420 case DEVICEID_ATHEROS_AR8172: 1421 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1422 break; 1423 case DEVICEID_ATHEROS_AR8152_B: 1424 case DEVICEID_ATHEROS_AR8152_B2: 1425 sc->alc_flags |= ALC_FLAG_APS; 1426 /* FALLTHROUGH */ 1427 case DEVICEID_ATHEROS_AR8132: 1428 sc->alc_flags |= ALC_FLAG_FASTETHER; 1429 break; 1430 case DEVICEID_ATHEROS_AR8151: 1431 case DEVICEID_ATHEROS_AR8151_V2: 1432 sc->alc_flags |= ALC_FLAG_APS; 1433 /* FALLTHROUGH */ 1434 default: 1435 break; 1436 } 1437 sc->alc_flags |= ALC_FLAG_JUMBO; 1438 1439 /* 1440 * It seems that AR813x/AR815x has silicon bug for SMB. In 1441 * addition, Atheros said that enabling SMB wouldn't improve 1442 * performance. However I think it's bad to access lots of 1443 * registers to extract MAC statistics. 1444 */ 1445 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1446 /* 1447 * Don't use Tx CMB. It is known to have silicon bug. 1448 */ 1449 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1450 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1451 MASTER_CHIP_REV_SHIFT; 1452 if (bootverbose) { 1453 device_printf(dev, "PCI device revision : 0x%04x\n", 1454 sc->alc_rev); 1455 device_printf(dev, "Chip id/revision : 0x%04x\n", 1456 sc->alc_chip_rev); 1457 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1458 device_printf(dev, "AR816x revision : 0x%x\n", 1459 AR816X_REV(sc->alc_rev)); 1460 } 1461 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1462 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1463 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1464 1465 /* Initialize DMA parameters. */ 1466 sc->alc_dma_rd_burst = 0; 1467 sc->alc_dma_wr_burst = 0; 1468 sc->alc_rcb = DMA_CFG_RCB_64; 1469 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1470 sc->alc_flags |= ALC_FLAG_PCIE; 1471 sc->alc_expcap = base; 1472 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1473 sc->alc_dma_rd_burst = 1474 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1475 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1476 if (bootverbose) { 1477 device_printf(dev, "Read request size : %u bytes.\n", 1478 alc_dma_burst[sc->alc_dma_rd_burst]); 1479 device_printf(dev, "TLP payload size : %u bytes.\n", 1480 alc_dma_burst[sc->alc_dma_wr_burst]); 1481 } 1482 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1483 sc->alc_dma_rd_burst = 3; 1484 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1485 sc->alc_dma_wr_burst = 3; 1486 /* 1487 * Force maximum payload size to 128 bytes for 1488 * E2200/E2400/E2500. 1489 * Otherwise it triggers DMA write error. 1490 */ 1491 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0) 1492 sc->alc_dma_wr_burst = 0; 1493 alc_init_pcie(sc); 1494 } 1495 1496 /* Reset PHY. */ 1497 alc_phy_reset(sc); 1498 1499 /* Reset the ethernet controller. */ 1500 alc_stop_mac(sc); 1501 alc_reset(sc); 1502 1503 /* Allocate IRQ resources. */ 1504 msixc = pci_msix_count(dev); 1505 msic = pci_msi_count(dev); 1506 if (bootverbose) { 1507 device_printf(dev, "MSIX count : %d\n", msixc); 1508 device_printf(dev, "MSI count : %d\n", msic); 1509 } 1510 if (msixc > 1) 1511 msixc = 1; 1512 if (msic > 1) 1513 msic = 1; 1514 /* 1515 * Prefer MSIX over MSI. 1516 * AR816x controller has a silicon bug that MSI interrupt 1517 * does not assert if PCIM_CMD_INTxDIS bit of command 1518 * register is set. pci(4) was taught to handle that case. 1519 */ 1520 if (msix_disable == 0 || msi_disable == 0) { 1521 if (msix_disable == 0 && msixc > 0 && 1522 pci_alloc_msix(dev, &msixc) == 0) { 1523 if (msic == 1) { 1524 device_printf(dev, 1525 "Using %d MSIX message(s).\n", msixc); 1526 sc->alc_flags |= ALC_FLAG_MSIX; 1527 sc->alc_irq_spec = alc_irq_spec_msix; 1528 } else 1529 pci_release_msi(dev); 1530 } 1531 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1532 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1533 if (msic == 1) { 1534 device_printf(dev, 1535 "Using %d MSI message(s).\n", msic); 1536 sc->alc_flags |= ALC_FLAG_MSI; 1537 sc->alc_irq_spec = alc_irq_spec_msi; 1538 } else 1539 pci_release_msi(dev); 1540 } 1541 } 1542 1543 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1544 if (error != 0) { 1545 device_printf(dev, "cannot allocate IRQ resources.\n"); 1546 goto fail; 1547 } 1548 1549 /* Create device sysctl node. */ 1550 alc_sysctl_node(sc); 1551 1552 if ((error = alc_dma_alloc(sc)) != 0) 1553 goto fail; 1554 1555 /* Load station address. */ 1556 alc_get_macaddr(sc); 1557 1558 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1559 if (ifp == NULL) { 1560 device_printf(dev, "cannot allocate ifnet structure.\n"); 1561 error = ENXIO; 1562 goto fail; 1563 } 1564 1565 ifp->if_softc = sc; 1566 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1567 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1568 ifp->if_ioctl = alc_ioctl; 1569 ifp->if_start = alc_start; 1570 ifp->if_init = alc_init; 1571 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 1572 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1573 IFQ_SET_READY(&ifp->if_snd); 1574 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1575 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 1576 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1577 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1578 sc->alc_flags |= ALC_FLAG_PM; 1579 sc->alc_pmcap = base; 1580 } 1581 ifp->if_capenable = ifp->if_capabilities; 1582 1583 /* Set up MII bus. */ 1584 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1585 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1586 MIIF_DOPAUSE); 1587 if (error != 0) { 1588 device_printf(dev, "attaching PHYs failed\n"); 1589 goto fail; 1590 } 1591 1592 ether_ifattach(ifp, sc->alc_eaddr); 1593 1594 /* VLAN capability setup. */ 1595 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1596 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1597 ifp->if_capenable = ifp->if_capabilities; 1598 /* 1599 * XXX 1600 * It seems enabling Tx checksum offloading makes more trouble. 1601 * Sometimes the controller does not receive any frames when 1602 * Tx checksum offloading is enabled. I'm not sure whether this 1603 * is a bug in Tx checksum offloading logic or I got broken 1604 * sample boards. To safety, don't enable Tx checksum offloading 1605 * by default but give chance to users to toggle it if they know 1606 * their controllers work without problems. 1607 * Fortunately, Tx checksum offloading for AR816x family 1608 * seems to work. 1609 */ 1610 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1611 ifp->if_capenable &= ~IFCAP_TXCSUM; 1612 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1613 } 1614 1615 /* Tell the upper layer(s) we support long frames. */ 1616 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1617 1618 /* Create local taskq. */ 1619 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1620 taskqueue_thread_enqueue, &sc->alc_tq); 1621 if (sc->alc_tq == NULL) { 1622 device_printf(dev, "could not create taskqueue.\n"); 1623 ether_ifdetach(ifp); 1624 error = ENXIO; 1625 goto fail; 1626 } 1627 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1628 device_get_nameunit(sc->alc_dev)); 1629 1630 alc_config_msi(sc); 1631 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1632 msic = ALC_MSIX_MESSAGES; 1633 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1634 msic = ALC_MSI_MESSAGES; 1635 else 1636 msic = 1; 1637 for (i = 0; i < msic; i++) { 1638 error = bus_setup_intr(dev, sc->alc_irq[i], 1639 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1640 &sc->alc_intrhand[i]); 1641 if (error != 0) 1642 break; 1643 } 1644 if (error != 0) { 1645 device_printf(dev, "could not set up interrupt handler.\n"); 1646 taskqueue_free(sc->alc_tq); 1647 sc->alc_tq = NULL; 1648 ether_ifdetach(ifp); 1649 goto fail; 1650 } 1651 1652fail: 1653 if (error != 0) 1654 alc_detach(dev); 1655 1656 return (error); 1657} 1658 1659static int 1660alc_detach(device_t dev) 1661{ 1662 struct alc_softc *sc; 1663 struct ifnet *ifp; 1664 int i, msic; 1665 1666 sc = device_get_softc(dev); 1667 1668 ifp = sc->alc_ifp; 1669 if (device_is_attached(dev)) { 1670 ether_ifdetach(ifp); 1671 ALC_LOCK(sc); 1672 alc_stop(sc); 1673 ALC_UNLOCK(sc); 1674 callout_drain(&sc->alc_tick_ch); 1675 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1676 } 1677 1678 if (sc->alc_tq != NULL) { 1679 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1680 taskqueue_free(sc->alc_tq); 1681 sc->alc_tq = NULL; 1682 } 1683 1684 if (sc->alc_miibus != NULL) { 1685 device_delete_child(dev, sc->alc_miibus); 1686 sc->alc_miibus = NULL; 1687 } 1688 bus_generic_detach(dev); 1689 alc_dma_free(sc); 1690 1691 if (ifp != NULL) { 1692 if_free(ifp); 1693 sc->alc_ifp = NULL; 1694 } 1695 1696 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1697 msic = ALC_MSIX_MESSAGES; 1698 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1699 msic = ALC_MSI_MESSAGES; 1700 else 1701 msic = 1; 1702 for (i = 0; i < msic; i++) { 1703 if (sc->alc_intrhand[i] != NULL) { 1704 bus_teardown_intr(dev, sc->alc_irq[i], 1705 sc->alc_intrhand[i]); 1706 sc->alc_intrhand[i] = NULL; 1707 } 1708 } 1709 if (sc->alc_res[0] != NULL) 1710 alc_phy_down(sc); 1711 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1712 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1713 pci_release_msi(dev); 1714 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1715 mtx_destroy(&sc->alc_mtx); 1716 1717 return (0); 1718} 1719 1720#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1721 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1722#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1723 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1724 1725static void 1726alc_sysctl_node(struct alc_softc *sc) 1727{ 1728 struct sysctl_ctx_list *ctx; 1729 struct sysctl_oid_list *child, *parent; 1730 struct sysctl_oid *tree; 1731 struct alc_hw_stats *stats; 1732 int error; 1733 1734 stats = &sc->alc_stats; 1735 ctx = device_get_sysctl_ctx(sc->alc_dev); 1736 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1737 1738 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1739 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1740 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1741 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1742 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1743 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1744 /* Pull in device tunables. */ 1745 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1746 error = resource_int_value(device_get_name(sc->alc_dev), 1747 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1748 if (error == 0) { 1749 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1750 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1751 device_printf(sc->alc_dev, "int_rx_mod value out of " 1752 "range; using default: %d\n", 1753 ALC_IM_RX_TIMER_DEFAULT); 1754 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1755 } 1756 } 1757 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1758 error = resource_int_value(device_get_name(sc->alc_dev), 1759 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1760 if (error == 0) { 1761 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1762 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1763 device_printf(sc->alc_dev, "int_tx_mod value out of " 1764 "range; using default: %d\n", 1765 ALC_IM_TX_TIMER_DEFAULT); 1766 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1767 } 1768 } 1769 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1770 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1771 sysctl_hw_alc_proc_limit, "I", 1772 "max number of Rx events to process"); 1773 /* Pull in device tunables. */ 1774 sc->alc_process_limit = ALC_PROC_DEFAULT; 1775 error = resource_int_value(device_get_name(sc->alc_dev), 1776 device_get_unit(sc->alc_dev), "process_limit", 1777 &sc->alc_process_limit); 1778 if (error == 0) { 1779 if (sc->alc_process_limit < ALC_PROC_MIN || 1780 sc->alc_process_limit > ALC_PROC_MAX) { 1781 device_printf(sc->alc_dev, 1782 "process_limit value out of range; " 1783 "using default: %d\n", ALC_PROC_DEFAULT); 1784 sc->alc_process_limit = ALC_PROC_DEFAULT; 1785 } 1786 } 1787 1788 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1789 NULL, "ALC statistics"); 1790 parent = SYSCTL_CHILDREN(tree); 1791 1792 /* Rx statistics. */ 1793 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1794 NULL, "Rx MAC statistics"); 1795 child = SYSCTL_CHILDREN(tree); 1796 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1797 &stats->rx_frames, "Good frames"); 1798 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1799 &stats->rx_bcast_frames, "Good broadcast frames"); 1800 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1801 &stats->rx_mcast_frames, "Good multicast frames"); 1802 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1803 &stats->rx_pause_frames, "Pause control frames"); 1804 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1805 &stats->rx_control_frames, "Control frames"); 1806 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1807 &stats->rx_crcerrs, "CRC errors"); 1808 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1809 &stats->rx_lenerrs, "Frames with length mismatched"); 1810 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1811 &stats->rx_bytes, "Good octets"); 1812 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1813 &stats->rx_bcast_bytes, "Good broadcast octets"); 1814 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1815 &stats->rx_mcast_bytes, "Good multicast octets"); 1816 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1817 &stats->rx_runts, "Too short frames"); 1818 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1819 &stats->rx_fragments, "Fragmented frames"); 1820 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1821 &stats->rx_pkts_64, "64 bytes frames"); 1822 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1823 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1824 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1825 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1826 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1827 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1828 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1829 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1830 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1831 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1832 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1833 &stats->rx_pkts_1519_max, "1519 to max frames"); 1834 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1835 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1836 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1837 &stats->rx_fifo_oflows, "FIFO overflows"); 1838 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1839 &stats->rx_rrs_errs, "Return status write-back errors"); 1840 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1841 &stats->rx_alignerrs, "Alignment errors"); 1842 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1843 &stats->rx_pkts_filtered, 1844 "Frames dropped due to address filtering"); 1845 1846 /* Tx statistics. */ 1847 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1848 NULL, "Tx MAC statistics"); 1849 child = SYSCTL_CHILDREN(tree); 1850 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1851 &stats->tx_frames, "Good frames"); 1852 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1853 &stats->tx_bcast_frames, "Good broadcast frames"); 1854 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1855 &stats->tx_mcast_frames, "Good multicast frames"); 1856 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1857 &stats->tx_pause_frames, "Pause control frames"); 1858 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1859 &stats->tx_control_frames, "Control frames"); 1860 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1861 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1862 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1863 &stats->tx_excess_defer, "Frames with derferrals"); 1864 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1865 &stats->tx_bytes, "Good octets"); 1866 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1867 &stats->tx_bcast_bytes, "Good broadcast octets"); 1868 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1869 &stats->tx_mcast_bytes, "Good multicast octets"); 1870 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1871 &stats->tx_pkts_64, "64 bytes frames"); 1872 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1873 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1874 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1875 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1876 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1877 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1878 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1879 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1880 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1881 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1882 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1883 &stats->tx_pkts_1519_max, "1519 to max frames"); 1884 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1885 &stats->tx_single_colls, "Single collisions"); 1886 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1887 &stats->tx_multi_colls, "Multiple collisions"); 1888 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1889 &stats->tx_late_colls, "Late collisions"); 1890 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1891 &stats->tx_excess_colls, "Excessive collisions"); 1892 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1893 &stats->tx_underrun, "FIFO underruns"); 1894 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1895 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1896 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1897 &stats->tx_lenerrs, "Frames with length mismatched"); 1898 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1899 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1900} 1901 1902#undef ALC_SYSCTL_STAT_ADD32 1903#undef ALC_SYSCTL_STAT_ADD64 1904 1905struct alc_dmamap_arg { 1906 bus_addr_t alc_busaddr; 1907}; 1908 1909static void 1910alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1911{ 1912 struct alc_dmamap_arg *ctx; 1913 1914 if (error != 0) 1915 return; 1916 1917 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1918 1919 ctx = (struct alc_dmamap_arg *)arg; 1920 ctx->alc_busaddr = segs[0].ds_addr; 1921} 1922 1923/* 1924 * Normal and high Tx descriptors shares single Tx high address. 1925 * Four Rx descriptor/return rings and CMB shares the same Rx 1926 * high address. 1927 */ 1928static int 1929alc_check_boundary(struct alc_softc *sc) 1930{ 1931 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1932 1933 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1934 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1935 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1936 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1937 1938 /* 4GB boundary crossing is not allowed. */ 1939 if ((ALC_ADDR_HI(rx_ring_end) != 1940 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1941 (ALC_ADDR_HI(rr_ring_end) != 1942 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1943 (ALC_ADDR_HI(cmb_end) != 1944 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1945 (ALC_ADDR_HI(tx_ring_end) != 1946 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1947 return (EFBIG); 1948 /* 1949 * Make sure Rx return descriptor/Rx descriptor/CMB use 1950 * the same high address. 1951 */ 1952 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1953 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1954 return (EFBIG); 1955 1956 return (0); 1957} 1958 1959static int 1960alc_dma_alloc(struct alc_softc *sc) 1961{ 1962 struct alc_txdesc *txd; 1963 struct alc_rxdesc *rxd; 1964 bus_addr_t lowaddr; 1965 struct alc_dmamap_arg ctx; 1966 int error, i; 1967 1968 lowaddr = BUS_SPACE_MAXADDR; 1969again: 1970 /* Create parent DMA tag. */ 1971 error = bus_dma_tag_create( 1972 bus_get_dma_tag(sc->alc_dev), /* parent */ 1973 1, 0, /* alignment, boundary */ 1974 lowaddr, /* lowaddr */ 1975 BUS_SPACE_MAXADDR, /* highaddr */ 1976 NULL, NULL, /* filter, filterarg */ 1977 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1978 0, /* nsegments */ 1979 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1980 0, /* flags */ 1981 NULL, NULL, /* lockfunc, lockarg */ 1982 &sc->alc_cdata.alc_parent_tag); 1983 if (error != 0) { 1984 device_printf(sc->alc_dev, 1985 "could not create parent DMA tag.\n"); 1986 goto fail; 1987 } 1988 1989 /* Create DMA tag for Tx descriptor ring. */ 1990 error = bus_dma_tag_create( 1991 sc->alc_cdata.alc_parent_tag, /* parent */ 1992 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1993 BUS_SPACE_MAXADDR, /* lowaddr */ 1994 BUS_SPACE_MAXADDR, /* highaddr */ 1995 NULL, NULL, /* filter, filterarg */ 1996 ALC_TX_RING_SZ, /* maxsize */ 1997 1, /* nsegments */ 1998 ALC_TX_RING_SZ, /* maxsegsize */ 1999 0, /* flags */ 2000 NULL, NULL, /* lockfunc, lockarg */ 2001 &sc->alc_cdata.alc_tx_ring_tag); 2002 if (error != 0) { 2003 device_printf(sc->alc_dev, 2004 "could not create Tx ring DMA tag.\n"); 2005 goto fail; 2006 } 2007 2008 /* Create DMA tag for Rx free descriptor ring. */ 2009 error = bus_dma_tag_create( 2010 sc->alc_cdata.alc_parent_tag, /* parent */ 2011 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2012 BUS_SPACE_MAXADDR, /* lowaddr */ 2013 BUS_SPACE_MAXADDR, /* highaddr */ 2014 NULL, NULL, /* filter, filterarg */ 2015 ALC_RX_RING_SZ, /* maxsize */ 2016 1, /* nsegments */ 2017 ALC_RX_RING_SZ, /* maxsegsize */ 2018 0, /* flags */ 2019 NULL, NULL, /* lockfunc, lockarg */ 2020 &sc->alc_cdata.alc_rx_ring_tag); 2021 if (error != 0) { 2022 device_printf(sc->alc_dev, 2023 "could not create Rx ring DMA tag.\n"); 2024 goto fail; 2025 } 2026 /* Create DMA tag for Rx return descriptor ring. */ 2027 error = bus_dma_tag_create( 2028 sc->alc_cdata.alc_parent_tag, /* parent */ 2029 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2030 BUS_SPACE_MAXADDR, /* lowaddr */ 2031 BUS_SPACE_MAXADDR, /* highaddr */ 2032 NULL, NULL, /* filter, filterarg */ 2033 ALC_RR_RING_SZ, /* maxsize */ 2034 1, /* nsegments */ 2035 ALC_RR_RING_SZ, /* maxsegsize */ 2036 0, /* flags */ 2037 NULL, NULL, /* lockfunc, lockarg */ 2038 &sc->alc_cdata.alc_rr_ring_tag); 2039 if (error != 0) { 2040 device_printf(sc->alc_dev, 2041 "could not create Rx return ring DMA tag.\n"); 2042 goto fail; 2043 } 2044 2045 /* Create DMA tag for coalescing message block. */ 2046 error = bus_dma_tag_create( 2047 sc->alc_cdata.alc_parent_tag, /* parent */ 2048 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2049 BUS_SPACE_MAXADDR, /* lowaddr */ 2050 BUS_SPACE_MAXADDR, /* highaddr */ 2051 NULL, NULL, /* filter, filterarg */ 2052 ALC_CMB_SZ, /* maxsize */ 2053 1, /* nsegments */ 2054 ALC_CMB_SZ, /* maxsegsize */ 2055 0, /* flags */ 2056 NULL, NULL, /* lockfunc, lockarg */ 2057 &sc->alc_cdata.alc_cmb_tag); 2058 if (error != 0) { 2059 device_printf(sc->alc_dev, 2060 "could not create CMB DMA tag.\n"); 2061 goto fail; 2062 } 2063 /* Create DMA tag for status message block. */ 2064 error = bus_dma_tag_create( 2065 sc->alc_cdata.alc_parent_tag, /* parent */ 2066 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2067 BUS_SPACE_MAXADDR, /* lowaddr */ 2068 BUS_SPACE_MAXADDR, /* highaddr */ 2069 NULL, NULL, /* filter, filterarg */ 2070 ALC_SMB_SZ, /* maxsize */ 2071 1, /* nsegments */ 2072 ALC_SMB_SZ, /* maxsegsize */ 2073 0, /* flags */ 2074 NULL, NULL, /* lockfunc, lockarg */ 2075 &sc->alc_cdata.alc_smb_tag); 2076 if (error != 0) { 2077 device_printf(sc->alc_dev, 2078 "could not create SMB DMA tag.\n"); 2079 goto fail; 2080 } 2081 2082 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2083 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2084 (void **)&sc->alc_rdata.alc_tx_ring, 2085 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2086 &sc->alc_cdata.alc_tx_ring_map); 2087 if (error != 0) { 2088 device_printf(sc->alc_dev, 2089 "could not allocate DMA'able memory for Tx ring.\n"); 2090 goto fail; 2091 } 2092 ctx.alc_busaddr = 0; 2093 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2094 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2095 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2096 if (error != 0 || ctx.alc_busaddr == 0) { 2097 device_printf(sc->alc_dev, 2098 "could not load DMA'able memory for Tx ring.\n"); 2099 goto fail; 2100 } 2101 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2102 2103 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2104 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2105 (void **)&sc->alc_rdata.alc_rx_ring, 2106 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2107 &sc->alc_cdata.alc_rx_ring_map); 2108 if (error != 0) { 2109 device_printf(sc->alc_dev, 2110 "could not allocate DMA'able memory for Rx ring.\n"); 2111 goto fail; 2112 } 2113 ctx.alc_busaddr = 0; 2114 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2115 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2116 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2117 if (error != 0 || ctx.alc_busaddr == 0) { 2118 device_printf(sc->alc_dev, 2119 "could not load DMA'able memory for Rx ring.\n"); 2120 goto fail; 2121 } 2122 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2123 2124 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2125 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2126 (void **)&sc->alc_rdata.alc_rr_ring, 2127 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2128 &sc->alc_cdata.alc_rr_ring_map); 2129 if (error != 0) { 2130 device_printf(sc->alc_dev, 2131 "could not allocate DMA'able memory for Rx return ring.\n"); 2132 goto fail; 2133 } 2134 ctx.alc_busaddr = 0; 2135 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2136 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2137 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2138 if (error != 0 || ctx.alc_busaddr == 0) { 2139 device_printf(sc->alc_dev, 2140 "could not load DMA'able memory for Tx ring.\n"); 2141 goto fail; 2142 } 2143 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2144 2145 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2146 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2147 (void **)&sc->alc_rdata.alc_cmb, 2148 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2149 &sc->alc_cdata.alc_cmb_map); 2150 if (error != 0) { 2151 device_printf(sc->alc_dev, 2152 "could not allocate DMA'able memory for CMB.\n"); 2153 goto fail; 2154 } 2155 ctx.alc_busaddr = 0; 2156 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2157 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2158 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2159 if (error != 0 || ctx.alc_busaddr == 0) { 2160 device_printf(sc->alc_dev, 2161 "could not load DMA'able memory for CMB.\n"); 2162 goto fail; 2163 } 2164 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2165 2166 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2167 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2168 (void **)&sc->alc_rdata.alc_smb, 2169 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2170 &sc->alc_cdata.alc_smb_map); 2171 if (error != 0) { 2172 device_printf(sc->alc_dev, 2173 "could not allocate DMA'able memory for SMB.\n"); 2174 goto fail; 2175 } 2176 ctx.alc_busaddr = 0; 2177 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2178 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2179 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2180 if (error != 0 || ctx.alc_busaddr == 0) { 2181 device_printf(sc->alc_dev, 2182 "could not load DMA'able memory for CMB.\n"); 2183 goto fail; 2184 } 2185 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2186 2187 /* Make sure we've not crossed 4GB boundary. */ 2188 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2189 (error = alc_check_boundary(sc)) != 0) { 2190 device_printf(sc->alc_dev, "4GB boundary crossed, " 2191 "switching to 32bit DMA addressing mode.\n"); 2192 alc_dma_free(sc); 2193 /* 2194 * Limit max allowable DMA address space to 32bit 2195 * and try again. 2196 */ 2197 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2198 goto again; 2199 } 2200 2201 /* 2202 * Create Tx buffer parent tag. 2203 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2204 * so it needs separate parent DMA tag as parent DMA address 2205 * space could be restricted to be within 32bit address space 2206 * by 4GB boundary crossing. 2207 */ 2208 error = bus_dma_tag_create( 2209 bus_get_dma_tag(sc->alc_dev), /* parent */ 2210 1, 0, /* alignment, boundary */ 2211 BUS_SPACE_MAXADDR, /* lowaddr */ 2212 BUS_SPACE_MAXADDR, /* highaddr */ 2213 NULL, NULL, /* filter, filterarg */ 2214 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2215 0, /* nsegments */ 2216 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2217 0, /* flags */ 2218 NULL, NULL, /* lockfunc, lockarg */ 2219 &sc->alc_cdata.alc_buffer_tag); 2220 if (error != 0) { 2221 device_printf(sc->alc_dev, 2222 "could not create parent buffer DMA tag.\n"); 2223 goto fail; 2224 } 2225 2226 /* Create DMA tag for Tx buffers. */ 2227 error = bus_dma_tag_create( 2228 sc->alc_cdata.alc_buffer_tag, /* parent */ 2229 1, 0, /* alignment, boundary */ 2230 BUS_SPACE_MAXADDR, /* lowaddr */ 2231 BUS_SPACE_MAXADDR, /* highaddr */ 2232 NULL, NULL, /* filter, filterarg */ 2233 ALC_TSO_MAXSIZE, /* maxsize */ 2234 ALC_MAXTXSEGS, /* nsegments */ 2235 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2236 0, /* flags */ 2237 NULL, NULL, /* lockfunc, lockarg */ 2238 &sc->alc_cdata.alc_tx_tag); 2239 if (error != 0) { 2240 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2241 goto fail; 2242 } 2243 2244 /* Create DMA tag for Rx buffers. */ 2245 error = bus_dma_tag_create( 2246 sc->alc_cdata.alc_buffer_tag, /* parent */ 2247 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2248 BUS_SPACE_MAXADDR, /* lowaddr */ 2249 BUS_SPACE_MAXADDR, /* highaddr */ 2250 NULL, NULL, /* filter, filterarg */ 2251 MCLBYTES, /* maxsize */ 2252 1, /* nsegments */ 2253 MCLBYTES, /* maxsegsize */ 2254 0, /* flags */ 2255 NULL, NULL, /* lockfunc, lockarg */ 2256 &sc->alc_cdata.alc_rx_tag); 2257 if (error != 0) { 2258 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2259 goto fail; 2260 } 2261 /* Create DMA maps for Tx buffers. */ 2262 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2263 txd = &sc->alc_cdata.alc_txdesc[i]; 2264 txd->tx_m = NULL; 2265 txd->tx_dmamap = NULL; 2266 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2267 &txd->tx_dmamap); 2268 if (error != 0) { 2269 device_printf(sc->alc_dev, 2270 "could not create Tx dmamap.\n"); 2271 goto fail; 2272 } 2273 } 2274 /* Create DMA maps for Rx buffers. */ 2275 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2276 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2277 device_printf(sc->alc_dev, 2278 "could not create spare Rx dmamap.\n"); 2279 goto fail; 2280 } 2281 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2282 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2283 rxd->rx_m = NULL; 2284 rxd->rx_dmamap = NULL; 2285 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2286 &rxd->rx_dmamap); 2287 if (error != 0) { 2288 device_printf(sc->alc_dev, 2289 "could not create Rx dmamap.\n"); 2290 goto fail; 2291 } 2292 } 2293 2294fail: 2295 return (error); 2296} 2297 2298static void 2299alc_dma_free(struct alc_softc *sc) 2300{ 2301 struct alc_txdesc *txd; 2302 struct alc_rxdesc *rxd; 2303 int i; 2304 2305 /* Tx buffers. */ 2306 if (sc->alc_cdata.alc_tx_tag != NULL) { 2307 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2308 txd = &sc->alc_cdata.alc_txdesc[i]; 2309 if (txd->tx_dmamap != NULL) { 2310 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2311 txd->tx_dmamap); 2312 txd->tx_dmamap = NULL; 2313 } 2314 } 2315 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2316 sc->alc_cdata.alc_tx_tag = NULL; 2317 } 2318 /* Rx buffers */ 2319 if (sc->alc_cdata.alc_rx_tag != NULL) { 2320 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2321 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2322 if (rxd->rx_dmamap != NULL) { 2323 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2324 rxd->rx_dmamap); 2325 rxd->rx_dmamap = NULL; 2326 } 2327 } 2328 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2329 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2330 sc->alc_cdata.alc_rx_sparemap); 2331 sc->alc_cdata.alc_rx_sparemap = NULL; 2332 } 2333 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2334 sc->alc_cdata.alc_rx_tag = NULL; 2335 } 2336 /* Tx descriptor ring. */ 2337 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2338 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2339 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2340 sc->alc_cdata.alc_tx_ring_map); 2341 if (sc->alc_rdata.alc_tx_ring != NULL) 2342 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2343 sc->alc_rdata.alc_tx_ring, 2344 sc->alc_cdata.alc_tx_ring_map); 2345 sc->alc_rdata.alc_tx_ring_paddr = 0; 2346 sc->alc_rdata.alc_tx_ring = NULL; 2347 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2348 sc->alc_cdata.alc_tx_ring_tag = NULL; 2349 } 2350 /* Rx ring. */ 2351 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2352 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2353 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2354 sc->alc_cdata.alc_rx_ring_map); 2355 if (sc->alc_rdata.alc_rx_ring != NULL) 2356 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2357 sc->alc_rdata.alc_rx_ring, 2358 sc->alc_cdata.alc_rx_ring_map); 2359 sc->alc_rdata.alc_rx_ring_paddr = 0; 2360 sc->alc_rdata.alc_rx_ring = NULL; 2361 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2362 sc->alc_cdata.alc_rx_ring_tag = NULL; 2363 } 2364 /* Rx return ring. */ 2365 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2366 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2367 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2368 sc->alc_cdata.alc_rr_ring_map); 2369 if (sc->alc_rdata.alc_rr_ring != NULL) 2370 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2371 sc->alc_rdata.alc_rr_ring, 2372 sc->alc_cdata.alc_rr_ring_map); 2373 sc->alc_rdata.alc_rr_ring_paddr = 0; 2374 sc->alc_rdata.alc_rr_ring = NULL; 2375 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2376 sc->alc_cdata.alc_rr_ring_tag = NULL; 2377 } 2378 /* CMB block */ 2379 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2380 if (sc->alc_rdata.alc_cmb_paddr != 0) 2381 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2382 sc->alc_cdata.alc_cmb_map); 2383 if (sc->alc_rdata.alc_cmb != NULL) 2384 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2385 sc->alc_rdata.alc_cmb, 2386 sc->alc_cdata.alc_cmb_map); 2387 sc->alc_rdata.alc_cmb_paddr = 0; 2388 sc->alc_rdata.alc_cmb = NULL; 2389 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2390 sc->alc_cdata.alc_cmb_tag = NULL; 2391 } 2392 /* SMB block */ 2393 if (sc->alc_cdata.alc_smb_tag != NULL) { 2394 if (sc->alc_rdata.alc_smb_paddr != 0) 2395 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2396 sc->alc_cdata.alc_smb_map); 2397 if (sc->alc_rdata.alc_smb != NULL) 2398 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2399 sc->alc_rdata.alc_smb, 2400 sc->alc_cdata.alc_smb_map); 2401 sc->alc_rdata.alc_smb_paddr = 0; 2402 sc->alc_rdata.alc_smb = NULL; 2403 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2404 sc->alc_cdata.alc_smb_tag = NULL; 2405 } 2406 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2407 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2408 sc->alc_cdata.alc_buffer_tag = NULL; 2409 } 2410 if (sc->alc_cdata.alc_parent_tag != NULL) { 2411 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2412 sc->alc_cdata.alc_parent_tag = NULL; 2413 } 2414} 2415 2416static int 2417alc_shutdown(device_t dev) 2418{ 2419 2420 return (alc_suspend(dev)); 2421} 2422 2423/* 2424 * Note, this driver resets the link speed to 10/100Mbps by 2425 * restarting auto-negotiation in suspend/shutdown phase but we 2426 * don't know whether that auto-negotiation would succeed or not 2427 * as driver has no control after powering off/suspend operation. 2428 * If the renegotiation fail WOL may not work. Running at 1Gbps 2429 * will draw more power than 375mA at 3.3V which is specified in 2430 * PCI specification and that would result in complete 2431 * shutdowning power to ethernet controller. 2432 * 2433 * TODO 2434 * Save current negotiated media speed/duplex/flow-control to 2435 * softc and restore the same link again after resuming. PHY 2436 * handling such as power down/resetting to 100Mbps may be better 2437 * handled in suspend method in phy driver. 2438 */ 2439static void 2440alc_setlinkspeed(struct alc_softc *sc) 2441{ 2442 struct mii_data *mii; 2443 int aneg, i; 2444 2445 mii = device_get_softc(sc->alc_miibus); 2446 mii_pollstat(mii); 2447 aneg = 0; 2448 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2449 (IFM_ACTIVE | IFM_AVALID)) { 2450 switch IFM_SUBTYPE(mii->mii_media_active) { 2451 case IFM_10_T: 2452 case IFM_100_TX: 2453 return; 2454 case IFM_1000_T: 2455 aneg++; 2456 break; 2457 default: 2458 break; 2459 } 2460 } 2461 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2462 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2463 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2464 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2465 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2466 DELAY(1000); 2467 if (aneg != 0) { 2468 /* 2469 * Poll link state until alc(4) get a 10/100Mbps link. 2470 */ 2471 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2472 mii_pollstat(mii); 2473 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2474 == (IFM_ACTIVE | IFM_AVALID)) { 2475 switch (IFM_SUBTYPE( 2476 mii->mii_media_active)) { 2477 case IFM_10_T: 2478 case IFM_100_TX: 2479 alc_mac_config(sc); 2480 return; 2481 default: 2482 break; 2483 } 2484 } 2485 ALC_UNLOCK(sc); 2486 pause("alclnk", hz); 2487 ALC_LOCK(sc); 2488 } 2489 if (i == MII_ANEGTICKS_GIGE) 2490 device_printf(sc->alc_dev, 2491 "establishing a link failed, WOL may not work!"); 2492 } 2493 /* 2494 * No link, force MAC to have 100Mbps, full-duplex link. 2495 * This is the last resort and may/may not work. 2496 */ 2497 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2498 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2499 alc_mac_config(sc); 2500} 2501 2502static void 2503alc_setwol(struct alc_softc *sc) 2504{ 2505 2506 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2507 alc_setwol_816x(sc); 2508 else 2509 alc_setwol_813x(sc); 2510} 2511 2512static void 2513alc_setwol_813x(struct alc_softc *sc) 2514{ 2515 struct ifnet *ifp; 2516 uint32_t reg, pmcs; 2517 uint16_t pmstat; 2518 2519 ALC_LOCK_ASSERT(sc); 2520 2521 alc_disable_l0s_l1(sc); 2522 ifp = sc->alc_ifp; 2523 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2524 /* Disable WOL. */ 2525 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2526 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2527 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2528 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2529 /* Force PHY power down. */ 2530 alc_phy_down(sc); 2531 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2532 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2533 return; 2534 } 2535 2536 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2537 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2538 alc_setlinkspeed(sc); 2539 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2540 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2541 } 2542 2543 pmcs = 0; 2544 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2545 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2546 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2547 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2548 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2549 MAC_CFG_BCAST); 2550 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2551 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2552 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2553 reg |= MAC_CFG_RX_ENB; 2554 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2555 2556 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2557 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2558 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2559 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2560 /* WOL disabled, PHY power down. */ 2561 alc_phy_down(sc); 2562 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2563 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2564 } 2565 /* Request PME. */ 2566 pmstat = pci_read_config(sc->alc_dev, 2567 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2568 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2569 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2570 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2571 pci_write_config(sc->alc_dev, 2572 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2573} 2574 2575static void 2576alc_setwol_816x(struct alc_softc *sc) 2577{ 2578 struct ifnet *ifp; 2579 uint32_t gphy, mac, master, pmcs, reg; 2580 uint16_t pmstat; 2581 2582 ALC_LOCK_ASSERT(sc); 2583 2584 ifp = sc->alc_ifp; 2585 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2586 master &= ~MASTER_CLK_SEL_DIS; 2587 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2588 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2589 GPHY_CFG_PHY_PLL_ON); 2590 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2591 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2592 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2593 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2594 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2595 } else { 2596 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2597 gphy |= GPHY_CFG_EXT_RESET; 2598 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2599 alc_setlinkspeed(sc); 2600 } 2601 pmcs = 0; 2602 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2603 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2604 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2605 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2606 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2607 MAC_CFG_BCAST); 2608 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2609 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2610 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2611 mac |= MAC_CFG_RX_ENB; 2612 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2613 ANEG_S3DIG10_SL); 2614 } 2615 2616 /* Enable OSC. */ 2617 reg = CSR_READ_4(sc, ALC_MISC); 2618 reg &= ~MISC_INTNLOSC_OPEN; 2619 CSR_WRITE_4(sc, ALC_MISC, reg); 2620 reg |= MISC_INTNLOSC_OPEN; 2621 CSR_WRITE_4(sc, ALC_MISC, reg); 2622 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2623 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2624 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2625 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2626 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2627 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2628 2629 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2630 /* Request PME. */ 2631 pmstat = pci_read_config(sc->alc_dev, 2632 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2633 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2634 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2635 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2636 pci_write_config(sc->alc_dev, 2637 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2638 } 2639} 2640 2641static int 2642alc_suspend(device_t dev) 2643{ 2644 struct alc_softc *sc; 2645 2646 sc = device_get_softc(dev); 2647 2648 ALC_LOCK(sc); 2649 alc_stop(sc); 2650 alc_setwol(sc); 2651 ALC_UNLOCK(sc); 2652 2653 return (0); 2654} 2655 2656static int 2657alc_resume(device_t dev) 2658{ 2659 struct alc_softc *sc; 2660 struct ifnet *ifp; 2661 uint16_t pmstat; 2662 2663 sc = device_get_softc(dev); 2664 2665 ALC_LOCK(sc); 2666 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2667 /* Disable PME and clear PME status. */ 2668 pmstat = pci_read_config(sc->alc_dev, 2669 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2670 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2671 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2672 pci_write_config(sc->alc_dev, 2673 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2674 } 2675 } 2676 /* Reset PHY. */ 2677 alc_phy_reset(sc); 2678 ifp = sc->alc_ifp; 2679 if ((ifp->if_flags & IFF_UP) != 0) { 2680 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2681 alc_init_locked(sc); 2682 } 2683 ALC_UNLOCK(sc); 2684 2685 return (0); 2686} 2687 2688static int 2689alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2690{ 2691 struct alc_txdesc *txd, *txd_last; 2692 struct tx_desc *desc; 2693 struct mbuf *m; 2694 struct ip *ip; 2695 struct tcphdr *tcp; 2696 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2697 bus_dmamap_t map; 2698 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2699 int error, idx, nsegs, prod; 2700 2701 ALC_LOCK_ASSERT(sc); 2702 2703 M_ASSERTPKTHDR((*m_head)); 2704 2705 m = *m_head; 2706 ip = NULL; 2707 tcp = NULL; 2708 ip_off = poff = 0; 2709 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2710 /* 2711 * AR81[3567]x requires offset of TCP/UDP header in its 2712 * Tx descriptor to perform Tx checksum offloading. TSO 2713 * also requires TCP header offset and modification of 2714 * IP/TCP header. This kind of operation takes many CPU 2715 * cycles on FreeBSD so fast host CPU is required to get 2716 * smooth TSO performance. 2717 */ 2718 struct ether_header *eh; 2719 2720 if (M_WRITABLE(m) == 0) { 2721 /* Get a writable copy. */ 2722 m = m_dup(*m_head, M_NOWAIT); 2723 /* Release original mbufs. */ 2724 m_freem(*m_head); 2725 if (m == NULL) { 2726 *m_head = NULL; 2727 return (ENOBUFS); 2728 } 2729 *m_head = m; 2730 } 2731 2732 ip_off = sizeof(struct ether_header); 2733 m = m_pullup(m, ip_off); 2734 if (m == NULL) { 2735 *m_head = NULL; 2736 return (ENOBUFS); 2737 } 2738 eh = mtod(m, struct ether_header *); 2739 /* 2740 * Check if hardware VLAN insertion is off. 2741 * Additional check for LLC/SNAP frame? 2742 */ 2743 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2744 ip_off = sizeof(struct ether_vlan_header); 2745 m = m_pullup(m, ip_off); 2746 if (m == NULL) { 2747 *m_head = NULL; 2748 return (ENOBUFS); 2749 } 2750 } 2751 m = m_pullup(m, ip_off + sizeof(struct ip)); 2752 if (m == NULL) { 2753 *m_head = NULL; 2754 return (ENOBUFS); 2755 } 2756 ip = (struct ip *)(mtod(m, char *) + ip_off); 2757 poff = ip_off + (ip->ip_hl << 2); 2758 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2759 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2760 if (m == NULL) { 2761 *m_head = NULL; 2762 return (ENOBUFS); 2763 } 2764 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2765 m = m_pullup(m, poff + (tcp->th_off << 2)); 2766 if (m == NULL) { 2767 *m_head = NULL; 2768 return (ENOBUFS); 2769 } 2770 /* 2771 * Due to strict adherence of Microsoft NDIS 2772 * Large Send specification, hardware expects 2773 * a pseudo TCP checksum inserted by upper 2774 * stack. Unfortunately the pseudo TCP 2775 * checksum that NDIS refers to does not include 2776 * TCP payload length so driver should recompute 2777 * the pseudo checksum here. Hopefully this 2778 * wouldn't be much burden on modern CPUs. 2779 * 2780 * Reset IP checksum and recompute TCP pseudo 2781 * checksum as NDIS specification said. 2782 */ 2783 ip = (struct ip *)(mtod(m, char *) + ip_off); 2784 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2785 ip->ip_sum = 0; 2786 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2787 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2788 } 2789 *m_head = m; 2790 } 2791 2792 prod = sc->alc_cdata.alc_tx_prod; 2793 txd = &sc->alc_cdata.alc_txdesc[prod]; 2794 txd_last = txd; 2795 map = txd->tx_dmamap; 2796 2797 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2798 *m_head, txsegs, &nsegs, 0); 2799 if (error == EFBIG) { 2800 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2801 if (m == NULL) { 2802 m_freem(*m_head); 2803 *m_head = NULL; 2804 return (ENOMEM); 2805 } 2806 *m_head = m; 2807 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2808 *m_head, txsegs, &nsegs, 0); 2809 if (error != 0) { 2810 m_freem(*m_head); 2811 *m_head = NULL; 2812 return (error); 2813 } 2814 } else if (error != 0) 2815 return (error); 2816 if (nsegs == 0) { 2817 m_freem(*m_head); 2818 *m_head = NULL; 2819 return (EIO); 2820 } 2821 2822 /* Check descriptor overrun. */ 2823 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2824 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2825 return (ENOBUFS); 2826 } 2827 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2828 2829 m = *m_head; 2830 cflags = TD_ETHERNET; 2831 vtag = 0; 2832 desc = NULL; 2833 idx = 0; 2834 /* Configure VLAN hardware tag insertion. */ 2835 if ((m->m_flags & M_VLANTAG) != 0) { 2836 vtag = htons(m->m_pkthdr.ether_vtag); 2837 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2838 cflags |= TD_INS_VLAN_TAG; 2839 } 2840 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2841 /* Request TSO and set MSS. */ 2842 cflags |= TD_TSO | TD_TSO_DESCV1; 2843 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2844 TD_MSS_MASK; 2845 /* Set TCP header offset. */ 2846 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2847 TD_TCPHDR_OFFSET_MASK; 2848 /* 2849 * AR81[3567]x requires the first buffer should 2850 * only hold IP/TCP header data. Payload should 2851 * be handled in other descriptors. 2852 */ 2853 hdrlen = poff + (tcp->th_off << 2); 2854 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2855 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2856 desc->flags = htole32(cflags); 2857 desc->addr = htole64(txsegs[0].ds_addr); 2858 sc->alc_cdata.alc_tx_cnt++; 2859 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2860 if (m->m_len - hdrlen > 0) { 2861 /* Handle remaining payload of the first fragment. */ 2862 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2863 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2864 vtag)); 2865 desc->flags = htole32(cflags); 2866 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2867 sc->alc_cdata.alc_tx_cnt++; 2868 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2869 } 2870 /* Handle remaining fragments. */ 2871 idx = 1; 2872 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2873 /* Configure Tx checksum offload. */ 2874#ifdef ALC_USE_CUSTOM_CSUM 2875 cflags |= TD_CUSTOM_CSUM; 2876 /* Set checksum start offset. */ 2877 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2878 TD_PLOAD_OFFSET_MASK; 2879 /* Set checksum insertion position of TCP/UDP. */ 2880 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2881 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2882#else 2883 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2884 cflags |= TD_IPCSUM; 2885 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2886 cflags |= TD_TCPCSUM; 2887 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2888 cflags |= TD_UDPCSUM; 2889 /* Set TCP/UDP header offset. */ 2890 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2891 TD_L4HDR_OFFSET_MASK; 2892#endif 2893 } 2894 for (; idx < nsegs; idx++) { 2895 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2896 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2897 desc->flags = htole32(cflags); 2898 desc->addr = htole64(txsegs[idx].ds_addr); 2899 sc->alc_cdata.alc_tx_cnt++; 2900 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2901 } 2902 /* Update producer index. */ 2903 sc->alc_cdata.alc_tx_prod = prod; 2904 2905 /* Finally set EOP on the last descriptor. */ 2906 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2907 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2908 desc->flags |= htole32(TD_EOP); 2909 2910 /* Swap dmamap of the first and the last. */ 2911 txd = &sc->alc_cdata.alc_txdesc[prod]; 2912 map = txd_last->tx_dmamap; 2913 txd_last->tx_dmamap = txd->tx_dmamap; 2914 txd->tx_dmamap = map; 2915 txd->tx_m = m; 2916 2917 return (0); 2918} 2919 2920static void 2921alc_start(struct ifnet *ifp) 2922{ 2923 struct alc_softc *sc; 2924 2925 sc = ifp->if_softc; 2926 ALC_LOCK(sc); 2927 alc_start_locked(ifp); 2928 ALC_UNLOCK(sc); 2929} 2930 2931static void 2932alc_start_locked(struct ifnet *ifp) 2933{ 2934 struct alc_softc *sc; 2935 struct mbuf *m_head; 2936 int enq; 2937 2938 sc = ifp->if_softc; 2939 2940 ALC_LOCK_ASSERT(sc); 2941 2942 /* Reclaim transmitted frames. */ 2943 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2944 alc_txeof(sc); 2945 2946 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2947 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2948 return; 2949 2950 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2951 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2952 if (m_head == NULL) 2953 break; 2954 /* 2955 * Pack the data into the transmit ring. If we 2956 * don't have room, set the OACTIVE flag and wait 2957 * for the NIC to drain the ring. 2958 */ 2959 if (alc_encap(sc, &m_head)) { 2960 if (m_head == NULL) 2961 break; 2962 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2963 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2964 break; 2965 } 2966 2967 enq++; 2968 /* 2969 * If there's a BPF listener, bounce a copy of this frame 2970 * to him. 2971 */ 2972 ETHER_BPF_MTAP(ifp, m_head); 2973 } 2974 2975 if (enq > 0) { 2976 /* Sync descriptors. */ 2977 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2978 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2979 /* Kick. Assume we're using normal Tx priority queue. */ 2980 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2981 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 2982 (uint16_t)sc->alc_cdata.alc_tx_prod); 2983 else 2984 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2985 (sc->alc_cdata.alc_tx_prod << 2986 MBOX_TD_PROD_LO_IDX_SHIFT) & 2987 MBOX_TD_PROD_LO_IDX_MASK); 2988 /* Set a timeout in case the chip goes out to lunch. */ 2989 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2990 } 2991} 2992 2993static void 2994alc_watchdog(struct alc_softc *sc) 2995{ 2996 struct ifnet *ifp; 2997 2998 ALC_LOCK_ASSERT(sc); 2999 3000 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3001 return; 3002 3003 ifp = sc->alc_ifp; 3004 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3005 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3006 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3007 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3008 alc_init_locked(sc); 3009 return; 3010 } 3011 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3012 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3013 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3014 alc_init_locked(sc); 3015 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3016 alc_start_locked(ifp); 3017} 3018 3019static int 3020alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3021{ 3022 struct alc_softc *sc; 3023 struct ifreq *ifr; 3024 struct mii_data *mii; 3025 int error, mask; 3026 3027 sc = ifp->if_softc; 3028 ifr = (struct ifreq *)data; 3029 error = 0; 3030 switch (cmd) { 3031 case SIOCSIFMTU: 3032 if (ifr->ifr_mtu < ETHERMIN || 3033 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3034 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3035 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3036 ifr->ifr_mtu > ETHERMTU)) 3037 error = EINVAL; 3038 else if (ifp->if_mtu != ifr->ifr_mtu) { 3039 ALC_LOCK(sc); 3040 ifp->if_mtu = ifr->ifr_mtu; 3041 /* AR81[3567]x has 13 bits MSS field. */ 3042 if (ifp->if_mtu > ALC_TSO_MTU && 3043 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3044 ifp->if_capenable &= ~IFCAP_TSO4; 3045 ifp->if_hwassist &= ~CSUM_TSO; 3046 VLAN_CAPABILITIES(ifp); 3047 } 3048 ALC_UNLOCK(sc); 3049 } 3050 break; 3051 case SIOCSIFFLAGS: 3052 ALC_LOCK(sc); 3053 if ((ifp->if_flags & IFF_UP) != 0) { 3054 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3055 ((ifp->if_flags ^ sc->alc_if_flags) & 3056 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3057 alc_rxfilter(sc); 3058 else 3059 alc_init_locked(sc); 3060 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3061 alc_stop(sc); 3062 sc->alc_if_flags = ifp->if_flags; 3063 ALC_UNLOCK(sc); 3064 break; 3065 case SIOCADDMULTI: 3066 case SIOCDELMULTI: 3067 ALC_LOCK(sc); 3068 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3069 alc_rxfilter(sc); 3070 ALC_UNLOCK(sc); 3071 break; 3072 case SIOCSIFMEDIA: 3073 case SIOCGIFMEDIA: 3074 mii = device_get_softc(sc->alc_miibus); 3075 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3076 break; 3077 case SIOCSIFCAP: 3078 ALC_LOCK(sc); 3079 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3080 if ((mask & IFCAP_TXCSUM) != 0 && 3081 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3082 ifp->if_capenable ^= IFCAP_TXCSUM; 3083 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3084 ifp->if_hwassist |= ALC_CSUM_FEATURES; 3085 else 3086 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 3087 } 3088 if ((mask & IFCAP_TSO4) != 0 && 3089 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3090 ifp->if_capenable ^= IFCAP_TSO4; 3091 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 3092 /* AR81[3567]x has 13 bits MSS field. */ 3093 if (ifp->if_mtu > ALC_TSO_MTU) { 3094 ifp->if_capenable &= ~IFCAP_TSO4; 3095 ifp->if_hwassist &= ~CSUM_TSO; 3096 } else 3097 ifp->if_hwassist |= CSUM_TSO; 3098 } else 3099 ifp->if_hwassist &= ~CSUM_TSO; 3100 } 3101 if ((mask & IFCAP_WOL_MCAST) != 0 && 3102 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 3103 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3104 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3105 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3106 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3107 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3108 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3109 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3110 alc_rxvlan(sc); 3111 } 3112 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3113 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3114 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3115 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3116 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3117 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3118 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3119 ifp->if_capenable &= 3120 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3121 ALC_UNLOCK(sc); 3122 VLAN_CAPABILITIES(ifp); 3123 break; 3124 default: 3125 error = ether_ioctl(ifp, cmd, data); 3126 break; 3127 } 3128 3129 return (error); 3130} 3131 3132static void 3133alc_mac_config(struct alc_softc *sc) 3134{ 3135 struct mii_data *mii; 3136 uint32_t reg; 3137 3138 ALC_LOCK_ASSERT(sc); 3139 3140 mii = device_get_softc(sc->alc_miibus); 3141 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3142 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3143 MAC_CFG_SPEED_MASK); 3144 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3145 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3146 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3147 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3148 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3149 /* Reprogram MAC with resolved speed/duplex. */ 3150 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3151 case IFM_10_T: 3152 case IFM_100_TX: 3153 reg |= MAC_CFG_SPEED_10_100; 3154 break; 3155 case IFM_1000_T: 3156 reg |= MAC_CFG_SPEED_1000; 3157 break; 3158 } 3159 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3160 reg |= MAC_CFG_FULL_DUPLEX; 3161 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3162 reg |= MAC_CFG_TX_FC; 3163 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3164 reg |= MAC_CFG_RX_FC; 3165 } 3166 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3167} 3168 3169static void 3170alc_stats_clear(struct alc_softc *sc) 3171{ 3172 struct smb sb, *smb; 3173 uint32_t *reg; 3174 int i; 3175 3176 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3177 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3178 sc->alc_cdata.alc_smb_map, 3179 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3180 smb = sc->alc_rdata.alc_smb; 3181 /* Update done, clear. */ 3182 smb->updated = 0; 3183 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3184 sc->alc_cdata.alc_smb_map, 3185 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3186 } else { 3187 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3188 reg++) { 3189 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3190 i += sizeof(uint32_t); 3191 } 3192 /* Read Tx statistics. */ 3193 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3194 reg++) { 3195 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3196 i += sizeof(uint32_t); 3197 } 3198 } 3199} 3200 3201static void 3202alc_stats_update(struct alc_softc *sc) 3203{ 3204 struct alc_hw_stats *stat; 3205 struct smb sb, *smb; 3206 struct ifnet *ifp; 3207 uint32_t *reg; 3208 int i; 3209 3210 ALC_LOCK_ASSERT(sc); 3211 3212 ifp = sc->alc_ifp; 3213 stat = &sc->alc_stats; 3214 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3215 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3216 sc->alc_cdata.alc_smb_map, 3217 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3218 smb = sc->alc_rdata.alc_smb; 3219 if (smb->updated == 0) 3220 return; 3221 } else { 3222 smb = &sb; 3223 /* Read Rx statistics. */ 3224 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3225 reg++) { 3226 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3227 i += sizeof(uint32_t); 3228 } 3229 /* Read Tx statistics. */ 3230 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3231 reg++) { 3232 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3233 i += sizeof(uint32_t); 3234 } 3235 } 3236 3237 /* Rx stats. */ 3238 stat->rx_frames += smb->rx_frames; 3239 stat->rx_bcast_frames += smb->rx_bcast_frames; 3240 stat->rx_mcast_frames += smb->rx_mcast_frames; 3241 stat->rx_pause_frames += smb->rx_pause_frames; 3242 stat->rx_control_frames += smb->rx_control_frames; 3243 stat->rx_crcerrs += smb->rx_crcerrs; 3244 stat->rx_lenerrs += smb->rx_lenerrs; 3245 stat->rx_bytes += smb->rx_bytes; 3246 stat->rx_runts += smb->rx_runts; 3247 stat->rx_fragments += smb->rx_fragments; 3248 stat->rx_pkts_64 += smb->rx_pkts_64; 3249 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3250 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3251 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3252 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3253 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3254 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3255 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3256 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3257 stat->rx_rrs_errs += smb->rx_rrs_errs; 3258 stat->rx_alignerrs += smb->rx_alignerrs; 3259 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3260 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3261 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3262 3263 /* Tx stats. */ 3264 stat->tx_frames += smb->tx_frames; 3265 stat->tx_bcast_frames += smb->tx_bcast_frames; 3266 stat->tx_mcast_frames += smb->tx_mcast_frames; 3267 stat->tx_pause_frames += smb->tx_pause_frames; 3268 stat->tx_excess_defer += smb->tx_excess_defer; 3269 stat->tx_control_frames += smb->tx_control_frames; 3270 stat->tx_deferred += smb->tx_deferred; 3271 stat->tx_bytes += smb->tx_bytes; 3272 stat->tx_pkts_64 += smb->tx_pkts_64; 3273 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3274 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3275 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3276 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3277 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3278 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3279 stat->tx_single_colls += smb->tx_single_colls; 3280 stat->tx_multi_colls += smb->tx_multi_colls; 3281 stat->tx_late_colls += smb->tx_late_colls; 3282 stat->tx_excess_colls += smb->tx_excess_colls; 3283 stat->tx_underrun += smb->tx_underrun; 3284 stat->tx_desc_underrun += smb->tx_desc_underrun; 3285 stat->tx_lenerrs += smb->tx_lenerrs; 3286 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3287 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3288 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3289 3290 /* Update counters in ifnet. */ 3291 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3292 3293 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3294 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3295 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3296 3297 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3298 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3299 3300 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3301 3302 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3303 smb->rx_crcerrs + smb->rx_lenerrs + 3304 smb->rx_runts + smb->rx_pkts_truncated + 3305 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3306 smb->rx_alignerrs); 3307 3308 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3309 /* Update done, clear. */ 3310 smb->updated = 0; 3311 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3312 sc->alc_cdata.alc_smb_map, 3313 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3314 } 3315} 3316 3317static int 3318alc_intr(void *arg) 3319{ 3320 struct alc_softc *sc; 3321 uint32_t status; 3322 3323 sc = (struct alc_softc *)arg; 3324 3325 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3326 if ((status & ALC_INTRS) == 0) 3327 return (FILTER_STRAY); 3328 /* Disable interrupts. */ 3329 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3330 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3331 3332 return (FILTER_HANDLED); 3333} 3334 3335static void 3336alc_int_task(void *arg, int pending) 3337{ 3338 struct alc_softc *sc; 3339 struct ifnet *ifp; 3340 uint32_t status; 3341 int more; 3342 3343 sc = (struct alc_softc *)arg; 3344 ifp = sc->alc_ifp; 3345 3346 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3347 ALC_LOCK(sc); 3348 if (sc->alc_morework != 0) { 3349 sc->alc_morework = 0; 3350 status |= INTR_RX_PKT; 3351 } 3352 if ((status & ALC_INTRS) == 0) 3353 goto done; 3354 3355 /* Acknowledge interrupts but still disable interrupts. */ 3356 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3357 3358 more = 0; 3359 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3360 if ((status & INTR_RX_PKT) != 0) { 3361 more = alc_rxintr(sc, sc->alc_process_limit); 3362 if (more == EAGAIN) 3363 sc->alc_morework = 1; 3364 else if (more == EIO) { 3365 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3366 alc_init_locked(sc); 3367 ALC_UNLOCK(sc); 3368 return; 3369 } 3370 } 3371 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3372 INTR_TXQ_TO_RST)) != 0) { 3373 if ((status & INTR_DMA_RD_TO_RST) != 0) 3374 device_printf(sc->alc_dev, 3375 "DMA read error! -- resetting\n"); 3376 if ((status & INTR_DMA_WR_TO_RST) != 0) 3377 device_printf(sc->alc_dev, 3378 "DMA write error! -- resetting\n"); 3379 if ((status & INTR_TXQ_TO_RST) != 0) 3380 device_printf(sc->alc_dev, 3381 "TxQ reset! -- resetting\n"); 3382 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3383 alc_init_locked(sc); 3384 ALC_UNLOCK(sc); 3385 return; 3386 } 3387 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3388 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3389 alc_start_locked(ifp); 3390 } 3391 3392 if (more == EAGAIN || 3393 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3394 ALC_UNLOCK(sc); 3395 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3396 return; 3397 } 3398 3399done: 3400 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3401 /* Re-enable interrupts if we're running. */ 3402 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3403 } 3404 ALC_UNLOCK(sc); 3405} 3406 3407static void 3408alc_txeof(struct alc_softc *sc) 3409{ 3410 struct ifnet *ifp; 3411 struct alc_txdesc *txd; 3412 uint32_t cons, prod; 3413 int prog; 3414 3415 ALC_LOCK_ASSERT(sc); 3416 3417 ifp = sc->alc_ifp; 3418 3419 if (sc->alc_cdata.alc_tx_cnt == 0) 3420 return; 3421 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3422 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3423 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3424 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3425 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3426 prod = sc->alc_rdata.alc_cmb->cons; 3427 } else { 3428 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3429 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3430 else { 3431 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3432 /* Assume we're using normal Tx priority queue. */ 3433 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3434 MBOX_TD_CONS_LO_IDX_SHIFT; 3435 } 3436 } 3437 cons = sc->alc_cdata.alc_tx_cons; 3438 /* 3439 * Go through our Tx list and free mbufs for those 3440 * frames which have been transmitted. 3441 */ 3442 for (prog = 0; cons != prod; prog++, 3443 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3444 if (sc->alc_cdata.alc_tx_cnt <= 0) 3445 break; 3446 prog++; 3447 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3448 sc->alc_cdata.alc_tx_cnt--; 3449 txd = &sc->alc_cdata.alc_txdesc[cons]; 3450 if (txd->tx_m != NULL) { 3451 /* Reclaim transmitted mbufs. */ 3452 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3453 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3454 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3455 txd->tx_dmamap); 3456 m_freem(txd->tx_m); 3457 txd->tx_m = NULL; 3458 } 3459 } 3460 3461 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3462 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3463 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3464 sc->alc_cdata.alc_tx_cons = cons; 3465 /* 3466 * Unarm watchdog timer only when there is no pending 3467 * frames in Tx queue. 3468 */ 3469 if (sc->alc_cdata.alc_tx_cnt == 0) 3470 sc->alc_watchdog_timer = 0; 3471} 3472 3473static int 3474alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3475{ 3476 struct mbuf *m; 3477 bus_dma_segment_t segs[1]; 3478 bus_dmamap_t map; 3479 int nsegs; 3480 3481 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3482 if (m == NULL) 3483 return (ENOBUFS); 3484 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3485#ifndef __NO_STRICT_ALIGNMENT 3486 m_adj(m, sizeof(uint64_t)); 3487#endif 3488 3489 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3490 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3491 m_freem(m); 3492 return (ENOBUFS); 3493 } 3494 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3495 3496 if (rxd->rx_m != NULL) { 3497 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3498 BUS_DMASYNC_POSTREAD); 3499 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3500 } 3501 map = rxd->rx_dmamap; 3502 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3503 sc->alc_cdata.alc_rx_sparemap = map; 3504 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3505 BUS_DMASYNC_PREREAD); 3506 rxd->rx_m = m; 3507 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3508 return (0); 3509} 3510 3511static int 3512alc_rxintr(struct alc_softc *sc, int count) 3513{ 3514 struct ifnet *ifp; 3515 struct rx_rdesc *rrd; 3516 uint32_t nsegs, status; 3517 int rr_cons, prog; 3518 3519 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3520 sc->alc_cdata.alc_rr_ring_map, 3521 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3522 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3523 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3524 rr_cons = sc->alc_cdata.alc_rr_cons; 3525 ifp = sc->alc_ifp; 3526 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 3527 if (count-- <= 0) 3528 break; 3529 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3530 status = le32toh(rrd->status); 3531 if ((status & RRD_VALID) == 0) 3532 break; 3533 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3534 if (nsegs == 0) { 3535 /* This should not happen! */ 3536 device_printf(sc->alc_dev, 3537 "unexpected segment count -- resetting\n"); 3538 return (EIO); 3539 } 3540 alc_rxeof(sc, rrd); 3541 /* Clear Rx return status. */ 3542 rrd->status = 0; 3543 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3544 sc->alc_cdata.alc_rx_cons += nsegs; 3545 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3546 prog += nsegs; 3547 } 3548 3549 if (prog > 0) { 3550 /* Update the consumer index. */ 3551 sc->alc_cdata.alc_rr_cons = rr_cons; 3552 /* Sync Rx return descriptors. */ 3553 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3554 sc->alc_cdata.alc_rr_ring_map, 3555 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3556 /* 3557 * Sync updated Rx descriptors such that controller see 3558 * modified buffer addresses. 3559 */ 3560 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3561 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3562 /* 3563 * Let controller know availability of new Rx buffers. 3564 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3565 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3566 * only when Rx buffer pre-fetching is required. In 3567 * addition we already set ALC_RX_RD_FREE_THRESH to 3568 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3569 * it still seems that pre-fetching needs more 3570 * experimentation. 3571 */ 3572 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3573 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3574 (uint16_t)sc->alc_cdata.alc_rx_cons); 3575 else 3576 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3577 sc->alc_cdata.alc_rx_cons); 3578 } 3579 3580 return (count > 0 ? 0 : EAGAIN); 3581} 3582 3583#ifndef __NO_STRICT_ALIGNMENT 3584static struct mbuf * 3585alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 3586{ 3587 struct mbuf *n; 3588 int i; 3589 uint16_t *src, *dst; 3590 3591 src = mtod(m, uint16_t *); 3592 dst = src - 3; 3593 3594 if (m->m_next == NULL) { 3595 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3596 *dst++ = *src++; 3597 m->m_data -= 6; 3598 return (m); 3599 } 3600 /* 3601 * Append a new mbuf to received mbuf chain and copy ethernet 3602 * header from the mbuf chain. This can save lots of CPU 3603 * cycles for jumbo frame. 3604 */ 3605 MGETHDR(n, M_NOWAIT, MT_DATA); 3606 if (n == NULL) { 3607 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3608 m_freem(m); 3609 return (NULL); 3610 } 3611 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3612 m->m_data += ETHER_HDR_LEN; 3613 m->m_len -= ETHER_HDR_LEN; 3614 n->m_len = ETHER_HDR_LEN; 3615 M_MOVE_PKTHDR(n, m); 3616 n->m_next = m; 3617 return (n); 3618} 3619#endif 3620 3621/* Receive a frame. */ 3622static void 3623alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3624{ 3625 struct alc_rxdesc *rxd; 3626 struct ifnet *ifp; 3627 struct mbuf *mp, *m; 3628 uint32_t rdinfo, status, vtag; 3629 int count, nsegs, rx_cons; 3630 3631 ifp = sc->alc_ifp; 3632 status = le32toh(rrd->status); 3633 rdinfo = le32toh(rrd->rdinfo); 3634 rx_cons = RRD_RD_IDX(rdinfo); 3635 nsegs = RRD_RD_CNT(rdinfo); 3636 3637 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3638 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3639 /* 3640 * We want to pass the following frames to upper 3641 * layer regardless of error status of Rx return 3642 * ring. 3643 * 3644 * o IP/TCP/UDP checksum is bad. 3645 * o frame length and protocol specific length 3646 * does not match. 3647 * 3648 * Force network stack compute checksum for 3649 * errored frames. 3650 */ 3651 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3652 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3653 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3654 return; 3655 } 3656 3657 for (count = 0; count < nsegs; count++, 3658 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3659 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3660 mp = rxd->rx_m; 3661 /* Add a new receive buffer to the ring. */ 3662 if (alc_newbuf(sc, rxd) != 0) { 3663 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3664 /* Reuse Rx buffers. */ 3665 if (sc->alc_cdata.alc_rxhead != NULL) 3666 m_freem(sc->alc_cdata.alc_rxhead); 3667 break; 3668 } 3669 3670 /* 3671 * Assume we've received a full sized frame. 3672 * Actual size is fixed when we encounter the end of 3673 * multi-segmented frame. 3674 */ 3675 mp->m_len = sc->alc_buf_size; 3676 3677 /* Chain received mbufs. */ 3678 if (sc->alc_cdata.alc_rxhead == NULL) { 3679 sc->alc_cdata.alc_rxhead = mp; 3680 sc->alc_cdata.alc_rxtail = mp; 3681 } else { 3682 mp->m_flags &= ~M_PKTHDR; 3683 sc->alc_cdata.alc_rxprev_tail = 3684 sc->alc_cdata.alc_rxtail; 3685 sc->alc_cdata.alc_rxtail->m_next = mp; 3686 sc->alc_cdata.alc_rxtail = mp; 3687 } 3688 3689 if (count == nsegs - 1) { 3690 /* Last desc. for this frame. */ 3691 m = sc->alc_cdata.alc_rxhead; 3692 m->m_flags |= M_PKTHDR; 3693 /* 3694 * It seems that L1C/L2C controller has no way 3695 * to tell hardware to strip CRC bytes. 3696 */ 3697 m->m_pkthdr.len = 3698 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3699 if (nsegs > 1) { 3700 /* Set last mbuf size. */ 3701 mp->m_len = sc->alc_cdata.alc_rxlen - 3702 (nsegs - 1) * sc->alc_buf_size; 3703 /* Remove the CRC bytes in chained mbufs. */ 3704 if (mp->m_len <= ETHER_CRC_LEN) { 3705 sc->alc_cdata.alc_rxtail = 3706 sc->alc_cdata.alc_rxprev_tail; 3707 sc->alc_cdata.alc_rxtail->m_len -= 3708 (ETHER_CRC_LEN - mp->m_len); 3709 sc->alc_cdata.alc_rxtail->m_next = NULL; 3710 m_freem(mp); 3711 } else { 3712 mp->m_len -= ETHER_CRC_LEN; 3713 } 3714 } else 3715 m->m_len = m->m_pkthdr.len; 3716 m->m_pkthdr.rcvif = ifp; 3717 /* 3718 * Due to hardware bugs, Rx checksum offloading 3719 * was intentionally disabled. 3720 */ 3721 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3722 (status & RRD_VLAN_TAG) != 0) { 3723 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3724 m->m_pkthdr.ether_vtag = ntohs(vtag); 3725 m->m_flags |= M_VLANTAG; 3726 } 3727#ifndef __NO_STRICT_ALIGNMENT 3728 m = alc_fixup_rx(ifp, m); 3729 if (m != NULL) 3730#endif 3731 { 3732 /* Pass it on. */ 3733 ALC_UNLOCK(sc); 3734 (*ifp->if_input)(ifp, m); 3735 ALC_LOCK(sc); 3736 } 3737 } 3738 } 3739 /* Reset mbuf chains. */ 3740 ALC_RXCHAIN_RESET(sc); 3741} 3742 3743static void 3744alc_tick(void *arg) 3745{ 3746 struct alc_softc *sc; 3747 struct mii_data *mii; 3748 3749 sc = (struct alc_softc *)arg; 3750 3751 ALC_LOCK_ASSERT(sc); 3752 3753 mii = device_get_softc(sc->alc_miibus); 3754 mii_tick(mii); 3755 alc_stats_update(sc); 3756 /* 3757 * alc(4) does not rely on Tx completion interrupts to reclaim 3758 * transferred buffers. Instead Tx completion interrupts are 3759 * used to hint for scheduling Tx task. So it's necessary to 3760 * release transmitted buffers by kicking Tx completion 3761 * handler. This limits the maximum reclamation delay to a hz. 3762 */ 3763 alc_txeof(sc); 3764 alc_watchdog(sc); 3765 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3766} 3767 3768static void 3769alc_osc_reset(struct alc_softc *sc) 3770{ 3771 uint32_t reg; 3772 3773 reg = CSR_READ_4(sc, ALC_MISC3); 3774 reg &= ~MISC3_25M_BY_SW; 3775 reg |= MISC3_25M_NOTO_INTNL; 3776 CSR_WRITE_4(sc, ALC_MISC3, reg); 3777 3778 reg = CSR_READ_4(sc, ALC_MISC); 3779 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3780 /* 3781 * Restore over-current protection default value. 3782 * This value could be reset by MAC reset. 3783 */ 3784 reg &= ~MISC_PSW_OCP_MASK; 3785 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3786 reg &= ~MISC_INTNLOSC_OPEN; 3787 CSR_WRITE_4(sc, ALC_MISC, reg); 3788 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3789 reg = CSR_READ_4(sc, ALC_MISC2); 3790 reg &= ~MISC2_CALB_START; 3791 CSR_WRITE_4(sc, ALC_MISC2, reg); 3792 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3793 3794 } else { 3795 reg &= ~MISC_INTNLOSC_OPEN; 3796 /* Disable isolate for revision A devices. */ 3797 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3798 reg &= ~MISC_ISO_ENB; 3799 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3800 CSR_WRITE_4(sc, ALC_MISC, reg); 3801 } 3802 3803 DELAY(20); 3804} 3805 3806static void 3807alc_reset(struct alc_softc *sc) 3808{ 3809 uint32_t pmcfg, reg; 3810 int i; 3811 3812 pmcfg = 0; 3813 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3814 /* Reset workaround. */ 3815 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3816 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3817 (sc->alc_rev & 0x01) != 0) { 3818 /* Disable L0s/L1s before reset. */ 3819 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3820 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3821 != 0) { 3822 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3823 PM_CFG_ASPM_L1_ENB); 3824 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3825 } 3826 } 3827 } 3828 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3829 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3830 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3831 3832 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3833 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3834 DELAY(10); 3835 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3836 break; 3837 } 3838 if (i == 0) 3839 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3840 } 3841 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3842 DELAY(10); 3843 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3844 break; 3845 } 3846 if (i == 0) 3847 device_printf(sc->alc_dev, "master reset timeout!\n"); 3848 3849 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3850 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3851 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3852 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3853 break; 3854 DELAY(10); 3855 } 3856 if (i == 0) 3857 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3858 3859 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3860 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3861 (sc->alc_rev & 0x01) != 0) { 3862 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3863 reg |= MASTER_CLK_SEL_DIS; 3864 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3865 /* Restore L0s/L1s config. */ 3866 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3867 != 0) 3868 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3869 } 3870 3871 alc_osc_reset(sc); 3872 reg = CSR_READ_4(sc, ALC_MISC3); 3873 reg &= ~MISC3_25M_BY_SW; 3874 reg |= MISC3_25M_NOTO_INTNL; 3875 CSR_WRITE_4(sc, ALC_MISC3, reg); 3876 reg = CSR_READ_4(sc, ALC_MISC); 3877 reg &= ~MISC_INTNLOSC_OPEN; 3878 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3879 reg &= ~MISC_ISO_ENB; 3880 CSR_WRITE_4(sc, ALC_MISC, reg); 3881 DELAY(20); 3882 } 3883 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3884 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3885 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3886 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3887 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3888 SERDES_PHY_CLK_SLOWDOWN); 3889} 3890 3891static void 3892alc_init(void *xsc) 3893{ 3894 struct alc_softc *sc; 3895 3896 sc = (struct alc_softc *)xsc; 3897 ALC_LOCK(sc); 3898 alc_init_locked(sc); 3899 ALC_UNLOCK(sc); 3900} 3901 3902static void 3903alc_init_locked(struct alc_softc *sc) 3904{ 3905 struct ifnet *ifp; 3906 struct mii_data *mii; 3907 uint8_t eaddr[ETHER_ADDR_LEN]; 3908 bus_addr_t paddr; 3909 uint32_t reg, rxf_hi, rxf_lo; 3910 3911 ALC_LOCK_ASSERT(sc); 3912 3913 ifp = sc->alc_ifp; 3914 mii = device_get_softc(sc->alc_miibus); 3915 3916 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3917 return; 3918 /* 3919 * Cancel any pending I/O. 3920 */ 3921 alc_stop(sc); 3922 /* 3923 * Reset the chip to a known state. 3924 */ 3925 alc_reset(sc); 3926 3927 /* Initialize Rx descriptors. */ 3928 if (alc_init_rx_ring(sc) != 0) { 3929 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3930 alc_stop(sc); 3931 return; 3932 } 3933 alc_init_rr_ring(sc); 3934 alc_init_tx_ring(sc); 3935 alc_init_cmb(sc); 3936 alc_init_smb(sc); 3937 3938 /* Enable all clocks. */ 3939 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3940 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3941 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3942 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3943 CLK_GATING_RXMAC_ENB); 3944 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3945 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3946 IDLE_DECISN_TIMER_DEFAULT_1MS); 3947 } else 3948 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3949 3950 /* Reprogram the station address. */ 3951 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3952 CSR_WRITE_4(sc, ALC_PAR0, 3953 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3954 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3955 /* 3956 * Clear WOL status and disable all WOL feature as WOL 3957 * would interfere Rx operation under normal environments. 3958 */ 3959 CSR_READ_4(sc, ALC_WOL_CFG); 3960 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3961 /* Set Tx descriptor base addresses. */ 3962 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3963 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3964 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3965 /* We don't use high priority ring. */ 3966 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3967 /* Set Tx descriptor counter. */ 3968 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3969 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3970 /* Set Rx descriptor base addresses. */ 3971 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3972 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3973 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3974 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3975 /* We use one Rx ring. */ 3976 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3977 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3978 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3979 } 3980 /* Set Rx descriptor counter. */ 3981 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3982 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3983 3984 /* 3985 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3986 * if it do not fit the buffer size. Rx return descriptor holds 3987 * a counter that indicates how many fragments were made by the 3988 * hardware. The buffer size should be multiple of 8 bytes. 3989 * Since hardware has limit on the size of buffer size, always 3990 * use the maximum value. 3991 * For strict-alignment architectures make sure to reduce buffer 3992 * size by 8 bytes to make room for alignment fixup. 3993 */ 3994#ifndef __NO_STRICT_ALIGNMENT 3995 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3996#else 3997 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3998#endif 3999 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4000 4001 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4002 /* Set Rx return descriptor base addresses. */ 4003 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4004 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4005 /* We use one Rx return ring. */ 4006 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4007 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4008 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4009 } 4010 /* Set Rx return descriptor counter. */ 4011 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4012 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4013 paddr = sc->alc_rdata.alc_cmb_paddr; 4014 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4015 paddr = sc->alc_rdata.alc_smb_paddr; 4016 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4017 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4018 4019 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4020 /* Reconfigure SRAM - Vendor magic. */ 4021 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4022 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4023 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4024 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4025 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4026 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4027 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4028 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4029 } 4030 4031 /* Tell hardware that we're ready to load DMA blocks. */ 4032 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4033 4034 /* Configure interrupt moderation timer. */ 4035 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4036 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4037 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4038 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4039 /* 4040 * We don't want to automatic interrupt clear as task queue 4041 * for the interrupt should know interrupt status. 4042 */ 4043 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4044 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4045 reg |= MASTER_SA_TIMER_ENB; 4046 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4047 reg |= MASTER_IM_RX_TIMER_ENB; 4048 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4049 ALC_USECS(sc->alc_int_tx_mod) != 0) 4050 reg |= MASTER_IM_TX_TIMER_ENB; 4051 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4052 /* 4053 * Disable interrupt re-trigger timer. We don't want automatic 4054 * re-triggering of un-ACKed interrupts. 4055 */ 4056 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4057 /* Configure CMB. */ 4058 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4059 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4060 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4061 ALC_USECS(sc->alc_int_tx_mod)); 4062 } else { 4063 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4064 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4065 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4066 } else 4067 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4068 } 4069 /* 4070 * Hardware can be configured to issue SMB interrupt based 4071 * on programmed interval. Since there is a callout that is 4072 * invoked for every hz in driver we use that instead of 4073 * relying on periodic SMB interrupt. 4074 */ 4075 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4076 /* Clear MAC statistics. */ 4077 alc_stats_clear(sc); 4078 4079 /* 4080 * Always use maximum frame size that controller can support. 4081 * Otherwise received frames that has larger frame length 4082 * than alc(4) MTU would be silently dropped in hardware. This 4083 * would make path-MTU discovery hard as sender wouldn't get 4084 * any responses from receiver. alc(4) supports 4085 * multi-fragmented frames on Rx path so it has no issue on 4086 * assembling fragmented frames. Using maximum frame size also 4087 * removes the need to reinitialize hardware when interface 4088 * MTU configuration was changed. 4089 * 4090 * Be conservative in what you do, be liberal in what you 4091 * accept from others - RFC 793. 4092 */ 4093 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4094 4095 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4096 /* Disable header split(?) */ 4097 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4098 4099 /* Configure IPG/IFG parameters. */ 4100 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4101 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4102 IPG_IFG_IPGT_MASK) | 4103 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4104 IPG_IFG_MIFG_MASK) | 4105 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4106 IPG_IFG_IPG1_MASK) | 4107 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4108 IPG_IFG_IPG2_MASK)); 4109 /* Set parameters for half-duplex media. */ 4110 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4111 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4112 HDPX_CFG_LCOL_MASK) | 4113 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4114 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4115 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4116 HDPX_CFG_ABEBT_MASK) | 4117 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4118 HDPX_CFG_JAMIPG_MASK)); 4119 } 4120 4121 /* 4122 * Set TSO/checksum offload threshold. For frames that is 4123 * larger than this threshold, hardware wouldn't do 4124 * TSO/checksum offloading. 4125 */ 4126 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4127 TSO_OFFLOAD_THRESH_MASK; 4128 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4129 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4130 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4131 /* Configure TxQ. */ 4132 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4133 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4134 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4135 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4136 reg >>= 1; 4137 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4138 TXQ_CFG_TD_BURST_MASK; 4139 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4140 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4141 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4142 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4143 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4144 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4145 HQTD_CFG_BURST_ENB); 4146 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4147 reg = WRR_PRI_RESTRICT_NONE; 4148 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4149 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4150 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4151 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4152 CSR_WRITE_4(sc, ALC_WRR, reg); 4153 } else { 4154 /* Configure Rx free descriptor pre-fetching. */ 4155 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4156 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4157 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4158 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4159 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4160 } 4161 4162 /* 4163 * Configure flow control parameters. 4164 * XON : 80% of Rx FIFO 4165 * XOFF : 30% of Rx FIFO 4166 */ 4167 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4168 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4169 reg &= SRAM_RX_FIFO_LEN_MASK; 4170 reg *= 8; 4171 if (reg > 8 * 1024) 4172 reg -= RX_FIFO_PAUSE_816X_RSVD; 4173 else 4174 reg -= RX_BUF_SIZE_MAX; 4175 reg /= 8; 4176 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4177 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4178 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4179 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4180 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4181 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4182 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4183 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4184 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4185 rxf_hi = (reg * 8) / 10; 4186 rxf_lo = (reg * 3) / 10; 4187 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4188 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4189 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4190 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4191 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4192 } 4193 4194 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4195 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4196 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4197 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4198 } 4199 4200 /* Configure RxQ. */ 4201 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4202 RXQ_CFG_RD_BURST_MASK; 4203 reg |= RXQ_CFG_RSS_MODE_DIS; 4204 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4205 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4206 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4207 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4208 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4209 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4210 } else { 4211 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4212 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4213 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4214 } 4215 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4216 4217 /* Configure DMA parameters. */ 4218 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4219 reg |= sc->alc_rcb; 4220 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4221 reg |= DMA_CFG_CMB_ENB; 4222 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4223 reg |= DMA_CFG_SMB_ENB; 4224 else 4225 reg |= DMA_CFG_SMB_DIS; 4226 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4227 DMA_CFG_RD_BURST_SHIFT; 4228 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4229 DMA_CFG_WR_BURST_SHIFT; 4230 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4231 DMA_CFG_RD_DELAY_CNT_MASK; 4232 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4233 DMA_CFG_WR_DELAY_CNT_MASK; 4234 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4235 switch (AR816X_REV(sc->alc_rev)) { 4236 case AR816X_REV_A0: 4237 case AR816X_REV_A1: 4238 reg |= DMA_CFG_RD_CHNL_SEL_2; 4239 break; 4240 case AR816X_REV_B0: 4241 /* FALLTHROUGH */ 4242 default: 4243 reg |= DMA_CFG_RD_CHNL_SEL_4; 4244 break; 4245 } 4246 } 4247 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4248 4249 /* 4250 * Configure Tx/Rx MACs. 4251 * - Auto-padding for short frames. 4252 * - Enable CRC generation. 4253 * Actual reconfiguration of MAC for resolved speed/duplex 4254 * is followed after detection of link establishment. 4255 * AR813x/AR815x always does checksum computation regardless 4256 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4257 * have bug in protocol field in Rx return structure so 4258 * these controllers can't handle fragmented frames. Disable 4259 * Rx checksum offloading until there is a newer controller 4260 * that has sane implementation. 4261 */ 4262 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4263 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4264 MAC_CFG_PREAMBLE_MASK); 4265 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4266 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4267 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4268 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4269 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4270 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4271 reg |= MAC_CFG_SPEED_10_100; 4272 else 4273 reg |= MAC_CFG_SPEED_1000; 4274 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4275 4276 /* Set up the receive filter. */ 4277 alc_rxfilter(sc); 4278 alc_rxvlan(sc); 4279 4280 /* Acknowledge all pending interrupts and clear it. */ 4281 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4282 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4283 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4284 4285 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4286 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4287 4288 sc->alc_flags &= ~ALC_FLAG_LINK; 4289 /* Switch to the current media. */ 4290 alc_mediachange_locked(sc); 4291 4292 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4293} 4294 4295static void 4296alc_stop(struct alc_softc *sc) 4297{ 4298 struct ifnet *ifp; 4299 struct alc_txdesc *txd; 4300 struct alc_rxdesc *rxd; 4301 uint32_t reg; 4302 int i; 4303 4304 ALC_LOCK_ASSERT(sc); 4305 /* 4306 * Mark the interface down and cancel the watchdog timer. 4307 */ 4308 ifp = sc->alc_ifp; 4309 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4310 sc->alc_flags &= ~ALC_FLAG_LINK; 4311 callout_stop(&sc->alc_tick_ch); 4312 sc->alc_watchdog_timer = 0; 4313 alc_stats_update(sc); 4314 /* Disable interrupts. */ 4315 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4316 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4317 /* Disable DMA. */ 4318 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4319 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4320 reg |= DMA_CFG_SMB_DIS; 4321 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4322 DELAY(1000); 4323 /* Stop Rx/Tx MACs. */ 4324 alc_stop_mac(sc); 4325 /* Disable interrupts which might be touched in taskq handler. */ 4326 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4327 /* Disable L0s/L1s */ 4328 alc_aspm(sc, 0, IFM_UNKNOWN); 4329 /* Reclaim Rx buffers that have been processed. */ 4330 if (sc->alc_cdata.alc_rxhead != NULL) 4331 m_freem(sc->alc_cdata.alc_rxhead); 4332 ALC_RXCHAIN_RESET(sc); 4333 /* 4334 * Free Tx/Rx mbufs still in the queues. 4335 */ 4336 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4337 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4338 if (rxd->rx_m != NULL) { 4339 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4340 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4341 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4342 rxd->rx_dmamap); 4343 m_freem(rxd->rx_m); 4344 rxd->rx_m = NULL; 4345 } 4346 } 4347 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4348 txd = &sc->alc_cdata.alc_txdesc[i]; 4349 if (txd->tx_m != NULL) { 4350 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4351 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4352 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4353 txd->tx_dmamap); 4354 m_freem(txd->tx_m); 4355 txd->tx_m = NULL; 4356 } 4357 } 4358} 4359 4360static void 4361alc_stop_mac(struct alc_softc *sc) 4362{ 4363 uint32_t reg; 4364 int i; 4365 4366 alc_stop_queue(sc); 4367 /* Disable Rx/Tx MAC. */ 4368 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4369 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4370 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4371 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4372 } 4373 for (i = ALC_TIMEOUT; i > 0; i--) { 4374 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4375 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4376 break; 4377 DELAY(10); 4378 } 4379 if (i == 0) 4380 device_printf(sc->alc_dev, 4381 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4382} 4383 4384static void 4385alc_start_queue(struct alc_softc *sc) 4386{ 4387 uint32_t qcfg[] = { 4388 0, 4389 RXQ_CFG_QUEUE0_ENB, 4390 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4391 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4392 RXQ_CFG_ENB 4393 }; 4394 uint32_t cfg; 4395 4396 ALC_LOCK_ASSERT(sc); 4397 4398 /* Enable RxQ. */ 4399 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4400 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4401 cfg &= ~RXQ_CFG_ENB; 4402 cfg |= qcfg[1]; 4403 } else 4404 cfg |= RXQ_CFG_QUEUE0_ENB; 4405 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4406 /* Enable TxQ. */ 4407 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4408 cfg |= TXQ_CFG_ENB; 4409 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4410} 4411 4412static void 4413alc_stop_queue(struct alc_softc *sc) 4414{ 4415 uint32_t reg; 4416 int i; 4417 4418 /* Disable RxQ. */ 4419 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4420 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4421 if ((reg & RXQ_CFG_ENB) != 0) { 4422 reg &= ~RXQ_CFG_ENB; 4423 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4424 } 4425 } else { 4426 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4427 reg &= ~RXQ_CFG_QUEUE0_ENB; 4428 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4429 } 4430 } 4431 /* Disable TxQ. */ 4432 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4433 if ((reg & TXQ_CFG_ENB) != 0) { 4434 reg &= ~TXQ_CFG_ENB; 4435 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4436 } 4437 DELAY(40); 4438 for (i = ALC_TIMEOUT; i > 0; i--) { 4439 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4440 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4441 break; 4442 DELAY(10); 4443 } 4444 if (i == 0) 4445 device_printf(sc->alc_dev, 4446 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4447} 4448 4449static void 4450alc_init_tx_ring(struct alc_softc *sc) 4451{ 4452 struct alc_ring_data *rd; 4453 struct alc_txdesc *txd; 4454 int i; 4455 4456 ALC_LOCK_ASSERT(sc); 4457 4458 sc->alc_cdata.alc_tx_prod = 0; 4459 sc->alc_cdata.alc_tx_cons = 0; 4460 sc->alc_cdata.alc_tx_cnt = 0; 4461 4462 rd = &sc->alc_rdata; 4463 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4464 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4465 txd = &sc->alc_cdata.alc_txdesc[i]; 4466 txd->tx_m = NULL; 4467 } 4468 4469 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4470 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4471} 4472 4473static int 4474alc_init_rx_ring(struct alc_softc *sc) 4475{ 4476 struct alc_ring_data *rd; 4477 struct alc_rxdesc *rxd; 4478 int i; 4479 4480 ALC_LOCK_ASSERT(sc); 4481 4482 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4483 sc->alc_morework = 0; 4484 rd = &sc->alc_rdata; 4485 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4486 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4487 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4488 rxd->rx_m = NULL; 4489 rxd->rx_desc = &rd->alc_rx_ring[i]; 4490 if (alc_newbuf(sc, rxd) != 0) 4491 return (ENOBUFS); 4492 } 4493 4494 /* 4495 * Since controller does not update Rx descriptors, driver 4496 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4497 * is enough to ensure coherence. 4498 */ 4499 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4500 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4501 /* Let controller know availability of new Rx buffers. */ 4502 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4503 4504 return (0); 4505} 4506 4507static void 4508alc_init_rr_ring(struct alc_softc *sc) 4509{ 4510 struct alc_ring_data *rd; 4511 4512 ALC_LOCK_ASSERT(sc); 4513 4514 sc->alc_cdata.alc_rr_cons = 0; 4515 ALC_RXCHAIN_RESET(sc); 4516 4517 rd = &sc->alc_rdata; 4518 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4519 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4520 sc->alc_cdata.alc_rr_ring_map, 4521 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4522} 4523 4524static void 4525alc_init_cmb(struct alc_softc *sc) 4526{ 4527 struct alc_ring_data *rd; 4528 4529 ALC_LOCK_ASSERT(sc); 4530 4531 rd = &sc->alc_rdata; 4532 bzero(rd->alc_cmb, ALC_CMB_SZ); 4533 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4534 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4535} 4536 4537static void 4538alc_init_smb(struct alc_softc *sc) 4539{ 4540 struct alc_ring_data *rd; 4541 4542 ALC_LOCK_ASSERT(sc); 4543 4544 rd = &sc->alc_rdata; 4545 bzero(rd->alc_smb, ALC_SMB_SZ); 4546 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4547 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4548} 4549 4550static void 4551alc_rxvlan(struct alc_softc *sc) 4552{ 4553 struct ifnet *ifp; 4554 uint32_t reg; 4555 4556 ALC_LOCK_ASSERT(sc); 4557 4558 ifp = sc->alc_ifp; 4559 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4560 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4561 reg |= MAC_CFG_VLAN_TAG_STRIP; 4562 else 4563 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4564 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4565} 4566 4567static void 4568alc_rxfilter(struct alc_softc *sc) 4569{ 4570 struct ifnet *ifp; 4571 struct ifmultiaddr *ifma; 4572 uint32_t crc; 4573 uint32_t mchash[2]; 4574 uint32_t rxcfg; 4575 4576 ALC_LOCK_ASSERT(sc); 4577 4578 ifp = sc->alc_ifp; 4579 4580 bzero(mchash, sizeof(mchash)); 4581 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4582 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4583 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4584 rxcfg |= MAC_CFG_BCAST; 4585 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4586 if ((ifp->if_flags & IFF_PROMISC) != 0) 4587 rxcfg |= MAC_CFG_PROMISC; 4588 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4589 rxcfg |= MAC_CFG_ALLMULTI; 4590 mchash[0] = 0xFFFFFFFF; 4591 mchash[1] = 0xFFFFFFFF; 4592 goto chipit; 4593 } 4594 4595 if_maddr_rlock(ifp); 4596 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 4597 if (ifma->ifma_addr->sa_family != AF_LINK) 4598 continue; 4599 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 4600 ifma->ifma_addr), ETHER_ADDR_LEN); 4601 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4602 } 4603 if_maddr_runlock(ifp); 4604 4605chipit: 4606 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4607 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4608 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4609} 4610 4611static int 4612sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4613{ 4614 int error, value; 4615 4616 if (arg1 == NULL) 4617 return (EINVAL); 4618 value = *(int *)arg1; 4619 error = sysctl_handle_int(oidp, &value, 0, req); 4620 if (error || req->newptr == NULL) 4621 return (error); 4622 if (value < low || value > high) 4623 return (EINVAL); 4624 *(int *)arg1 = value; 4625 4626 return (0); 4627} 4628 4629static int 4630sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4631{ 4632 return (sysctl_int_range(oidp, arg1, arg2, req, 4633 ALC_PROC_MIN, ALC_PROC_MAX)); 4634} 4635 4636static int 4637sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4638{ 4639 4640 return (sysctl_int_range(oidp, arg1, arg2, req, 4641 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4642} 4643