cpufunc.h revision 314530
1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD: stable/11/sys/arm/include/cpufunc.h 314530 2017-03-02 01:18:46Z ian $ 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> 50#include <machine/armreg.h> 51 52static __inline void 53breakpoint(void) 54{ 55 __asm(".word 0xe7ffffff"); 56} 57 58struct cpu_functions { 59 60 /* CPU functions */ 61 62 void (*cf_cpwait) (void); 63 64 /* MMU functions */ 65 66 u_int (*cf_control) (u_int bic, u_int eor); 67 void (*cf_setttb) (u_int ttb); 68 69 /* TLB functions */ 70 71 void (*cf_tlb_flushID) (void); 72 void (*cf_tlb_flushID_SE) (u_int va); 73 void (*cf_tlb_flushD) (void); 74 void (*cf_tlb_flushD_SE) (u_int va); 75 76 /* 77 * Cache operations: 78 * 79 * We define the following primitives: 80 * 81 * icache_sync_range Synchronize I-cache range 82 * 83 * dcache_wbinv_all Write-back and Invalidate D-cache 84 * dcache_wbinv_range Write-back and Invalidate D-cache range 85 * dcache_inv_range Invalidate D-cache range 86 * dcache_wb_range Write-back D-cache range 87 * 88 * idcache_wbinv_all Write-back and Invalidate D-cache, 89 * Invalidate I-cache 90 * idcache_wbinv_range Write-back and Invalidate D-cache, 91 * Invalidate I-cache range 92 * 93 * Note that the ARM term for "write-back" is "clean". We use 94 * the term "write-back" since it's a more common way to describe 95 * the operation. 96 * 97 * There are some rules that must be followed: 98 * 99 * ID-cache Invalidate All: 100 * Unlike other functions, this one must never write back. 101 * It is used to intialize the MMU when it is in an unknown 102 * state (such as when it may have lines tagged as valid 103 * that belong to a previous set of mappings). 104 * 105 * I-cache Sync range: 106 * The goal is to synchronize the instruction stream, 107 * so you may beed to write-back dirty D-cache blocks 108 * first. If a range is requested, and you can't 109 * synchronize just a range, you have to hit the whole 110 * thing. 111 * 112 * D-cache Write-Back and Invalidate range: 113 * If you can't WB-Inv a range, you must WB-Inv the 114 * entire D-cache. 115 * 116 * D-cache Invalidate: 117 * If you can't Inv the D-cache, you must Write-Back 118 * and Invalidate. Code that uses this operation 119 * MUST NOT assume that the D-cache will not be written 120 * back to memory. 121 * 122 * D-cache Write-Back: 123 * If you can't Write-back without doing an Inv, 124 * that's fine. Then treat this as a WB-Inv. 125 * Skipping the invalidate is merely an optimization. 126 * 127 * All operations: 128 * Valid virtual addresses must be passed to each 129 * cache operation. 130 */ 131 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 132 133 void (*cf_dcache_wbinv_all) (void); 134 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 135 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 136 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 137 138 void (*cf_idcache_inv_all) (void); 139 void (*cf_idcache_wbinv_all) (void); 140 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 141 void (*cf_l2cache_wbinv_all) (void); 142 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 143 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 144 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 145 void (*cf_l2cache_drain_writebuf) (void); 146 147 /* Other functions */ 148 149 void (*cf_drain_writebuf) (void); 150 151 void (*cf_sleep) (int mode); 152 153 /* Soft functions */ 154 155 void (*cf_context_switch) (void); 156 157 void (*cf_setup) (void); 158}; 159 160extern struct cpu_functions cpufuncs; 161extern u_int cputype; 162 163#if __ARM_ARCH < 6 164#define cpu_cpwait() cpufuncs.cf_cpwait() 165#endif 166 167#define cpu_control(c, e) cpufuncs.cf_control(c, e) 168#if __ARM_ARCH < 6 169#define cpu_setttb(t) cpufuncs.cf_setttb(t) 170 171#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 172#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 173#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 174#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 175 176#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 177 178#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 179#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 180#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 181#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 182 183#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 184#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 185#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 186#endif 187#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 188#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 189#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 190#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 191#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 192 193#if __ARM_ARCH < 6 194#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 195#endif 196#define cpu_sleep(m) cpufuncs.cf_sleep(m) 197 198#define cpu_setup() cpufuncs.cf_setup() 199 200int set_cpufuncs (void); 201#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 202#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 203 204void cpufunc_nullop (void); 205u_int cpu_ident (void); 206u_int cpufunc_control (u_int clear, u_int bic); 207void cpu_domains (u_int domains); 208u_int cpu_faultstatus (void); 209u_int cpu_faultaddress (void); 210u_int cpu_get_control (void); 211u_int cpu_pfr (int); 212 213#if defined(CPU_FA526) 214void fa526_setup (void); 215void fa526_setttb (u_int ttb); 216void fa526_context_switch (void); 217void fa526_cpu_sleep (int); 218void fa526_tlb_flushID_SE (u_int); 219 220void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 221void fa526_dcache_wbinv_all (void); 222void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 223void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 224void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 225void fa526_idcache_wbinv_all(void); 226void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 227#endif 228 229 230#if defined(CPU_ARM9) || defined(CPU_ARM9E) 231void arm9_setttb (u_int); 232void arm9_tlb_flushID_SE (u_int va); 233void arm9_context_switch (void); 234#endif 235 236#if defined(CPU_ARM9) 237void arm9_icache_sync_range (vm_offset_t, vm_size_t); 238 239void arm9_dcache_wbinv_all (void); 240void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 241void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 242void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 243 244void arm9_idcache_wbinv_all (void); 245void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 246 247void arm9_setup (void); 248 249extern unsigned arm9_dcache_sets_max; 250extern unsigned arm9_dcache_sets_inc; 251extern unsigned arm9_dcache_index_max; 252extern unsigned arm9_dcache_index_inc; 253#endif 254 255#if defined(CPU_ARM9E) 256void arm10_setup (void); 257 258u_int sheeva_control_ext (u_int, u_int); 259void sheeva_cpu_sleep (int); 260void sheeva_setttb (u_int); 261void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 262void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 263void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 264void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 265 266void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 267void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 268void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 269void sheeva_l2cache_wbinv_all (void); 270#endif 271 272#if defined(CPU_MV_PJ4B) 273void armv6_idcache_wbinv_all (void); 274#endif 275#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) 276void armv7_setttb (u_int); 277void armv7_tlb_flushID (void); 278void armv7_tlb_flushID_SE (u_int); 279void armv7_icache_sync_range (vm_offset_t, vm_size_t); 280void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 281void armv7_idcache_inv_all (void); 282void armv7_dcache_wbinv_all (void); 283void armv7_idcache_wbinv_all (void); 284void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 285void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 286void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 287void armv7_cpu_sleep (int); 288void armv7_setup (void); 289void armv7_context_switch (void); 290void armv7_drain_writebuf (void); 291u_int armv7_auxctrl (u_int, u_int); 292 293void armadaxp_idcache_wbinv_all (void); 294 295void cortexa_setup (void); 296#endif 297#if defined(CPU_MV_PJ4B) 298void pj4b_config (void); 299void pj4bv7_setup (void); 300#endif 301 302#if defined(CPU_ARM1176) 303void arm11_tlb_flushID (void); 304void arm11_tlb_flushID_SE (u_int); 305void arm11_tlb_flushD (void); 306void arm11_tlb_flushD_SE (u_int va); 307 308void arm11_context_switch (void); 309 310void arm11_drain_writebuf (void); 311 312void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 313void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 314void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 315 316void armv6_idcache_inv_all (void); 317 318void arm11x6_setttb (u_int); 319void arm11x6_idcache_wbinv_all (void); 320void arm11x6_dcache_wbinv_all (void); 321void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 322void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 323void arm11x6_setup (void); 324void arm11x6_sleep (int); /* no ref. for errata */ 325#endif 326 327#if defined(CPU_ARM9E) 328void armv5_ec_setttb(u_int); 329 330void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 331 332void armv5_ec_dcache_wbinv_all(void); 333void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 334void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 335void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 336 337void armv5_ec_idcache_wbinv_all(void); 338void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 339#endif 340 341#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 342 defined(CPU_FA526) || \ 343 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 344 defined(CPU_XSCALE_81342) 345 346void armv4_tlb_flushID (void); 347void armv4_tlb_flushD (void); 348void armv4_tlb_flushD_SE (u_int va); 349 350void armv4_drain_writebuf (void); 351void armv4_idcache_inv_all (void); 352#endif 353 354#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 355 defined(CPU_XSCALE_81342) 356void xscale_cpwait (void); 357 358void xscale_cpu_sleep (int mode); 359 360u_int xscale_control (u_int clear, u_int bic); 361 362void xscale_setttb (u_int ttb); 363 364void xscale_tlb_flushID_SE (u_int va); 365 366void xscale_cache_flushID (void); 367void xscale_cache_flushI (void); 368void xscale_cache_flushD (void); 369void xscale_cache_flushD_SE (u_int entry); 370 371void xscale_cache_cleanID (void); 372void xscale_cache_cleanD (void); 373void xscale_cache_cleanD_E (u_int entry); 374 375void xscale_cache_clean_minidata (void); 376 377void xscale_cache_purgeID (void); 378void xscale_cache_purgeID_E (u_int entry); 379void xscale_cache_purgeD (void); 380void xscale_cache_purgeD_E (u_int entry); 381 382void xscale_cache_syncI (void); 383void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 384void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 385void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 386void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 387void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 388void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 389 390void xscale_context_switch (void); 391 392void xscale_setup (void); 393#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 394 395#ifdef CPU_XSCALE_81342 396 397void xscalec3_l2cache_purge (void); 398void xscalec3_cache_purgeID (void); 399void xscalec3_cache_purgeD (void); 400void xscalec3_cache_cleanID (void); 401void xscalec3_cache_cleanD (void); 402void xscalec3_cache_syncI (void); 403 404void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 405void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 406void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 407void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 408void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 409 410void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 411void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 412void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 413 414 415void xscalec3_setttb (u_int ttb); 416void xscalec3_context_switch (void); 417 418#endif /* CPU_XSCALE_81342 */ 419 420/* 421 * Macros for manipulating CPU interrupts 422 */ 423#if __ARM_ARCH < 6 424#define __ARM_INTR_BITS (PSR_I | PSR_F) 425#else 426#define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 427#endif 428 429static __inline uint32_t 430__set_cpsr(uint32_t bic, uint32_t eor) 431{ 432 uint32_t tmp, ret; 433 434 __asm __volatile( 435 "mrs %0, cpsr\n" /* Get the CPSR */ 436 "bic %1, %0, %2\n" /* Clear bits */ 437 "eor %1, %1, %3\n" /* XOR bits */ 438 "msr cpsr_xc, %1\n" /* Set the CPSR */ 439 : "=&r" (ret), "=&r" (tmp) 440 : "r" (bic), "r" (eor) : "memory"); 441 442 return ret; 443} 444 445static __inline uint32_t 446disable_interrupts(uint32_t mask) 447{ 448 449 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 450} 451 452static __inline uint32_t 453enable_interrupts(uint32_t mask) 454{ 455 456 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 457} 458 459static __inline uint32_t 460restore_interrupts(uint32_t old_cpsr) 461{ 462 463 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 464} 465 466static __inline register_t 467intr_disable(void) 468{ 469 470 return (disable_interrupts(PSR_I | PSR_F)); 471} 472 473static __inline void 474intr_restore(register_t s) 475{ 476 477 restore_interrupts(s); 478} 479#undef __ARM_INTR_BITS 480 481/* 482 * Functions to manipulate cpu r13 483 * (in arm/arm32/setstack.S) 484 */ 485 486void set_stackptr (u_int mode, u_int address); 487u_int get_stackptr (u_int mode); 488 489/* 490 * Miscellany 491 */ 492 493int get_pc_str_offset (void); 494 495/* 496 * CPU functions from locore.S 497 */ 498 499void cpu_reset (void) __attribute__((__noreturn__)); 500 501/* 502 * Cache info variables. 503 */ 504 505/* PRIMARY CACHE VARIABLES */ 506extern int arm_picache_size; 507extern int arm_picache_line_size; 508extern int arm_picache_ways; 509 510extern int arm_pdcache_size; /* and unified */ 511extern int arm_pdcache_line_size; 512extern int arm_pdcache_ways; 513 514extern int arm_pcache_type; 515extern int arm_pcache_unified; 516 517extern int arm_dcache_align; 518extern int arm_dcache_align_mask; 519 520extern u_int arm_cache_level; 521extern u_int arm_cache_loc; 522extern u_int arm_cache_type[14]; 523 524#endif /* _KERNEL */ 525#endif /* _MACHINE_CPUFUNC_H_ */ 526 527/* End of cpufunc.h */ 528