atphyreg.h revision 331722 
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/11/sys/dev/mii/atphyreg.h 331722 2018-03-29 02:50:57Z eadler $
28 */
29
30#ifndef	_DEV_MII_ATPHYREG_H_
31#define	_DEV_MII_ATPHYREG_H_
32
33/*
34 * Registers for the Attansic/Atheros Gigabit PHY.
35 */
36
37/* Special Control Register */
38#define ATPHY_SCR			0x10
39#define ATPHY_SCR_JABBER_DISABLE	0x0001
40#define ATPHY_SCR_POLARITY_REVERSAL	0x0002
41#define ATPHY_SCR_SQE_TEST		0x0004
42#define ATPHY_SCR_MAC_PDOWN		0x0008
43#define ATPHY_SCR_CLK125_DISABLE	0x0010
44#define ATPHY_SCR_MDI_MANUAL_MODE	0x0000
45#define ATPHY_SCR_MDIX_MANUAL_MODE	0x0020
46#define ATPHY_SCR_AUTO_X_1000T		0x0040
47#define ATPHY_SCR_AUTO_X_MODE		0x0060
48#define ATPHY_SCR_10BT_EXT_ENABLE	0x0080
49#define ATPHY_SCR_MII_5BIT_ENABLE	0x0100
50#define ATPHY_SCR_SCRAMBLER_DISABLE	0x0200
51#define ATPHY_SCR_FORCE_LINK_GOOD	0x0400
52#define ATPHY_SCR_ASSERT_CRS_ON_TX	0x0800
53
54/* Special Status Register. */
55#define ATPHY_SSR			0x11
56#define ATPHY_SSR_SPD_DPLX_RESOLVED	0x0800
57#define ATPHY_SSR_DUPLEX		0x2000
58#define ATPHY_SSR_SPEED_MASK		0xC000
59#define ATPHY_SSR_10MBS			0x0000
60#define ATPHY_SSR_100MBS		0x4000
61#define ATPHY_SSR_1000MBS		0x8000
62
63#endif	/* _DEV_MII_ATPHYREG_H_ */
64