efx_ev.c revision 331722
1/*- 2 * Copyright (c) 2007-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/11/sys/dev/sfxge/common/efx_ev.c 331722 2018-03-29 02:50:57Z eadler $"); 33 34#include "efx.h" 35#include "efx_impl.h" 36#if EFSYS_OPT_MON_MCDI 37#include "mcdi_mon.h" 38#endif 39 40#if EFSYS_OPT_QSTATS 41#define EFX_EV_QSTAT_INCR(_eep, _stat) \ 42 do { \ 43 (_eep)->ee_stat[_stat]++; \ 44 _NOTE(CONSTANTCONDITION) \ 45 } while (B_FALSE) 46#else 47#define EFX_EV_QSTAT_INCR(_eep, _stat) 48#endif 49 50#define EFX_EV_PRESENT(_qword) \ 51 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ 52 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) 53 54 55 56#if EFSYS_OPT_SIENA 57 58static __checkReturn efx_rc_t 59siena_ev_init( 60 __in efx_nic_t *enp); 61 62static void 63siena_ev_fini( 64 __in efx_nic_t *enp); 65 66static __checkReturn efx_rc_t 67siena_ev_qcreate( 68 __in efx_nic_t *enp, 69 __in unsigned int index, 70 __in efsys_mem_t *esmp, 71 __in size_t n, 72 __in uint32_t id, 73 __in uint32_t us, 74 __in uint32_t flags, 75 __in efx_evq_t *eep); 76 77static void 78siena_ev_qdestroy( 79 __in efx_evq_t *eep); 80 81static __checkReturn efx_rc_t 82siena_ev_qprime( 83 __in efx_evq_t *eep, 84 __in unsigned int count); 85 86static void 87siena_ev_qpost( 88 __in efx_evq_t *eep, 89 __in uint16_t data); 90 91static __checkReturn efx_rc_t 92siena_ev_qmoderate( 93 __in efx_evq_t *eep, 94 __in unsigned int us); 95 96#if EFSYS_OPT_QSTATS 97static void 98siena_ev_qstats_update( 99 __in efx_evq_t *eep, 100 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 101 102#endif 103 104#endif /* EFSYS_OPT_SIENA */ 105 106#if EFSYS_OPT_SIENA 107static const efx_ev_ops_t __efx_ev_siena_ops = { 108 siena_ev_init, /* eevo_init */ 109 siena_ev_fini, /* eevo_fini */ 110 siena_ev_qcreate, /* eevo_qcreate */ 111 siena_ev_qdestroy, /* eevo_qdestroy */ 112 siena_ev_qprime, /* eevo_qprime */ 113 siena_ev_qpost, /* eevo_qpost */ 114 siena_ev_qmoderate, /* eevo_qmoderate */ 115#if EFSYS_OPT_QSTATS 116 siena_ev_qstats_update, /* eevo_qstats_update */ 117#endif 118}; 119#endif /* EFSYS_OPT_SIENA */ 120 121#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 122static const efx_ev_ops_t __efx_ev_ef10_ops = { 123 ef10_ev_init, /* eevo_init */ 124 ef10_ev_fini, /* eevo_fini */ 125 ef10_ev_qcreate, /* eevo_qcreate */ 126 ef10_ev_qdestroy, /* eevo_qdestroy */ 127 ef10_ev_qprime, /* eevo_qprime */ 128 ef10_ev_qpost, /* eevo_qpost */ 129 ef10_ev_qmoderate, /* eevo_qmoderate */ 130#if EFSYS_OPT_QSTATS 131 ef10_ev_qstats_update, /* eevo_qstats_update */ 132#endif 133}; 134#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 135 136 137 __checkReturn efx_rc_t 138efx_ev_init( 139 __in efx_nic_t *enp) 140{ 141 const efx_ev_ops_t *eevop; 142 efx_rc_t rc; 143 144 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 145 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 146 147 if (enp->en_mod_flags & EFX_MOD_EV) { 148 rc = EINVAL; 149 goto fail1; 150 } 151 152 switch (enp->en_family) { 153#if EFSYS_OPT_SIENA 154 case EFX_FAMILY_SIENA: 155 eevop = &__efx_ev_siena_ops; 156 break; 157#endif /* EFSYS_OPT_SIENA */ 158 159#if EFSYS_OPT_HUNTINGTON 160 case EFX_FAMILY_HUNTINGTON: 161 eevop = &__efx_ev_ef10_ops; 162 break; 163#endif /* EFSYS_OPT_HUNTINGTON */ 164 165#if EFSYS_OPT_MEDFORD 166 case EFX_FAMILY_MEDFORD: 167 eevop = &__efx_ev_ef10_ops; 168 break; 169#endif /* EFSYS_OPT_MEDFORD */ 170 171 default: 172 EFSYS_ASSERT(0); 173 rc = ENOTSUP; 174 goto fail1; 175 } 176 177 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 178 179 if ((rc = eevop->eevo_init(enp)) != 0) 180 goto fail2; 181 182 enp->en_eevop = eevop; 183 enp->en_mod_flags |= EFX_MOD_EV; 184 return (0); 185 186fail2: 187 EFSYS_PROBE(fail2); 188 189fail1: 190 EFSYS_PROBE1(fail1, efx_rc_t, rc); 191 192 enp->en_eevop = NULL; 193 enp->en_mod_flags &= ~EFX_MOD_EV; 194 return (rc); 195} 196 197 void 198efx_ev_fini( 199 __in efx_nic_t *enp) 200{ 201 const efx_ev_ops_t *eevop = enp->en_eevop; 202 203 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 204 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 205 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 206 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 207 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 208 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 209 210 eevop->eevo_fini(enp); 211 212 enp->en_eevop = NULL; 213 enp->en_mod_flags &= ~EFX_MOD_EV; 214} 215 216 217 __checkReturn efx_rc_t 218efx_ev_qcreate( 219 __in efx_nic_t *enp, 220 __in unsigned int index, 221 __in efsys_mem_t *esmp, 222 __in size_t n, 223 __in uint32_t id, 224 __in uint32_t us, 225 __in uint32_t flags, 226 __deref_out efx_evq_t **eepp) 227{ 228 const efx_ev_ops_t *eevop = enp->en_eevop; 229 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 230 efx_evq_t *eep; 231 efx_rc_t rc; 232 233 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 234 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 235 236 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); 237 238 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) { 239 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT: 240 break; 241 case EFX_EVQ_FLAGS_NOTIFY_DISABLED: 242 if (us != 0) { 243 rc = EINVAL; 244 goto fail1; 245 } 246 break; 247 default: 248 rc = EINVAL; 249 goto fail2; 250 } 251 252 /* Allocate an EVQ object */ 253 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); 254 if (eep == NULL) { 255 rc = ENOMEM; 256 goto fail3; 257 } 258 259 eep->ee_magic = EFX_EVQ_MAGIC; 260 eep->ee_enp = enp; 261 eep->ee_index = index; 262 eep->ee_mask = n - 1; 263 eep->ee_flags = flags; 264 eep->ee_esmp = esmp; 265 266 /* 267 * Set outputs before the queue is created because interrupts may be 268 * raised for events immediately after the queue is created, before the 269 * function call below returns. See bug58606. 270 * 271 * The eepp pointer passed in by the client must therefore point to data 272 * shared with the client's event processing context. 273 */ 274 enp->en_ev_qcount++; 275 *eepp = eep; 276 277 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags, 278 eep)) != 0) 279 goto fail4; 280 281 return (0); 282 283fail4: 284 EFSYS_PROBE(fail4); 285 286 *eepp = NULL; 287 enp->en_ev_qcount--; 288 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 289fail3: 290 EFSYS_PROBE(fail3); 291fail2: 292 EFSYS_PROBE(fail2); 293fail1: 294 EFSYS_PROBE1(fail1, efx_rc_t, rc); 295 return (rc); 296} 297 298 void 299efx_ev_qdestroy( 300 __in efx_evq_t *eep) 301{ 302 efx_nic_t *enp = eep->ee_enp; 303 const efx_ev_ops_t *eevop = enp->en_eevop; 304 305 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 306 307 EFSYS_ASSERT(enp->en_ev_qcount != 0); 308 --enp->en_ev_qcount; 309 310 eevop->eevo_qdestroy(eep); 311 312 /* Free the EVQ object */ 313 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 314} 315 316 __checkReturn efx_rc_t 317efx_ev_qprime( 318 __in efx_evq_t *eep, 319 __in unsigned int count) 320{ 321 efx_nic_t *enp = eep->ee_enp; 322 const efx_ev_ops_t *eevop = enp->en_eevop; 323 efx_rc_t rc; 324 325 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 326 327 if (!(enp->en_mod_flags & EFX_MOD_INTR)) { 328 rc = EINVAL; 329 goto fail1; 330 } 331 332 if ((rc = eevop->eevo_qprime(eep, count)) != 0) 333 goto fail2; 334 335 return (0); 336 337fail2: 338 EFSYS_PROBE(fail2); 339fail1: 340 EFSYS_PROBE1(fail1, efx_rc_t, rc); 341 return (rc); 342} 343 344 __checkReturn boolean_t 345efx_ev_qpending( 346 __in efx_evq_t *eep, 347 __in unsigned int count) 348{ 349 size_t offset; 350 efx_qword_t qword; 351 352 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 353 354 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 355 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); 356 357 return (EFX_EV_PRESENT(qword)); 358} 359 360#if EFSYS_OPT_EV_PREFETCH 361 362 void 363efx_ev_qprefetch( 364 __in efx_evq_t *eep, 365 __in unsigned int count) 366{ 367 unsigned int offset; 368 369 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 370 371 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 372 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 373} 374 375#endif /* EFSYS_OPT_EV_PREFETCH */ 376 377#define EFX_EV_BATCH 8 378 379 void 380efx_ev_qpoll( 381 __in efx_evq_t *eep, 382 __inout unsigned int *countp, 383 __in const efx_ev_callbacks_t *eecp, 384 __in_opt void *arg) 385{ 386 efx_qword_t ev[EFX_EV_BATCH]; 387 unsigned int batch; 388 unsigned int total; 389 unsigned int count; 390 unsigned int index; 391 size_t offset; 392 393 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */ 394 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN); 395 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH); 396 397 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV); 398 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV); 399 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV); 400 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV == 401 FSE_AZ_EV_CODE_DRV_GEN_EV); 402#if EFSYS_OPT_MCDI 403 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV == 404 FSE_AZ_EV_CODE_MCDI_EVRESPONSE); 405#endif 406 407 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 408 EFSYS_ASSERT(countp != NULL); 409 EFSYS_ASSERT(eecp != NULL); 410 411 count = *countp; 412 do { 413 /* Read up until the end of the batch period */ 414 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1)); 415 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 416 for (total = 0; total < batch; ++total) { 417 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total])); 418 419 if (!EFX_EV_PRESENT(ev[total])) 420 break; 421 422 EFSYS_PROBE3(event, unsigned int, eep->ee_index, 423 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1), 424 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0)); 425 426 offset += sizeof (efx_qword_t); 427 } 428 429#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1) 430 /* 431 * Prefetch the next batch when we get within PREFETCH_PERIOD 432 * of a completed batch. If the batch is smaller, then prefetch 433 * immediately. 434 */ 435 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD) 436 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 437#endif /* EFSYS_OPT_EV_PREFETCH */ 438 439 /* Process the batch of events */ 440 for (index = 0; index < total; ++index) { 441 boolean_t should_abort; 442 uint32_t code; 443 444#if EFSYS_OPT_EV_PREFETCH 445 /* Prefetch if we've now reached the batch period */ 446 if (total == batch && 447 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) { 448 offset = (count + batch) & eep->ee_mask; 449 offset *= sizeof (efx_qword_t); 450 451 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 452 } 453#endif /* EFSYS_OPT_EV_PREFETCH */ 454 455 EFX_EV_QSTAT_INCR(eep, EV_ALL); 456 457 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE); 458 switch (code) { 459 case FSE_AZ_EV_CODE_RX_EV: 460 should_abort = eep->ee_rx(eep, 461 &(ev[index]), eecp, arg); 462 break; 463 case FSE_AZ_EV_CODE_TX_EV: 464 should_abort = eep->ee_tx(eep, 465 &(ev[index]), eecp, arg); 466 break; 467 case FSE_AZ_EV_CODE_DRIVER_EV: 468 should_abort = eep->ee_driver(eep, 469 &(ev[index]), eecp, arg); 470 break; 471 case FSE_AZ_EV_CODE_DRV_GEN_EV: 472 should_abort = eep->ee_drv_gen(eep, 473 &(ev[index]), eecp, arg); 474 break; 475#if EFSYS_OPT_MCDI 476 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE: 477 should_abort = eep->ee_mcdi(eep, 478 &(ev[index]), eecp, arg); 479 break; 480#endif 481 case FSE_AZ_EV_CODE_GLOBAL_EV: 482 if (eep->ee_global) { 483 should_abort = eep->ee_global(eep, 484 &(ev[index]), eecp, arg); 485 break; 486 } 487 /* else fallthrough */ 488 default: 489 EFSYS_PROBE3(bad_event, 490 unsigned int, eep->ee_index, 491 uint32_t, 492 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1), 493 uint32_t, 494 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0)); 495 496 EFSYS_ASSERT(eecp->eec_exception != NULL); 497 (void) eecp->eec_exception(arg, 498 EFX_EXCEPTION_EV_ERROR, code); 499 should_abort = B_TRUE; 500 } 501 if (should_abort) { 502 /* Ignore subsequent events */ 503 total = index + 1; 504 break; 505 } 506 } 507 508 /* 509 * Now that the hardware has most likely moved onto dma'ing 510 * into the next cache line, clear the processed events. Take 511 * care to only clear out events that we've processed 512 */ 513 EFX_SET_QWORD(ev[0]); 514 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 515 for (index = 0; index < total; ++index) { 516 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0])); 517 offset += sizeof (efx_qword_t); 518 } 519 520 count += total; 521 522 } while (total == batch); 523 524 *countp = count; 525} 526 527 void 528efx_ev_qpost( 529 __in efx_evq_t *eep, 530 __in uint16_t data) 531{ 532 efx_nic_t *enp = eep->ee_enp; 533 const efx_ev_ops_t *eevop = enp->en_eevop; 534 535 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 536 537 EFSYS_ASSERT(eevop != NULL && 538 eevop->eevo_qpost != NULL); 539 540 eevop->eevo_qpost(eep, data); 541} 542 543 __checkReturn efx_rc_t 544efx_ev_usecs_to_ticks( 545 __in efx_nic_t *enp, 546 __in unsigned int us, 547 __out unsigned int *ticksp) 548{ 549 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 550 unsigned int ticks; 551 552 /* Convert microseconds to a timer tick count */ 553 if (us == 0) 554 ticks = 0; 555 else if (us * 1000 < encp->enc_evq_timer_quantum_ns) 556 ticks = 1; /* Never round down to zero */ 557 else 558 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns; 559 560 *ticksp = ticks; 561 return (0); 562} 563 564 __checkReturn efx_rc_t 565efx_ev_qmoderate( 566 __in efx_evq_t *eep, 567 __in unsigned int us) 568{ 569 efx_nic_t *enp = eep->ee_enp; 570 const efx_ev_ops_t *eevop = enp->en_eevop; 571 efx_rc_t rc; 572 573 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 574 575 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) == 576 EFX_EVQ_FLAGS_NOTIFY_DISABLED) { 577 rc = EINVAL; 578 goto fail1; 579 } 580 581 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0) 582 goto fail2; 583 584 return (0); 585 586fail2: 587 EFSYS_PROBE(fail2); 588fail1: 589 EFSYS_PROBE1(fail1, efx_rc_t, rc); 590 return (rc); 591} 592 593#if EFSYS_OPT_QSTATS 594 void 595efx_ev_qstats_update( 596 __in efx_evq_t *eep, 597 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 598 599{ efx_nic_t *enp = eep->ee_enp; 600 const efx_ev_ops_t *eevop = enp->en_eevop; 601 602 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 603 604 eevop->eevo_qstats_update(eep, stat); 605} 606 607#endif /* EFSYS_OPT_QSTATS */ 608 609#if EFSYS_OPT_SIENA 610 611static __checkReturn efx_rc_t 612siena_ev_init( 613 __in efx_nic_t *enp) 614{ 615 efx_oword_t oword; 616 617 /* 618 * Program the event queue for receive and transmit queue 619 * flush events. 620 */ 621 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword); 622 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0); 623 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword); 624 625 return (0); 626 627} 628 629static __checkReturn boolean_t 630siena_ev_rx_not_ok( 631 __in efx_evq_t *eep, 632 __in efx_qword_t *eqp, 633 __in uint32_t label, 634 __in uint32_t id, 635 __inout uint16_t *flagsp) 636{ 637 boolean_t ignore = B_FALSE; 638 639 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) { 640 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC); 641 EFSYS_PROBE(tobe_disc); 642 /* 643 * Assume this is a unicast address mismatch, unless below 644 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or 645 * EV_RX_PAUSE_FRM_ERR is set. 646 */ 647 (*flagsp) |= EFX_ADDR_MISMATCH; 648 } 649 650 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) { 651 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id); 652 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); 653 (*flagsp) |= EFX_DISCARD; 654 655#if EFSYS_OPT_RX_SCATTER 656 /* 657 * Lookout for payload queue ran dry errors and ignore them. 658 * 659 * Sadly for the header/data split cases, the descriptor 660 * pointer in this event refers to the header queue and 661 * therefore cannot be easily detected as duplicate. 662 * So we drop these and rely on the receive processing seeing 663 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard 664 * the partially received packet. 665 */ 666 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) && 667 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && 668 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) 669 ignore = B_TRUE; 670#endif /* EFSYS_OPT_RX_SCATTER */ 671 } 672 673 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { 674 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR); 675 EFSYS_PROBE(crc_err); 676 (*flagsp) &= ~EFX_ADDR_MISMATCH; 677 (*flagsp) |= EFX_DISCARD; 678 } 679 680 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) { 681 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR); 682 EFSYS_PROBE(pause_frm_err); 683 (*flagsp) &= ~EFX_ADDR_MISMATCH; 684 (*flagsp) |= EFX_DISCARD; 685 } 686 687 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) { 688 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR); 689 EFSYS_PROBE(owner_id_err); 690 (*flagsp) |= EFX_DISCARD; 691 } 692 693 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) { 694 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR); 695 EFSYS_PROBE(ipv4_err); 696 (*flagsp) &= ~EFX_CKSUM_IPV4; 697 } 698 699 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) { 700 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR); 701 EFSYS_PROBE(udp_chk_err); 702 (*flagsp) &= ~EFX_CKSUM_TCPUDP; 703 } 704 705 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) { 706 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR); 707 708 /* 709 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This 710 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error 711 * condition. 712 */ 713 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP); 714 } 715 716 return (ignore); 717} 718 719static __checkReturn boolean_t 720siena_ev_rx( 721 __in efx_evq_t *eep, 722 __in efx_qword_t *eqp, 723 __in const efx_ev_callbacks_t *eecp, 724 __in_opt void *arg) 725{ 726 uint32_t id; 727 uint32_t size; 728 uint32_t label; 729 boolean_t ok; 730#if EFSYS_OPT_RX_SCATTER 731 boolean_t sop; 732 boolean_t jumbo_cont; 733#endif /* EFSYS_OPT_RX_SCATTER */ 734 uint32_t hdr_type; 735 boolean_t is_v6; 736 uint16_t flags; 737 boolean_t ignore; 738 boolean_t should_abort; 739 740 EFX_EV_QSTAT_INCR(eep, EV_RX); 741 742 /* Basic packet information */ 743 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR); 744 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT); 745 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); 746 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); 747 748#if EFSYS_OPT_RX_SCATTER 749 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); 750 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); 751#endif /* EFSYS_OPT_RX_SCATTER */ 752 753 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); 754 755 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0); 756 757 /* 758 * If packet is marked as OK and packet type is TCP/IP or 759 * UDP/IP or other IP, then we can rely on the hardware checksums. 760 */ 761 switch (hdr_type) { 762 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP: 763 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP; 764 if (is_v6) { 765 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6); 766 flags |= EFX_PKT_IPV6; 767 } else { 768 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4); 769 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 770 } 771 break; 772 773 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP: 774 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP; 775 if (is_v6) { 776 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6); 777 flags |= EFX_PKT_IPV6; 778 } else { 779 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4); 780 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 781 } 782 break; 783 784 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: 785 if (is_v6) { 786 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6); 787 flags = EFX_PKT_IPV6; 788 } else { 789 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4); 790 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 791 } 792 break; 793 794 case FSE_AZ_RX_EV_HDR_TYPE_OTHER: 795 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP); 796 flags = 0; 797 break; 798 799 default: 800 EFSYS_ASSERT(B_FALSE); 801 flags = 0; 802 break; 803 } 804 805#if EFSYS_OPT_RX_SCATTER 806 /* Report scatter and header/lookahead split buffer flags */ 807 if (sop) 808 flags |= EFX_PKT_START; 809 if (jumbo_cont) 810 flags |= EFX_PKT_CONT; 811#endif /* EFSYS_OPT_RX_SCATTER */ 812 813 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ 814 if (!ok) { 815 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags); 816 if (ignore) { 817 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 818 uint32_t, size, uint16_t, flags); 819 820 return (B_FALSE); 821 } 822 } 823 824 /* If we're not discarding the packet then it is ok */ 825 if (~flags & EFX_DISCARD) 826 EFX_EV_QSTAT_INCR(eep, EV_RX_OK); 827 828 /* Detect multicast packets that didn't match the filter */ 829 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) { 830 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT); 831 832 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) { 833 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH); 834 } else { 835 EFSYS_PROBE(mcast_mismatch); 836 flags |= EFX_ADDR_MISMATCH; 837 } 838 } else { 839 flags |= EFX_PKT_UNICAST; 840 } 841 842 /* 843 * The packet parser in Siena can abort parsing packets under 844 * certain error conditions, setting the PKT_NOT_PARSED bit 845 * (which clears PKT_OK). If this is set, then don't trust 846 * the PKT_TYPE field. 847 */ 848 if (!ok) { 849 uint32_t parse_err; 850 851 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED); 852 if (parse_err != 0) 853 flags |= EFX_CHECK_VLAN; 854 } 855 856 if (~flags & EFX_CHECK_VLAN) { 857 uint32_t pkt_type; 858 859 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE); 860 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN) 861 flags |= EFX_PKT_VLAN_TAGGED; 862 } 863 864 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 865 uint32_t, size, uint16_t, flags); 866 867 EFSYS_ASSERT(eecp->eec_rx != NULL); 868 should_abort = eecp->eec_rx(arg, label, id, size, flags); 869 870 return (should_abort); 871} 872 873static __checkReturn boolean_t 874siena_ev_tx( 875 __in efx_evq_t *eep, 876 __in efx_qword_t *eqp, 877 __in const efx_ev_callbacks_t *eecp, 878 __in_opt void *arg) 879{ 880 uint32_t id; 881 uint32_t label; 882 boolean_t should_abort; 883 884 EFX_EV_QSTAT_INCR(eep, EV_TX); 885 886 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 && 887 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && 888 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && 889 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { 890 891 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); 892 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); 893 894 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); 895 896 EFSYS_ASSERT(eecp->eec_tx != NULL); 897 should_abort = eecp->eec_tx(arg, label, id); 898 899 return (should_abort); 900 } 901 902 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0) 903 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 904 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 905 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 906 907 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0) 908 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR); 909 910 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0) 911 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG); 912 913 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0) 914 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL); 915 916 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED); 917 return (B_FALSE); 918} 919 920static __checkReturn boolean_t 921siena_ev_global( 922 __in efx_evq_t *eep, 923 __in efx_qword_t *eqp, 924 __in const efx_ev_callbacks_t *eecp, 925 __in_opt void *arg) 926{ 927 _NOTE(ARGUNUSED(eqp, eecp, arg)) 928 929 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL); 930 931 return (B_FALSE); 932} 933 934static __checkReturn boolean_t 935siena_ev_driver( 936 __in efx_evq_t *eep, 937 __in efx_qword_t *eqp, 938 __in const efx_ev_callbacks_t *eecp, 939 __in_opt void *arg) 940{ 941 boolean_t should_abort; 942 943 EFX_EV_QSTAT_INCR(eep, EV_DRIVER); 944 should_abort = B_FALSE; 945 946 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) { 947 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: { 948 uint32_t txq_index; 949 950 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); 951 952 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 953 954 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index); 955 956 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); 957 should_abort = eecp->eec_txq_flush_done(arg, txq_index); 958 959 break; 960 } 961 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: { 962 uint32_t rxq_index; 963 uint32_t failed; 964 965 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 966 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 967 968 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); 969 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL); 970 971 if (failed) { 972 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED); 973 974 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index); 975 976 should_abort = eecp->eec_rxq_flush_failed(arg, 977 rxq_index); 978 } else { 979 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); 980 981 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index); 982 983 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index); 984 } 985 986 break; 987 } 988 case FSE_AZ_EVQ_INIT_DONE_EV: 989 EFSYS_ASSERT(eecp->eec_initialized != NULL); 990 should_abort = eecp->eec_initialized(arg); 991 992 break; 993 994 case FSE_AZ_EVQ_NOT_EN_EV: 995 EFSYS_PROBE(evq_not_en); 996 break; 997 998 case FSE_AZ_SRM_UPD_DONE_EV: { 999 uint32_t code; 1000 1001 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE); 1002 1003 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 1004 1005 EFSYS_ASSERT(eecp->eec_sram != NULL); 1006 should_abort = eecp->eec_sram(arg, code); 1007 1008 break; 1009 } 1010 case FSE_AZ_WAKE_UP_EV: { 1011 uint32_t id; 1012 1013 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 1014 1015 EFSYS_ASSERT(eecp->eec_wake_up != NULL); 1016 should_abort = eecp->eec_wake_up(arg, id); 1017 1018 break; 1019 } 1020 case FSE_AZ_TX_PKT_NON_TCP_UDP: 1021 EFSYS_PROBE(tx_pkt_non_tcp_udp); 1022 break; 1023 1024 case FSE_AZ_TIMER_EV: { 1025 uint32_t id; 1026 1027 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 1028 1029 EFSYS_ASSERT(eecp->eec_timer != NULL); 1030 should_abort = eecp->eec_timer(arg, id); 1031 1032 break; 1033 } 1034 case FSE_AZ_RX_DSC_ERROR_EV: 1035 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR); 1036 1037 EFSYS_PROBE(rx_dsc_error); 1038 1039 EFSYS_ASSERT(eecp->eec_exception != NULL); 1040 should_abort = eecp->eec_exception(arg, 1041 EFX_EXCEPTION_RX_DSC_ERROR, 0); 1042 1043 break; 1044 1045 case FSE_AZ_TX_DSC_ERROR_EV: 1046 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR); 1047 1048 EFSYS_PROBE(tx_dsc_error); 1049 1050 EFSYS_ASSERT(eecp->eec_exception != NULL); 1051 should_abort = eecp->eec_exception(arg, 1052 EFX_EXCEPTION_TX_DSC_ERROR, 0); 1053 1054 break; 1055 1056 default: 1057 break; 1058 } 1059 1060 return (should_abort); 1061} 1062 1063static __checkReturn boolean_t 1064siena_ev_drv_gen( 1065 __in efx_evq_t *eep, 1066 __in efx_qword_t *eqp, 1067 __in const efx_ev_callbacks_t *eecp, 1068 __in_opt void *arg) 1069{ 1070 uint32_t data; 1071 boolean_t should_abort; 1072 1073 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); 1074 1075 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0); 1076 if (data >= ((uint32_t)1 << 16)) { 1077 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 1078 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 1079 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 1080 return (B_TRUE); 1081 } 1082 1083 EFSYS_ASSERT(eecp->eec_software != NULL); 1084 should_abort = eecp->eec_software(arg, (uint16_t)data); 1085 1086 return (should_abort); 1087} 1088 1089#if EFSYS_OPT_MCDI 1090 1091static __checkReturn boolean_t 1092siena_ev_mcdi( 1093 __in efx_evq_t *eep, 1094 __in efx_qword_t *eqp, 1095 __in const efx_ev_callbacks_t *eecp, 1096 __in_opt void *arg) 1097{ 1098 efx_nic_t *enp = eep->ee_enp; 1099 unsigned int code; 1100 boolean_t should_abort = B_FALSE; 1101 1102 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); 1103 1104 if (enp->en_family != EFX_FAMILY_SIENA) 1105 goto out; 1106 1107 EFSYS_ASSERT(eecp->eec_link_change != NULL); 1108 EFSYS_ASSERT(eecp->eec_exception != NULL); 1109#if EFSYS_OPT_MON_STATS 1110 EFSYS_ASSERT(eecp->eec_monitor != NULL); 1111#endif 1112 1113 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); 1114 1115 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); 1116 switch (code) { 1117 case MCDI_EVENT_CODE_BADSSERT: 1118 efx_mcdi_ev_death(enp, EINTR); 1119 break; 1120 1121 case MCDI_EVENT_CODE_CMDDONE: 1122 efx_mcdi_ev_cpl(enp, 1123 MCDI_EV_FIELD(eqp, CMDDONE_SEQ), 1124 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN), 1125 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO)); 1126 break; 1127 1128 case MCDI_EVENT_CODE_LINKCHANGE: { 1129 efx_link_mode_t link_mode; 1130 1131 siena_phy_link_ev(enp, eqp, &link_mode); 1132 should_abort = eecp->eec_link_change(arg, link_mode); 1133 break; 1134 } 1135 case MCDI_EVENT_CODE_SENSOREVT: { 1136#if EFSYS_OPT_MON_STATS 1137 efx_mon_stat_t id; 1138 efx_mon_stat_value_t value; 1139 efx_rc_t rc; 1140 1141 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) 1142 should_abort = eecp->eec_monitor(arg, id, value); 1143 else if (rc == ENOTSUP) { 1144 should_abort = eecp->eec_exception(arg, 1145 EFX_EXCEPTION_UNKNOWN_SENSOREVT, 1146 MCDI_EV_FIELD(eqp, DATA)); 1147 } else 1148 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ 1149#else 1150 should_abort = B_FALSE; 1151#endif 1152 break; 1153 } 1154 case MCDI_EVENT_CODE_SCHEDERR: 1155 /* Informational only */ 1156 break; 1157 1158 case MCDI_EVENT_CODE_REBOOT: 1159 efx_mcdi_ev_death(enp, EIO); 1160 break; 1161 1162 case MCDI_EVENT_CODE_MAC_STATS_DMA: 1163#if EFSYS_OPT_MAC_STATS 1164 if (eecp->eec_mac_stats != NULL) { 1165 eecp->eec_mac_stats(arg, 1166 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); 1167 } 1168#endif 1169 break; 1170 1171 case MCDI_EVENT_CODE_FWALERT: { 1172 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); 1173 1174 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) 1175 should_abort = eecp->eec_exception(arg, 1176 EFX_EXCEPTION_FWALERT_SRAM, 1177 MCDI_EV_FIELD(eqp, FWALERT_DATA)); 1178 else 1179 should_abort = eecp->eec_exception(arg, 1180 EFX_EXCEPTION_UNKNOWN_FWALERT, 1181 MCDI_EV_FIELD(eqp, DATA)); 1182 break; 1183 } 1184 1185 default: 1186 EFSYS_PROBE1(mc_pcol_error, int, code); 1187 break; 1188 } 1189 1190out: 1191 return (should_abort); 1192} 1193 1194#endif /* EFSYS_OPT_MCDI */ 1195 1196static __checkReturn efx_rc_t 1197siena_ev_qprime( 1198 __in efx_evq_t *eep, 1199 __in unsigned int count) 1200{ 1201 efx_nic_t *enp = eep->ee_enp; 1202 uint32_t rptr; 1203 efx_dword_t dword; 1204 1205 rptr = count & eep->ee_mask; 1206 1207 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr); 1208 1209 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index, 1210 &dword, B_FALSE); 1211 1212 return (0); 1213} 1214 1215static void 1216siena_ev_qpost( 1217 __in efx_evq_t *eep, 1218 __in uint16_t data) 1219{ 1220 efx_nic_t *enp = eep->ee_enp; 1221 efx_qword_t ev; 1222 efx_oword_t oword; 1223 1224 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV, 1225 FSF_AZ_EV_DATA_DW0, (uint32_t)data); 1226 1227 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index, 1228 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0), 1229 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1)); 1230 1231 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); 1232} 1233 1234static __checkReturn efx_rc_t 1235siena_ev_qmoderate( 1236 __in efx_evq_t *eep, 1237 __in unsigned int us) 1238{ 1239 efx_nic_t *enp = eep->ee_enp; 1240 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1241 unsigned int locked; 1242 efx_dword_t dword; 1243 efx_rc_t rc; 1244 1245 if (us > encp->enc_evq_timer_max_us) { 1246 rc = EINVAL; 1247 goto fail1; 1248 } 1249 1250 /* If the value is zero then disable the timer */ 1251 if (us == 0) { 1252 EFX_POPULATE_DWORD_2(dword, 1253 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS, 1254 FRF_CZ_TC_TIMER_VAL, 0); 1255 } else { 1256 unsigned int ticks; 1257 1258 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0) 1259 goto fail2; 1260 1261 EFSYS_ASSERT(ticks > 0); 1262 EFX_POPULATE_DWORD_2(dword, 1263 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF, 1264 FRF_CZ_TC_TIMER_VAL, ticks - 1); 1265 } 1266 1267 locked = (eep->ee_index == 0) ? 1 : 0; 1268 1269 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, 1270 eep->ee_index, &dword, locked); 1271 1272 return (0); 1273 1274fail2: 1275 EFSYS_PROBE(fail2); 1276fail1: 1277 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1278 1279 return (rc); 1280} 1281 1282static __checkReturn efx_rc_t 1283siena_ev_qcreate( 1284 __in efx_nic_t *enp, 1285 __in unsigned int index, 1286 __in efsys_mem_t *esmp, 1287 __in size_t n, 1288 __in uint32_t id, 1289 __in uint32_t us, 1290 __in uint32_t flags, 1291 __in efx_evq_t *eep) 1292{ 1293 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1294 uint32_t size; 1295 efx_oword_t oword; 1296 efx_rc_t rc; 1297 boolean_t notify_mode; 1298 1299 _NOTE(ARGUNUSED(esmp)) 1300 1301 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); 1302 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); 1303 1304 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) { 1305 rc = EINVAL; 1306 goto fail1; 1307 } 1308 if (index >= encp->enc_evq_limit) { 1309 rc = EINVAL; 1310 goto fail2; 1311 } 1312#if EFSYS_OPT_RX_SCALE 1313 if (enp->en_intr.ei_type == EFX_INTR_LINE && 1314 index >= EFX_MAXRSS_LEGACY) { 1315 rc = EINVAL; 1316 goto fail3; 1317 } 1318#endif 1319 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS); 1320 size++) 1321 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS)) 1322 break; 1323 if (id + (1 << size) >= encp->enc_buftbl_limit) { 1324 rc = EINVAL; 1325 goto fail4; 1326 } 1327 1328 /* Set up the handler table */ 1329 eep->ee_rx = siena_ev_rx; 1330 eep->ee_tx = siena_ev_tx; 1331 eep->ee_driver = siena_ev_driver; 1332 eep->ee_global = siena_ev_global; 1333 eep->ee_drv_gen = siena_ev_drv_gen; 1334#if EFSYS_OPT_MCDI 1335 eep->ee_mcdi = siena_ev_mcdi; 1336#endif /* EFSYS_OPT_MCDI */ 1337 1338 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) != 1339 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT); 1340 1341 /* Set up the new event queue */ 1342 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1, 1343 FRF_CZ_HOST_NOTIFY_MODE, notify_mode, 1344 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); 1345 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE); 1346 1347 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size, 1348 FRF_AZ_EVQ_BUF_BASE_ID, id); 1349 1350 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE); 1351 1352 /* Set initial interrupt moderation */ 1353 siena_ev_qmoderate(eep, us); 1354 1355 return (0); 1356 1357fail4: 1358 EFSYS_PROBE(fail4); 1359#if EFSYS_OPT_RX_SCALE 1360fail3: 1361 EFSYS_PROBE(fail3); 1362#endif 1363fail2: 1364 EFSYS_PROBE(fail2); 1365fail1: 1366 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1367 1368 return (rc); 1369} 1370 1371#endif /* EFSYS_OPT_SIENA */ 1372 1373#if EFSYS_OPT_QSTATS 1374#if EFSYS_OPT_NAMES 1375/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */ 1376static const char * const __efx_ev_qstat_name[] = { 1377 "all", 1378 "rx", 1379 "rx_ok", 1380 "rx_frm_trunc", 1381 "rx_tobe_disc", 1382 "rx_pause_frm_err", 1383 "rx_buf_owner_id_err", 1384 "rx_ipv4_hdr_chksum_err", 1385 "rx_tcp_udp_chksum_err", 1386 "rx_eth_crc_err", 1387 "rx_ip_frag_err", 1388 "rx_mcast_pkt", 1389 "rx_mcast_hash_match", 1390 "rx_tcp_ipv4", 1391 "rx_tcp_ipv6", 1392 "rx_udp_ipv4", 1393 "rx_udp_ipv6", 1394 "rx_other_ipv4", 1395 "rx_other_ipv6", 1396 "rx_non_ip", 1397 "rx_batch", 1398 "tx", 1399 "tx_wq_ff_full", 1400 "tx_pkt_err", 1401 "tx_pkt_too_big", 1402 "tx_unexpected", 1403 "global", 1404 "global_mnt", 1405 "driver", 1406 "driver_srm_upd_done", 1407 "driver_tx_descq_fls_done", 1408 "driver_rx_descq_fls_done", 1409 "driver_rx_descq_fls_failed", 1410 "driver_rx_dsc_error", 1411 "driver_tx_dsc_error", 1412 "drv_gen", 1413 "mcdi_response", 1414}; 1415/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */ 1416 1417 const char * 1418efx_ev_qstat_name( 1419 __in efx_nic_t *enp, 1420 __in unsigned int id) 1421{ 1422 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1423 EFSYS_ASSERT3U(id, <, EV_NQSTATS); 1424 1425 return (__efx_ev_qstat_name[id]); 1426} 1427#endif /* EFSYS_OPT_NAMES */ 1428#endif /* EFSYS_OPT_QSTATS */ 1429 1430#if EFSYS_OPT_SIENA 1431 1432#if EFSYS_OPT_QSTATS 1433static void 1434siena_ev_qstats_update( 1435 __in efx_evq_t *eep, 1436 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 1437{ 1438 unsigned int id; 1439 1440 for (id = 0; id < EV_NQSTATS; id++) { 1441 efsys_stat_t *essp = &stat[id]; 1442 1443 EFSYS_STAT_INCR(essp, eep->ee_stat[id]); 1444 eep->ee_stat[id] = 0; 1445 } 1446} 1447#endif /* EFSYS_OPT_QSTATS */ 1448 1449static void 1450siena_ev_qdestroy( 1451 __in efx_evq_t *eep) 1452{ 1453 efx_nic_t *enp = eep->ee_enp; 1454 efx_oword_t oword; 1455 1456 /* Purge event queue */ 1457 EFX_ZERO_OWORD(oword); 1458 1459 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, 1460 eep->ee_index, &oword, B_TRUE); 1461 1462 EFX_ZERO_OWORD(oword); 1463 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE); 1464} 1465 1466static void 1467siena_ev_fini( 1468 __in efx_nic_t *enp) 1469{ 1470 _NOTE(ARGUNUSED(enp)) 1471} 1472 1473#endif /* EFSYS_OPT_SIENA */ 1474