efx.h revision 331722 
1/*-
2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/11/sys/dev/sfxge/common/efx.h 331722 2018-03-29 02:50:57Z eadler $
31 */
32
33#ifndef	_SYS_EFX_H
34#define	_SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_check.h"
38#include "efx_phy_ids.h"
39
40#ifdef	__cplusplus
41extern "C" {
42#endif
43
44#define	EFX_STATIC_ASSERT(_cond)		\
45	((void)sizeof(char[(_cond) ? 1 : -1]))
46
47#define	EFX_ARRAY_SIZE(_array)			\
48	(sizeof(_array) / sizeof((_array)[0]))
49
50#define	EFX_FIELD_OFFSET(_type, _field)		\
51	((size_t) &(((_type *)0)->_field))
52
53/* Return codes */
54
55typedef __success(return == 0) int efx_rc_t;
56
57
58/* Chip families */
59
60typedef enum efx_family_e {
61	EFX_FAMILY_INVALID,
62	EFX_FAMILY_FALCON,	/* Obsolete and not supported */
63	EFX_FAMILY_SIENA,
64	EFX_FAMILY_HUNTINGTON,
65	EFX_FAMILY_MEDFORD,
66	EFX_FAMILY_NTYPES
67} efx_family_t;
68
69extern	__checkReturn	efx_rc_t
70efx_family(
71	__in		uint16_t venid,
72	__in		uint16_t devid,
73	__out		efx_family_t *efp);
74
75
76#define	EFX_PCI_VENID_SFC			0x1924
77
78#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
79
80#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
81#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
82#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
83
84#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
85#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
86#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
87
88#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
89#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
90
91#define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
92#define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
93#define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
94
95#define	EFX_MEM_BAR	2
96
97/* Error codes */
98
99enum {
100	EFX_ERR_INVALID,
101	EFX_ERR_SRAM_OOB,
102	EFX_ERR_BUFID_DC_OOB,
103	EFX_ERR_MEM_PERR,
104	EFX_ERR_RBUF_OWN,
105	EFX_ERR_TBUF_OWN,
106	EFX_ERR_RDESQ_OWN,
107	EFX_ERR_TDESQ_OWN,
108	EFX_ERR_EVQ_OWN,
109	EFX_ERR_EVFF_OFLO,
110	EFX_ERR_ILL_ADDR,
111	EFX_ERR_SRAM_PERR,
112	EFX_ERR_NCODES
113};
114
115/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
116extern	__checkReturn		uint32_t
117efx_crc32_calculate(
118	__in			uint32_t crc_init,
119	__in_ecount(length)	uint8_t const *input,
120	__in			int length);
121
122
123/* Type prototypes */
124
125typedef struct efx_rxq_s	efx_rxq_t;
126
127/* NIC */
128
129typedef struct efx_nic_s	efx_nic_t;
130
131extern	__checkReturn	efx_rc_t
132efx_nic_create(
133	__in		efx_family_t family,
134	__in		efsys_identifier_t *esip,
135	__in		efsys_bar_t *esbp,
136	__in		efsys_lock_t *eslp,
137	__deref_out	efx_nic_t **enpp);
138
139extern	__checkReturn	efx_rc_t
140efx_nic_probe(
141	__in		efx_nic_t *enp);
142
143extern	__checkReturn	efx_rc_t
144efx_nic_init(
145	__in		efx_nic_t *enp);
146
147extern	__checkReturn	efx_rc_t
148efx_nic_reset(
149	__in		efx_nic_t *enp);
150
151#if EFSYS_OPT_DIAG
152
153extern	__checkReturn	efx_rc_t
154efx_nic_register_test(
155	__in		efx_nic_t *enp);
156
157#endif	/* EFSYS_OPT_DIAG */
158
159extern		void
160efx_nic_fini(
161	__in		efx_nic_t *enp);
162
163extern		void
164efx_nic_unprobe(
165	__in		efx_nic_t *enp);
166
167extern		void
168efx_nic_destroy(
169	__in	efx_nic_t *enp);
170
171#define	EFX_PCIE_LINK_SPEED_GEN1		1
172#define	EFX_PCIE_LINK_SPEED_GEN2		2
173#define	EFX_PCIE_LINK_SPEED_GEN3		3
174
175typedef enum efx_pcie_link_performance_e {
176	EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
177	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
178	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
179	EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
180} efx_pcie_link_performance_t;
181
182extern	__checkReturn	efx_rc_t
183efx_nic_calculate_pcie_link_bandwidth(
184	__in		uint32_t pcie_link_width,
185	__in		uint32_t pcie_link_gen,
186	__out		uint32_t *bandwidth_mbpsp);
187
188extern	__checkReturn	efx_rc_t
189efx_nic_check_pcie_link_speed(
190	__in		efx_nic_t *enp,
191	__in		uint32_t pcie_link_width,
192	__in		uint32_t pcie_link_gen,
193	__out		efx_pcie_link_performance_t *resultp);
194
195#if EFSYS_OPT_MCDI
196
197#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
198/* Huntington and Medford require MCDIv2 commands */
199#define	WITH_MCDI_V2 1
200#endif
201
202typedef struct efx_mcdi_req_s efx_mcdi_req_t;
203
204typedef enum efx_mcdi_exception_e {
205	EFX_MCDI_EXCEPTION_MC_REBOOT,
206	EFX_MCDI_EXCEPTION_MC_BADASSERT,
207} efx_mcdi_exception_t;
208
209#if EFSYS_OPT_MCDI_LOGGING
210typedef enum efx_log_msg_e {
211	EFX_LOG_INVALID,
212	EFX_LOG_MCDI_REQUEST,
213	EFX_LOG_MCDI_RESPONSE,
214} efx_log_msg_t;
215#endif /* EFSYS_OPT_MCDI_LOGGING */
216
217typedef struct efx_mcdi_transport_s {
218	void		*emt_context;
219	efsys_mem_t	*emt_dma_mem;
220	void		(*emt_execute)(void *, efx_mcdi_req_t *);
221	void		(*emt_ev_cpl)(void *);
222	void		(*emt_exception)(void *, efx_mcdi_exception_t);
223#if EFSYS_OPT_MCDI_LOGGING
224	void		(*emt_logger)(void *, efx_log_msg_t,
225					void *, size_t, void *, size_t);
226#endif /* EFSYS_OPT_MCDI_LOGGING */
227#if EFSYS_OPT_MCDI_PROXY_AUTH
228	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
229#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
230} efx_mcdi_transport_t;
231
232extern	__checkReturn	efx_rc_t
233efx_mcdi_init(
234	__in		efx_nic_t *enp,
235	__in		const efx_mcdi_transport_t *mtp);
236
237extern	__checkReturn	efx_rc_t
238efx_mcdi_reboot(
239	__in		efx_nic_t *enp);
240
241			void
242efx_mcdi_new_epoch(
243	__in		efx_nic_t *enp);
244
245extern			void
246efx_mcdi_get_timeout(
247	__in		efx_nic_t *enp,
248	__in		efx_mcdi_req_t *emrp,
249	__out		uint32_t *usec_timeoutp);
250
251extern			void
252efx_mcdi_request_start(
253	__in		efx_nic_t *enp,
254	__in		efx_mcdi_req_t *emrp,
255	__in		boolean_t ev_cpl);
256
257extern	__checkReturn	boolean_t
258efx_mcdi_request_poll(
259	__in		efx_nic_t *enp);
260
261extern	__checkReturn	boolean_t
262efx_mcdi_request_abort(
263	__in		efx_nic_t *enp);
264
265extern			void
266efx_mcdi_fini(
267	__in		efx_nic_t *enp);
268
269#endif	/* EFSYS_OPT_MCDI */
270
271/* INTR */
272
273#define	EFX_NINTR_SIENA 1024
274
275typedef enum efx_intr_type_e {
276	EFX_INTR_INVALID = 0,
277	EFX_INTR_LINE,
278	EFX_INTR_MESSAGE,
279	EFX_INTR_NTYPES
280} efx_intr_type_t;
281
282#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
283
284extern	__checkReturn	efx_rc_t
285efx_intr_init(
286	__in		efx_nic_t *enp,
287	__in		efx_intr_type_t type,
288	__in		efsys_mem_t *esmp);
289
290extern			void
291efx_intr_enable(
292	__in		efx_nic_t *enp);
293
294extern			void
295efx_intr_disable(
296	__in		efx_nic_t *enp);
297
298extern			void
299efx_intr_disable_unlocked(
300	__in		efx_nic_t *enp);
301
302#define	EFX_INTR_NEVQS	32
303
304extern	__checkReturn	efx_rc_t
305efx_intr_trigger(
306	__in		efx_nic_t *enp,
307	__in		unsigned int level);
308
309extern			void
310efx_intr_status_line(
311	__in		efx_nic_t *enp,
312	__out		boolean_t *fatalp,
313	__out		uint32_t *maskp);
314
315extern			void
316efx_intr_status_message(
317	__in		efx_nic_t *enp,
318	__in		unsigned int message,
319	__out		boolean_t *fatalp);
320
321extern			void
322efx_intr_fatal(
323	__in		efx_nic_t *enp);
324
325extern			void
326efx_intr_fini(
327	__in		efx_nic_t *enp);
328
329/* MAC */
330
331#if EFSYS_OPT_MAC_STATS
332
333/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
334typedef enum efx_mac_stat_e {
335	EFX_MAC_RX_OCTETS,
336	EFX_MAC_RX_PKTS,
337	EFX_MAC_RX_UNICST_PKTS,
338	EFX_MAC_RX_MULTICST_PKTS,
339	EFX_MAC_RX_BRDCST_PKTS,
340	EFX_MAC_RX_PAUSE_PKTS,
341	EFX_MAC_RX_LE_64_PKTS,
342	EFX_MAC_RX_65_TO_127_PKTS,
343	EFX_MAC_RX_128_TO_255_PKTS,
344	EFX_MAC_RX_256_TO_511_PKTS,
345	EFX_MAC_RX_512_TO_1023_PKTS,
346	EFX_MAC_RX_1024_TO_15XX_PKTS,
347	EFX_MAC_RX_GE_15XX_PKTS,
348	EFX_MAC_RX_ERRORS,
349	EFX_MAC_RX_FCS_ERRORS,
350	EFX_MAC_RX_DROP_EVENTS,
351	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
352	EFX_MAC_RX_SYMBOL_ERRORS,
353	EFX_MAC_RX_ALIGN_ERRORS,
354	EFX_MAC_RX_INTERNAL_ERRORS,
355	EFX_MAC_RX_JABBER_PKTS,
356	EFX_MAC_RX_LANE0_CHAR_ERR,
357	EFX_MAC_RX_LANE1_CHAR_ERR,
358	EFX_MAC_RX_LANE2_CHAR_ERR,
359	EFX_MAC_RX_LANE3_CHAR_ERR,
360	EFX_MAC_RX_LANE0_DISP_ERR,
361	EFX_MAC_RX_LANE1_DISP_ERR,
362	EFX_MAC_RX_LANE2_DISP_ERR,
363	EFX_MAC_RX_LANE3_DISP_ERR,
364	EFX_MAC_RX_MATCH_FAULT,
365	EFX_MAC_RX_NODESC_DROP_CNT,
366	EFX_MAC_TX_OCTETS,
367	EFX_MAC_TX_PKTS,
368	EFX_MAC_TX_UNICST_PKTS,
369	EFX_MAC_TX_MULTICST_PKTS,
370	EFX_MAC_TX_BRDCST_PKTS,
371	EFX_MAC_TX_PAUSE_PKTS,
372	EFX_MAC_TX_LE_64_PKTS,
373	EFX_MAC_TX_65_TO_127_PKTS,
374	EFX_MAC_TX_128_TO_255_PKTS,
375	EFX_MAC_TX_256_TO_511_PKTS,
376	EFX_MAC_TX_512_TO_1023_PKTS,
377	EFX_MAC_TX_1024_TO_15XX_PKTS,
378	EFX_MAC_TX_GE_15XX_PKTS,
379	EFX_MAC_TX_ERRORS,
380	EFX_MAC_TX_SGL_COL_PKTS,
381	EFX_MAC_TX_MULT_COL_PKTS,
382	EFX_MAC_TX_EX_COL_PKTS,
383	EFX_MAC_TX_LATE_COL_PKTS,
384	EFX_MAC_TX_DEF_PKTS,
385	EFX_MAC_TX_EX_DEF_PKTS,
386	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
387	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
388	EFX_MAC_PM_TRUNC_VFIFO_FULL,
389	EFX_MAC_PM_DISCARD_VFIFO_FULL,
390	EFX_MAC_PM_TRUNC_QBB,
391	EFX_MAC_PM_DISCARD_QBB,
392	EFX_MAC_PM_DISCARD_MAPPING,
393	EFX_MAC_RXDP_Q_DISABLED_PKTS,
394	EFX_MAC_RXDP_DI_DROPPED_PKTS,
395	EFX_MAC_RXDP_STREAMING_PKTS,
396	EFX_MAC_RXDP_HLB_FETCH,
397	EFX_MAC_RXDP_HLB_WAIT,
398	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
399	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
400	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
401	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
402	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
403	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
404	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
405	EFX_MAC_VADAPTER_RX_BAD_BYTES,
406	EFX_MAC_VADAPTER_RX_OVERFLOW,
407	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
408	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
409	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
410	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
411	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
412	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
413	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
414	EFX_MAC_VADAPTER_TX_BAD_BYTES,
415	EFX_MAC_VADAPTER_TX_OVERFLOW,
416	EFX_MAC_NSTATS
417} efx_mac_stat_t;
418
419/* END MKCONFIG GENERATED EfxHeaderMacBlock */
420
421#endif	/* EFSYS_OPT_MAC_STATS */
422
423typedef enum efx_link_mode_e {
424	EFX_LINK_UNKNOWN = 0,
425	EFX_LINK_DOWN,
426	EFX_LINK_10HDX,
427	EFX_LINK_10FDX,
428	EFX_LINK_100HDX,
429	EFX_LINK_100FDX,
430	EFX_LINK_1000HDX,
431	EFX_LINK_1000FDX,
432	EFX_LINK_10000FDX,
433	EFX_LINK_40000FDX,
434	EFX_LINK_NMODES
435} efx_link_mode_t;
436
437#define	EFX_MAC_ADDR_LEN 6
438
439#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
440
441#define	EFX_MAC_MULTICAST_LIST_MAX	256
442
443#define	EFX_MAC_SDU_MAX	9202
444
445#define	EFX_MAC_PDU_ADJUSTMENT					\
446	(/* EtherII */ 14					\
447	    + /* VLAN */ 4					\
448	    + /* CRC */ 4					\
449	    + /* bug16011 */ 16)				\
450
451#define	EFX_MAC_PDU(_sdu)					\
452	P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
453
454/*
455 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
456 * the SDU rounded up slightly.
457 */
458#define	EFX_MAC_SDU_FROM_PDU(_pdu)	((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
459
460#define	EFX_MAC_PDU_MIN	60
461#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
462
463extern	__checkReturn	efx_rc_t
464efx_mac_pdu_get(
465	__in		efx_nic_t *enp,
466	__out		size_t *pdu);
467
468extern	__checkReturn	efx_rc_t
469efx_mac_pdu_set(
470	__in		efx_nic_t *enp,
471	__in		size_t pdu);
472
473extern	__checkReturn	efx_rc_t
474efx_mac_addr_set(
475	__in		efx_nic_t *enp,
476	__in		uint8_t *addr);
477
478extern	__checkReturn			efx_rc_t
479efx_mac_filter_set(
480	__in				efx_nic_t *enp,
481	__in				boolean_t all_unicst,
482	__in				boolean_t mulcst,
483	__in				boolean_t all_mulcst,
484	__in				boolean_t brdcst);
485
486extern	__checkReturn	efx_rc_t
487efx_mac_multicast_list_set(
488	__in				efx_nic_t *enp,
489	__in_ecount(6*count)		uint8_t const *addrs,
490	__in				int count);
491
492extern	__checkReturn	efx_rc_t
493efx_mac_filter_default_rxq_set(
494	__in		efx_nic_t *enp,
495	__in		efx_rxq_t *erp,
496	__in		boolean_t using_rss);
497
498extern			void
499efx_mac_filter_default_rxq_clear(
500	__in		efx_nic_t *enp);
501
502extern	__checkReturn	efx_rc_t
503efx_mac_drain(
504	__in		efx_nic_t *enp,
505	__in		boolean_t enabled);
506
507extern	__checkReturn	efx_rc_t
508efx_mac_up(
509	__in		efx_nic_t *enp,
510	__out		boolean_t *mac_upp);
511
512#define	EFX_FCNTL_RESPOND	0x00000001
513#define	EFX_FCNTL_GENERATE	0x00000002
514
515extern	__checkReturn	efx_rc_t
516efx_mac_fcntl_set(
517	__in		efx_nic_t *enp,
518	__in		unsigned int fcntl,
519	__in		boolean_t autoneg);
520
521extern			void
522efx_mac_fcntl_get(
523	__in		efx_nic_t *enp,
524	__out		unsigned int *fcntl_wantedp,
525	__out		unsigned int *fcntl_linkp);
526
527
528#if EFSYS_OPT_MAC_STATS
529
530#if EFSYS_OPT_NAMES
531
532extern	__checkReturn			const char *
533efx_mac_stat_name(
534	__in				efx_nic_t *enp,
535	__in				unsigned int id);
536
537#endif	/* EFSYS_OPT_NAMES */
538
539#define	EFX_MAC_STATS_MASK_BITS_PER_PAGE	(8 * sizeof (uint32_t))
540
541#define	EFX_MAC_STATS_MASK_NPAGES	\
542	(P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
543	    EFX_MAC_STATS_MASK_BITS_PER_PAGE)
544
545/*
546 * Get mask of MAC statistics supported by the hardware.
547 *
548 * If mask_size is insufficient to return the mask, EINVAL error is
549 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
550 * (which is sizeof (uint32_t)) is sufficient.
551 */
552extern	__checkReturn			efx_rc_t
553efx_mac_stats_get_mask(
554	__in				efx_nic_t *enp,
555	__out_bcount(mask_size)		uint32_t *maskp,
556	__in				size_t mask_size);
557
558#define	EFX_MAC_STAT_SUPPORTED(_mask, _stat)	\
559	((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] &	\
560	 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
561
562#define	EFX_MAC_STATS_SIZE 0x400
563
564/*
565 * Upload mac statistics supported by the hardware into the given buffer.
566 *
567 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
568 * and page aligned.
569 *
570 * The hardware will only DMA statistics that it understands (of course).
571 * Drivers should not make any assumptions about which statistics are
572 * supported, especially when the statistics are generated by firmware.
573 *
574 * Thus, drivers should zero this buffer before use, so that not-understood
575 * statistics read back as zero.
576 */
577extern	__checkReturn			efx_rc_t
578efx_mac_stats_upload(
579	__in				efx_nic_t *enp,
580	__in				efsys_mem_t *esmp);
581
582extern	__checkReturn			efx_rc_t
583efx_mac_stats_periodic(
584	__in				efx_nic_t *enp,
585	__in				efsys_mem_t *esmp,
586	__in				uint16_t period_ms,
587	__in				boolean_t events);
588
589extern	__checkReturn			efx_rc_t
590efx_mac_stats_update(
591	__in				efx_nic_t *enp,
592	__in				efsys_mem_t *esmp,
593	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
594	__inout_opt			uint32_t *generationp);
595
596#endif	/* EFSYS_OPT_MAC_STATS */
597
598/* MON */
599
600typedef enum efx_mon_type_e {
601	EFX_MON_INVALID = 0,
602	EFX_MON_SFC90X0,
603	EFX_MON_SFC91X0,
604	EFX_MON_SFC92X0,
605	EFX_MON_NTYPES
606} efx_mon_type_t;
607
608#if EFSYS_OPT_NAMES
609
610extern		const char *
611efx_mon_name(
612	__in	efx_nic_t *enp);
613
614#endif	/* EFSYS_OPT_NAMES */
615
616extern	__checkReturn	efx_rc_t
617efx_mon_init(
618	__in		efx_nic_t *enp);
619
620#if EFSYS_OPT_MON_STATS
621
622#define	EFX_MON_STATS_PAGE_SIZE 0x100
623#define	EFX_MON_MASK_ELEMENT_SIZE 32
624
625/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
626typedef enum efx_mon_stat_e {
627	EFX_MON_STAT_2_5V,
628	EFX_MON_STAT_VCCP1,
629	EFX_MON_STAT_VCC,
630	EFX_MON_STAT_5V,
631	EFX_MON_STAT_12V,
632	EFX_MON_STAT_VCCP2,
633	EFX_MON_STAT_EXT_TEMP,
634	EFX_MON_STAT_INT_TEMP,
635	EFX_MON_STAT_AIN1,
636	EFX_MON_STAT_AIN2,
637	EFX_MON_STAT_INT_COOLING,
638	EFX_MON_STAT_EXT_COOLING,
639	EFX_MON_STAT_1V,
640	EFX_MON_STAT_1_2V,
641	EFX_MON_STAT_1_8V,
642	EFX_MON_STAT_3_3V,
643	EFX_MON_STAT_1_2VA,
644	EFX_MON_STAT_VREF,
645	EFX_MON_STAT_VAOE,
646	EFX_MON_STAT_AOE_TEMP,
647	EFX_MON_STAT_PSU_AOE_TEMP,
648	EFX_MON_STAT_PSU_TEMP,
649	EFX_MON_STAT_FAN0,
650	EFX_MON_STAT_FAN1,
651	EFX_MON_STAT_FAN2,
652	EFX_MON_STAT_FAN3,
653	EFX_MON_STAT_FAN4,
654	EFX_MON_STAT_VAOE_IN,
655	EFX_MON_STAT_IAOE,
656	EFX_MON_STAT_IAOE_IN,
657	EFX_MON_STAT_NIC_POWER,
658	EFX_MON_STAT_0_9V,
659	EFX_MON_STAT_I0_9V,
660	EFX_MON_STAT_I1_2V,
661	EFX_MON_STAT_0_9V_ADC,
662	EFX_MON_STAT_INT_TEMP2,
663	EFX_MON_STAT_VREG_TEMP,
664	EFX_MON_STAT_VREG_0_9V_TEMP,
665	EFX_MON_STAT_VREG_1_2V_TEMP,
666	EFX_MON_STAT_INT_VPTAT,
667	EFX_MON_STAT_INT_ADC_TEMP,
668	EFX_MON_STAT_EXT_VPTAT,
669	EFX_MON_STAT_EXT_ADC_TEMP,
670	EFX_MON_STAT_AMBIENT_TEMP,
671	EFX_MON_STAT_AIRFLOW,
672	EFX_MON_STAT_VDD08D_VSS08D_CSR,
673	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
674	EFX_MON_STAT_HOTPOINT_TEMP,
675	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
676	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
677	EFX_MON_STAT_MUM_VCC,
678	EFX_MON_STAT_0V9_A,
679	EFX_MON_STAT_I0V9_A,
680	EFX_MON_STAT_0V9_A_TEMP,
681	EFX_MON_STAT_0V9_B,
682	EFX_MON_STAT_I0V9_B,
683	EFX_MON_STAT_0V9_B_TEMP,
684	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
685	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
686	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
687	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
688	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
689	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
690	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
691	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
692	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
693	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
694	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
695	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
696	EFX_MON_STAT_SODIMM_VOUT,
697	EFX_MON_STAT_SODIMM_0_TEMP,
698	EFX_MON_STAT_SODIMM_1_TEMP,
699	EFX_MON_STAT_PHY0_VCC,
700	EFX_MON_STAT_PHY1_VCC,
701	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
702	EFX_MON_STAT_BOARD_FRONT_TEMP,
703	EFX_MON_STAT_BOARD_BACK_TEMP,
704	EFX_MON_NSTATS
705} efx_mon_stat_t;
706
707/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
708
709typedef enum efx_mon_stat_state_e {
710	EFX_MON_STAT_STATE_OK = 0,
711	EFX_MON_STAT_STATE_WARNING = 1,
712	EFX_MON_STAT_STATE_FATAL = 2,
713	EFX_MON_STAT_STATE_BROKEN = 3,
714	EFX_MON_STAT_STATE_NO_READING = 4,
715} efx_mon_stat_state_t;
716
717typedef struct efx_mon_stat_value_s {
718	uint16_t	emsv_value;
719	uint16_t	emsv_state;
720} efx_mon_stat_value_t;
721
722#if EFSYS_OPT_NAMES
723
724extern					const char *
725efx_mon_stat_name(
726	__in				efx_nic_t *enp,
727	__in				efx_mon_stat_t id);
728
729#endif	/* EFSYS_OPT_NAMES */
730
731extern	__checkReturn			efx_rc_t
732efx_mon_stats_update(
733	__in				efx_nic_t *enp,
734	__in				efsys_mem_t *esmp,
735	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
736
737#endif	/* EFSYS_OPT_MON_STATS */
738
739extern		void
740efx_mon_fini(
741	__in	efx_nic_t *enp);
742
743/* PHY */
744
745extern	__checkReturn	efx_rc_t
746efx_phy_verify(
747	__in		efx_nic_t *enp);
748
749#if EFSYS_OPT_PHY_LED_CONTROL
750
751typedef enum efx_phy_led_mode_e {
752	EFX_PHY_LED_DEFAULT = 0,
753	EFX_PHY_LED_OFF,
754	EFX_PHY_LED_ON,
755	EFX_PHY_LED_FLASH,
756	EFX_PHY_LED_NMODES
757} efx_phy_led_mode_t;
758
759extern	__checkReturn	efx_rc_t
760efx_phy_led_set(
761	__in	efx_nic_t *enp,
762	__in	efx_phy_led_mode_t mode);
763
764#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
765
766extern	__checkReturn	efx_rc_t
767efx_port_init(
768	__in		efx_nic_t *enp);
769
770#if EFSYS_OPT_LOOPBACK
771
772typedef enum efx_loopback_type_e {
773	EFX_LOOPBACK_OFF = 0,
774	EFX_LOOPBACK_DATA = 1,
775	EFX_LOOPBACK_GMAC = 2,
776	EFX_LOOPBACK_XGMII = 3,
777	EFX_LOOPBACK_XGXS = 4,
778	EFX_LOOPBACK_XAUI = 5,
779	EFX_LOOPBACK_GMII = 6,
780	EFX_LOOPBACK_SGMII = 7,
781	EFX_LOOPBACK_XGBR = 8,
782	EFX_LOOPBACK_XFI = 9,
783	EFX_LOOPBACK_XAUI_FAR = 10,
784	EFX_LOOPBACK_GMII_FAR = 11,
785	EFX_LOOPBACK_SGMII_FAR = 12,
786	EFX_LOOPBACK_XFI_FAR = 13,
787	EFX_LOOPBACK_GPHY = 14,
788	EFX_LOOPBACK_PHY_XS = 15,
789	EFX_LOOPBACK_PCS = 16,
790	EFX_LOOPBACK_PMA_PMD = 17,
791	EFX_LOOPBACK_XPORT = 18,
792	EFX_LOOPBACK_XGMII_WS = 19,
793	EFX_LOOPBACK_XAUI_WS = 20,
794	EFX_LOOPBACK_XAUI_WS_FAR = 21,
795	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
796	EFX_LOOPBACK_GMII_WS = 23,
797	EFX_LOOPBACK_XFI_WS = 24,
798	EFX_LOOPBACK_XFI_WS_FAR = 25,
799	EFX_LOOPBACK_PHYXS_WS = 26,
800	EFX_LOOPBACK_PMA_INT = 27,
801	EFX_LOOPBACK_SD_NEAR = 28,
802	EFX_LOOPBACK_SD_FAR = 29,
803	EFX_LOOPBACK_PMA_INT_WS = 30,
804	EFX_LOOPBACK_SD_FEP2_WS = 31,
805	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
806	EFX_LOOPBACK_SD_FEP_WS = 33,
807	EFX_LOOPBACK_SD_FES_WS = 34,
808	EFX_LOOPBACK_NTYPES
809} efx_loopback_type_t;
810
811typedef enum efx_loopback_kind_e {
812	EFX_LOOPBACK_KIND_OFF = 0,
813	EFX_LOOPBACK_KIND_ALL,
814	EFX_LOOPBACK_KIND_MAC,
815	EFX_LOOPBACK_KIND_PHY,
816	EFX_LOOPBACK_NKINDS
817} efx_loopback_kind_t;
818
819extern			void
820efx_loopback_mask(
821	__in	efx_loopback_kind_t loopback_kind,
822	__out	efx_qword_t *maskp);
823
824extern	__checkReturn	efx_rc_t
825efx_port_loopback_set(
826	__in	efx_nic_t *enp,
827	__in	efx_link_mode_t link_mode,
828	__in	efx_loopback_type_t type);
829
830#if EFSYS_OPT_NAMES
831
832extern	__checkReturn	const char *
833efx_loopback_type_name(
834	__in		efx_nic_t *enp,
835	__in		efx_loopback_type_t type);
836
837#endif	/* EFSYS_OPT_NAMES */
838
839#endif	/* EFSYS_OPT_LOOPBACK */
840
841extern	__checkReturn	efx_rc_t
842efx_port_poll(
843	__in		efx_nic_t *enp,
844	__out_opt	efx_link_mode_t	*link_modep);
845
846extern		void
847efx_port_fini(
848	__in	efx_nic_t *enp);
849
850typedef enum efx_phy_cap_type_e {
851	EFX_PHY_CAP_INVALID = 0,
852	EFX_PHY_CAP_10HDX,
853	EFX_PHY_CAP_10FDX,
854	EFX_PHY_CAP_100HDX,
855	EFX_PHY_CAP_100FDX,
856	EFX_PHY_CAP_1000HDX,
857	EFX_PHY_CAP_1000FDX,
858	EFX_PHY_CAP_10000FDX,
859	EFX_PHY_CAP_PAUSE,
860	EFX_PHY_CAP_ASYM,
861	EFX_PHY_CAP_AN,
862	EFX_PHY_CAP_40000FDX,
863	EFX_PHY_CAP_NTYPES
864} efx_phy_cap_type_t;
865
866
867#define	EFX_PHY_CAP_CURRENT	0x00000000
868#define	EFX_PHY_CAP_DEFAULT	0x00000001
869#define	EFX_PHY_CAP_PERM	0x00000002
870
871extern		void
872efx_phy_adv_cap_get(
873	__in		efx_nic_t *enp,
874	__in		uint32_t flag,
875	__out		uint32_t *maskp);
876
877extern	__checkReturn	efx_rc_t
878efx_phy_adv_cap_set(
879	__in		efx_nic_t *enp,
880	__in		uint32_t mask);
881
882extern			void
883efx_phy_lp_cap_get(
884	__in		efx_nic_t *enp,
885	__out		uint32_t *maskp);
886
887extern	__checkReturn	efx_rc_t
888efx_phy_oui_get(
889	__in		efx_nic_t *enp,
890	__out		uint32_t *ouip);
891
892typedef enum efx_phy_media_type_e {
893	EFX_PHY_MEDIA_INVALID = 0,
894	EFX_PHY_MEDIA_XAUI,
895	EFX_PHY_MEDIA_CX4,
896	EFX_PHY_MEDIA_KX4,
897	EFX_PHY_MEDIA_XFP,
898	EFX_PHY_MEDIA_SFP_PLUS,
899	EFX_PHY_MEDIA_BASE_T,
900	EFX_PHY_MEDIA_QSFP_PLUS,
901	EFX_PHY_MEDIA_NTYPES
902} efx_phy_media_type_t;
903
904/* Get the type of medium currently used.  If the board has ports for
905 * modules, a module is present, and we recognise the media type of
906 * the module, then this will be the media type of the module.
907 * Otherwise it will be the media type of the port.
908 */
909extern			void
910efx_phy_media_type_get(
911	__in		efx_nic_t *enp,
912	__out		efx_phy_media_type_t *typep);
913
914extern					efx_rc_t
915efx_phy_module_get_info(
916	__in				efx_nic_t *enp,
917	__in				uint8_t dev_addr,
918	__in				uint8_t offset,
919	__in				uint8_t len,
920	__out_bcount(len)		uint8_t *data);
921
922#if EFSYS_OPT_PHY_STATS
923
924/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
925typedef enum efx_phy_stat_e {
926	EFX_PHY_STAT_OUI,
927	EFX_PHY_STAT_PMA_PMD_LINK_UP,
928	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
929	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
930	EFX_PHY_STAT_PMA_PMD_REV_A,
931	EFX_PHY_STAT_PMA_PMD_REV_B,
932	EFX_PHY_STAT_PMA_PMD_REV_C,
933	EFX_PHY_STAT_PMA_PMD_REV_D,
934	EFX_PHY_STAT_PCS_LINK_UP,
935	EFX_PHY_STAT_PCS_RX_FAULT,
936	EFX_PHY_STAT_PCS_TX_FAULT,
937	EFX_PHY_STAT_PCS_BER,
938	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
939	EFX_PHY_STAT_PHY_XS_LINK_UP,
940	EFX_PHY_STAT_PHY_XS_RX_FAULT,
941	EFX_PHY_STAT_PHY_XS_TX_FAULT,
942	EFX_PHY_STAT_PHY_XS_ALIGN,
943	EFX_PHY_STAT_PHY_XS_SYNC_A,
944	EFX_PHY_STAT_PHY_XS_SYNC_B,
945	EFX_PHY_STAT_PHY_XS_SYNC_C,
946	EFX_PHY_STAT_PHY_XS_SYNC_D,
947	EFX_PHY_STAT_AN_LINK_UP,
948	EFX_PHY_STAT_AN_MASTER,
949	EFX_PHY_STAT_AN_LOCAL_RX_OK,
950	EFX_PHY_STAT_AN_REMOTE_RX_OK,
951	EFX_PHY_STAT_CL22EXT_LINK_UP,
952	EFX_PHY_STAT_SNR_A,
953	EFX_PHY_STAT_SNR_B,
954	EFX_PHY_STAT_SNR_C,
955	EFX_PHY_STAT_SNR_D,
956	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
957	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
958	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
959	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
960	EFX_PHY_STAT_AN_COMPLETE,
961	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
962	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
963	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
964	EFX_PHY_STAT_PCS_FW_VERSION_0,
965	EFX_PHY_STAT_PCS_FW_VERSION_1,
966	EFX_PHY_STAT_PCS_FW_VERSION_2,
967	EFX_PHY_STAT_PCS_FW_VERSION_3,
968	EFX_PHY_STAT_PCS_FW_BUILD_YY,
969	EFX_PHY_STAT_PCS_FW_BUILD_MM,
970	EFX_PHY_STAT_PCS_FW_BUILD_DD,
971	EFX_PHY_STAT_PCS_OP_MODE,
972	EFX_PHY_NSTATS
973} efx_phy_stat_t;
974
975/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
976
977#if EFSYS_OPT_NAMES
978
979extern					const char *
980efx_phy_stat_name(
981	__in				efx_nic_t *enp,
982	__in				efx_phy_stat_t stat);
983
984#endif	/* EFSYS_OPT_NAMES */
985
986#define	EFX_PHY_STATS_SIZE 0x100
987
988extern	__checkReturn			efx_rc_t
989efx_phy_stats_update(
990	__in				efx_nic_t *enp,
991	__in				efsys_mem_t *esmp,
992	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
993
994#endif	/* EFSYS_OPT_PHY_STATS */
995
996
997#if EFSYS_OPT_BIST
998
999typedef enum efx_bist_type_e {
1000	EFX_BIST_TYPE_UNKNOWN,
1001	EFX_BIST_TYPE_PHY_NORMAL,
1002	EFX_BIST_TYPE_PHY_CABLE_SHORT,
1003	EFX_BIST_TYPE_PHY_CABLE_LONG,
1004	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
1005	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
1006	EFX_BIST_TYPE_REG,	/* Test the register memories */
1007	EFX_BIST_TYPE_NTYPES,
1008} efx_bist_type_t;
1009
1010typedef enum efx_bist_result_e {
1011	EFX_BIST_RESULT_UNKNOWN,
1012	EFX_BIST_RESULT_RUNNING,
1013	EFX_BIST_RESULT_PASSED,
1014	EFX_BIST_RESULT_FAILED,
1015} efx_bist_result_t;
1016
1017typedef enum efx_phy_cable_status_e {
1018	EFX_PHY_CABLE_STATUS_OK,
1019	EFX_PHY_CABLE_STATUS_INVALID,
1020	EFX_PHY_CABLE_STATUS_OPEN,
1021	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1022	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1023	EFX_PHY_CABLE_STATUS_BUSY,
1024} efx_phy_cable_status_t;
1025
1026typedef enum efx_bist_value_e {
1027	EFX_BIST_PHY_CABLE_LENGTH_A,
1028	EFX_BIST_PHY_CABLE_LENGTH_B,
1029	EFX_BIST_PHY_CABLE_LENGTH_C,
1030	EFX_BIST_PHY_CABLE_LENGTH_D,
1031	EFX_BIST_PHY_CABLE_STATUS_A,
1032	EFX_BIST_PHY_CABLE_STATUS_B,
1033	EFX_BIST_PHY_CABLE_STATUS_C,
1034	EFX_BIST_PHY_CABLE_STATUS_D,
1035	EFX_BIST_FAULT_CODE,
1036	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1037	 * response. */
1038	EFX_BIST_MEM_TEST,
1039	EFX_BIST_MEM_ADDR,
1040	EFX_BIST_MEM_BUS,
1041	EFX_BIST_MEM_EXPECT,
1042	EFX_BIST_MEM_ACTUAL,
1043	EFX_BIST_MEM_ECC,
1044	EFX_BIST_MEM_ECC_PARITY,
1045	EFX_BIST_MEM_ECC_FATAL,
1046	EFX_BIST_NVALUES,
1047} efx_bist_value_t;
1048
1049extern	__checkReturn		efx_rc_t
1050efx_bist_enable_offline(
1051	__in			efx_nic_t *enp);
1052
1053extern	__checkReturn		efx_rc_t
1054efx_bist_start(
1055	__in			efx_nic_t *enp,
1056	__in			efx_bist_type_t type);
1057
1058extern	__checkReturn		efx_rc_t
1059efx_bist_poll(
1060	__in			efx_nic_t *enp,
1061	__in			efx_bist_type_t type,
1062	__out			efx_bist_result_t *resultp,
1063	__out_opt		uint32_t *value_maskp,
1064	__out_ecount_opt(count)	unsigned long *valuesp,
1065	__in			size_t count);
1066
1067extern				void
1068efx_bist_stop(
1069	__in			efx_nic_t *enp,
1070	__in			efx_bist_type_t type);
1071
1072#endif	/* EFSYS_OPT_BIST */
1073
1074#define	EFX_FEATURE_IPV6		0x00000001
1075#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1076#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1077#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1078#define	EFX_FEATURE_MCDI		0x00000020
1079#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1080#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1081#define	EFX_FEATURE_TURBO		0x00000100
1082#define	EFX_FEATURE_MCDI_DMA		0x00000200
1083#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1084#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1085#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1086#define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1087
1088typedef struct efx_nic_cfg_s {
1089	uint32_t		enc_board_type;
1090	uint32_t		enc_phy_type;
1091#if EFSYS_OPT_NAMES
1092	char			enc_phy_name[21];
1093#endif
1094	char			enc_phy_revision[21];
1095	efx_mon_type_t		enc_mon_type;
1096#if EFSYS_OPT_MON_STATS
1097	uint32_t		enc_mon_stat_dma_buf_size;
1098	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1099#endif
1100	unsigned int		enc_features;
1101	uint8_t			enc_mac_addr[6];
1102	uint8_t			enc_port;	/* PHY port number */
1103	uint32_t		enc_intr_vec_base;
1104	uint32_t		enc_intr_limit;
1105	uint32_t		enc_evq_limit;
1106	uint32_t		enc_txq_limit;
1107	uint32_t		enc_rxq_limit;
1108	uint32_t		enc_buftbl_limit;
1109	uint32_t		enc_piobuf_limit;
1110	uint32_t		enc_piobuf_size;
1111	uint32_t		enc_piobuf_min_alloc_size;
1112	uint32_t		enc_evq_timer_quantum_ns;
1113	uint32_t		enc_evq_timer_max_us;
1114	uint32_t		enc_clk_mult;
1115	uint32_t		enc_rx_prefix_size;
1116	uint32_t		enc_rx_buf_align_start;
1117	uint32_t		enc_rx_buf_align_end;
1118#if EFSYS_OPT_LOOPBACK
1119	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1120#endif	/* EFSYS_OPT_LOOPBACK */
1121#if EFSYS_OPT_PHY_FLAGS
1122	uint32_t		enc_phy_flags_mask;
1123#endif	/* EFSYS_OPT_PHY_FLAGS */
1124#if EFSYS_OPT_PHY_LED_CONTROL
1125	uint32_t		enc_led_mask;
1126#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1127#if EFSYS_OPT_PHY_STATS
1128	uint64_t		enc_phy_stat_mask;
1129#endif	/* EFSYS_OPT_PHY_STATS */
1130#if EFSYS_OPT_MCDI
1131	uint8_t			enc_mcdi_mdio_channel;
1132#if EFSYS_OPT_PHY_STATS
1133	uint32_t		enc_mcdi_phy_stat_mask;
1134#endif	/* EFSYS_OPT_PHY_STATS */
1135#if EFSYS_OPT_MON_STATS
1136	uint32_t		*enc_mcdi_sensor_maskp;
1137	uint32_t		enc_mcdi_sensor_mask_size;
1138#endif	/* EFSYS_OPT_MON_STATS */
1139#endif	/* EFSYS_OPT_MCDI */
1140#if EFSYS_OPT_BIST
1141	uint32_t		enc_bist_mask;
1142#endif	/* EFSYS_OPT_BIST */
1143#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1144	uint32_t		enc_pf;
1145	uint32_t		enc_vf;
1146	uint32_t		enc_privilege_mask;
1147#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1148	boolean_t		enc_bug26807_workaround;
1149	boolean_t		enc_bug35388_workaround;
1150	boolean_t		enc_bug41750_workaround;
1151	boolean_t		enc_bug61265_workaround;
1152	boolean_t		enc_rx_batching_enabled;
1153	/* Maximum number of descriptors completed in an rx event. */
1154	uint32_t		enc_rx_batch_max;
1155	/* Number of rx descriptors the hardware requires for a push. */
1156	uint32_t		enc_rx_push_align;
1157	/* Maximum amount of data in DMA descriptor */
1158	uint32_t		enc_tx_dma_desc_size_max;
1159	/*
1160	 * Boundary which DMA descriptor data must not cross or 0 if no
1161	 * limitation.
1162	 */
1163	uint32_t		enc_tx_dma_desc_boundary;
1164	/*
1165	 * Maximum number of bytes into the packet the TCP header can start for
1166	 * the hardware to apply TSO packet edits.
1167	 */
1168	uint32_t		enc_tx_tso_tcp_header_offset_limit;
1169	boolean_t		enc_fw_assisted_tso_enabled;
1170	boolean_t		enc_fw_assisted_tso_v2_enabled;
1171	/* Number of TSO contexts on the NIC (FATSOv2) */
1172	uint32_t		enc_fw_assisted_tso_v2_n_contexts;
1173	boolean_t		enc_hw_tx_insert_vlan_enabled;
1174	/* Number of PFs on the NIC */
1175	uint32_t		enc_hw_pf_count;
1176	/* Datapath firmware vadapter/vport/vswitch support */
1177	boolean_t		enc_datapath_cap_evb;
1178	boolean_t		enc_rx_disable_scatter_supported;
1179	boolean_t		enc_allow_set_mac_with_installed_filters;
1180	boolean_t		enc_enhanced_set_mac_supported;
1181	boolean_t		enc_init_evq_v2_supported;
1182	boolean_t		enc_pm_and_rxdp_counters;
1183	boolean_t		enc_mac_stats_40g_tx_size_bins;
1184	/* External port identifier */
1185	uint8_t			enc_external_port;
1186	uint32_t		enc_mcdi_max_payload_length;
1187	/* VPD may be per-PF or global */
1188	boolean_t		enc_vpd_is_global;
1189	/* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1190	uint32_t		enc_required_pcie_bandwidth_mbps;
1191	uint32_t		enc_max_pcie_link_gen;
1192	/* Firmware verifies integrity of NVRAM updates */
1193	uint32_t		enc_fw_verified_nvram_update_required;
1194} efx_nic_cfg_t;
1195
1196#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1197#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1198
1199#define	EFX_PCI_FUNCTION(_encp)	\
1200	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1201
1202#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1203
1204extern			const efx_nic_cfg_t *
1205efx_nic_cfg_get(
1206	__in		efx_nic_t *enp);
1207
1208/* Driver resource limits (minimum required/maximum usable). */
1209typedef struct efx_drv_limits_s {
1210	uint32_t	edl_min_evq_count;
1211	uint32_t	edl_max_evq_count;
1212
1213	uint32_t	edl_min_rxq_count;
1214	uint32_t	edl_max_rxq_count;
1215
1216	uint32_t	edl_min_txq_count;
1217	uint32_t	edl_max_txq_count;
1218
1219	/* PIO blocks (sub-allocated from piobuf) */
1220	uint32_t	edl_min_pio_alloc_size;
1221	uint32_t	edl_max_pio_alloc_count;
1222} efx_drv_limits_t;
1223
1224extern	__checkReturn	efx_rc_t
1225efx_nic_set_drv_limits(
1226	__inout		efx_nic_t *enp,
1227	__in		efx_drv_limits_t *edlp);
1228
1229typedef enum efx_nic_region_e {
1230	EFX_REGION_VI,			/* Memory BAR UC mapping */
1231	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1232} efx_nic_region_t;
1233
1234extern	__checkReturn	efx_rc_t
1235efx_nic_get_bar_region(
1236	__in		efx_nic_t *enp,
1237	__in		efx_nic_region_t region,
1238	__out		uint32_t *offsetp,
1239	__out		size_t *sizep);
1240
1241extern	__checkReturn	efx_rc_t
1242efx_nic_get_vi_pool(
1243	__in		efx_nic_t *enp,
1244	__out		uint32_t *evq_countp,
1245	__out		uint32_t *rxq_countp,
1246	__out		uint32_t *txq_countp);
1247
1248
1249#if EFSYS_OPT_VPD
1250
1251typedef enum efx_vpd_tag_e {
1252	EFX_VPD_ID = 0x02,
1253	EFX_VPD_END = 0x0f,
1254	EFX_VPD_RO = 0x10,
1255	EFX_VPD_RW = 0x11,
1256} efx_vpd_tag_t;
1257
1258typedef uint16_t efx_vpd_keyword_t;
1259
1260typedef struct efx_vpd_value_s {
1261	efx_vpd_tag_t		evv_tag;
1262	efx_vpd_keyword_t	evv_keyword;
1263	uint8_t			evv_length;
1264	uint8_t			evv_value[0x100];
1265} efx_vpd_value_t;
1266
1267
1268#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1269
1270extern	__checkReturn		efx_rc_t
1271efx_vpd_init(
1272	__in			efx_nic_t *enp);
1273
1274extern	__checkReturn		efx_rc_t
1275efx_vpd_size(
1276	__in			efx_nic_t *enp,
1277	__out			size_t *sizep);
1278
1279extern	__checkReturn		efx_rc_t
1280efx_vpd_read(
1281	__in			efx_nic_t *enp,
1282	__out_bcount(size)	caddr_t data,
1283	__in			size_t size);
1284
1285extern	__checkReturn		efx_rc_t
1286efx_vpd_verify(
1287	__in			efx_nic_t *enp,
1288	__in_bcount(size)	caddr_t data,
1289	__in			size_t size);
1290
1291extern	__checkReturn		efx_rc_t
1292efx_vpd_reinit(
1293	__in			efx_nic_t *enp,
1294	__in_bcount(size)	caddr_t data,
1295	__in			size_t size);
1296
1297extern	__checkReturn		efx_rc_t
1298efx_vpd_get(
1299	__in			efx_nic_t *enp,
1300	__in_bcount(size)	caddr_t data,
1301	__in			size_t size,
1302	__inout			efx_vpd_value_t *evvp);
1303
1304extern	__checkReturn		efx_rc_t
1305efx_vpd_set(
1306	__in			efx_nic_t *enp,
1307	__inout_bcount(size)	caddr_t data,
1308	__in			size_t size,
1309	__in			efx_vpd_value_t *evvp);
1310
1311extern	__checkReturn		efx_rc_t
1312efx_vpd_next(
1313	__in			efx_nic_t *enp,
1314	__inout_bcount(size)	caddr_t data,
1315	__in			size_t size,
1316	__out			efx_vpd_value_t *evvp,
1317	__inout			unsigned int *contp);
1318
1319extern	__checkReturn		efx_rc_t
1320efx_vpd_write(
1321	__in			efx_nic_t *enp,
1322	__in_bcount(size)	caddr_t data,
1323	__in			size_t size);
1324
1325extern				void
1326efx_vpd_fini(
1327	__in			efx_nic_t *enp);
1328
1329#endif	/* EFSYS_OPT_VPD */
1330
1331/* NVRAM */
1332
1333#if EFSYS_OPT_NVRAM
1334
1335typedef enum efx_nvram_type_e {
1336	EFX_NVRAM_INVALID = 0,
1337	EFX_NVRAM_BOOTROM,
1338	EFX_NVRAM_BOOTROM_CFG,
1339	EFX_NVRAM_MC_FIRMWARE,
1340	EFX_NVRAM_MC_GOLDEN,
1341	EFX_NVRAM_PHY,
1342	EFX_NVRAM_NULLPHY,
1343	EFX_NVRAM_FPGA,
1344	EFX_NVRAM_FCFW,
1345	EFX_NVRAM_CPLD,
1346	EFX_NVRAM_FPGA_BACKUP,
1347	EFX_NVRAM_DYNAMIC_CFG,
1348	EFX_NVRAM_LICENSE,
1349	EFX_NVRAM_UEFIROM,
1350	EFX_NVRAM_NTYPES,
1351} efx_nvram_type_t;
1352
1353extern	__checkReturn		efx_rc_t
1354efx_nvram_init(
1355	__in			efx_nic_t *enp);
1356
1357#if EFSYS_OPT_DIAG
1358
1359extern	__checkReturn		efx_rc_t
1360efx_nvram_test(
1361	__in			efx_nic_t *enp);
1362
1363#endif	/* EFSYS_OPT_DIAG */
1364
1365extern	__checkReturn		efx_rc_t
1366efx_nvram_size(
1367	__in			efx_nic_t *enp,
1368	__in			efx_nvram_type_t type,
1369	__out			size_t *sizep);
1370
1371extern	__checkReturn		efx_rc_t
1372efx_nvram_rw_start(
1373	__in			efx_nic_t *enp,
1374	__in			efx_nvram_type_t type,
1375	__out_opt		size_t *pref_chunkp);
1376
1377extern	__checkReturn		efx_rc_t
1378efx_nvram_rw_finish(
1379	__in			efx_nic_t *enp,
1380	__in			efx_nvram_type_t type);
1381
1382extern	__checkReturn		efx_rc_t
1383efx_nvram_get_version(
1384	__in			efx_nic_t *enp,
1385	__in			efx_nvram_type_t type,
1386	__out			uint32_t *subtypep,
1387	__out_ecount(4)		uint16_t version[4]);
1388
1389extern	__checkReturn		efx_rc_t
1390efx_nvram_read_chunk(
1391	__in			efx_nic_t *enp,
1392	__in			efx_nvram_type_t type,
1393	__in			unsigned int offset,
1394	__out_bcount(size)	caddr_t data,
1395	__in			size_t size);
1396
1397extern	__checkReturn		efx_rc_t
1398efx_nvram_set_version(
1399	__in			efx_nic_t *enp,
1400	__in			efx_nvram_type_t type,
1401	__in_ecount(4)		uint16_t version[4]);
1402
1403extern	__checkReturn		efx_rc_t
1404efx_nvram_validate(
1405	__in			efx_nic_t *enp,
1406	__in			efx_nvram_type_t type,
1407	__in_bcount(partn_size)	caddr_t partn_data,
1408	__in			size_t partn_size);
1409
1410extern	 __checkReturn		efx_rc_t
1411efx_nvram_erase(
1412	__in			efx_nic_t *enp,
1413	__in			efx_nvram_type_t type);
1414
1415extern	__checkReturn		efx_rc_t
1416efx_nvram_write_chunk(
1417	__in			efx_nic_t *enp,
1418	__in			efx_nvram_type_t type,
1419	__in			unsigned int offset,
1420	__in_bcount(size)	caddr_t data,
1421	__in			size_t size);
1422
1423extern				void
1424efx_nvram_fini(
1425	__in			efx_nic_t *enp);
1426
1427#endif	/* EFSYS_OPT_NVRAM */
1428
1429#if EFSYS_OPT_BOOTCFG
1430
1431/* Report size and offset of bootcfg sector in NVRAM partition. */
1432extern	__checkReturn		efx_rc_t
1433efx_bootcfg_sector_info(
1434	__in			efx_nic_t *enp,
1435	__in			uint32_t pf,
1436	__out_opt		uint32_t *sector_countp,
1437	__out			size_t *offsetp,
1438	__out			size_t *max_sizep);
1439
1440/*
1441 * Copy bootcfg sector data to a target buffer which may differ in size.
1442 * Optionally corrects format errors in source buffer.
1443 */
1444extern				efx_rc_t
1445efx_bootcfg_copy_sector(
1446	__in			efx_nic_t *enp,
1447	__inout_bcount(sector_length)
1448				uint8_t *sector,
1449	__in			size_t sector_length,
1450	__out_bcount(data_size)	uint8_t *data,
1451	__in			size_t data_size,
1452	__in			boolean_t handle_format_errors);
1453
1454extern				efx_rc_t
1455efx_bootcfg_read(
1456	__in			efx_nic_t *enp,
1457	__out_bcount(size)	caddr_t data,
1458	__in			size_t size);
1459
1460extern				efx_rc_t
1461efx_bootcfg_write(
1462	__in			efx_nic_t *enp,
1463	__in_bcount(size)	caddr_t data,
1464	__in			size_t size);
1465
1466#endif	/* EFSYS_OPT_BOOTCFG */
1467
1468#if EFSYS_OPT_DIAG
1469
1470typedef enum efx_pattern_type_t {
1471	EFX_PATTERN_BYTE_INCREMENT = 0,
1472	EFX_PATTERN_ALL_THE_SAME,
1473	EFX_PATTERN_BIT_ALTERNATE,
1474	EFX_PATTERN_BYTE_ALTERNATE,
1475	EFX_PATTERN_BYTE_CHANGING,
1476	EFX_PATTERN_BIT_SWEEP,
1477	EFX_PATTERN_NTYPES
1478} efx_pattern_type_t;
1479
1480typedef			void
1481(*efx_sram_pattern_fn_t)(
1482	__in		size_t row,
1483	__in		boolean_t negate,
1484	__out		efx_qword_t *eqp);
1485
1486extern	__checkReturn	efx_rc_t
1487efx_sram_test(
1488	__in		efx_nic_t *enp,
1489	__in		efx_pattern_type_t type);
1490
1491#endif	/* EFSYS_OPT_DIAG */
1492
1493extern	__checkReturn	efx_rc_t
1494efx_sram_buf_tbl_set(
1495	__in		efx_nic_t *enp,
1496	__in		uint32_t id,
1497	__in		efsys_mem_t *esmp,
1498	__in		size_t n);
1499
1500extern		void
1501efx_sram_buf_tbl_clear(
1502	__in	efx_nic_t *enp,
1503	__in	uint32_t id,
1504	__in	size_t n);
1505
1506#define	EFX_BUF_TBL_SIZE	0x20000
1507
1508#define	EFX_BUF_SIZE		4096
1509
1510/* EV */
1511
1512typedef struct efx_evq_s	efx_evq_t;
1513
1514#if EFSYS_OPT_QSTATS
1515
1516/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1517typedef enum efx_ev_qstat_e {
1518	EV_ALL,
1519	EV_RX,
1520	EV_RX_OK,
1521	EV_RX_FRM_TRUNC,
1522	EV_RX_TOBE_DISC,
1523	EV_RX_PAUSE_FRM_ERR,
1524	EV_RX_BUF_OWNER_ID_ERR,
1525	EV_RX_IPV4_HDR_CHKSUM_ERR,
1526	EV_RX_TCP_UDP_CHKSUM_ERR,
1527	EV_RX_ETH_CRC_ERR,
1528	EV_RX_IP_FRAG_ERR,
1529	EV_RX_MCAST_PKT,
1530	EV_RX_MCAST_HASH_MATCH,
1531	EV_RX_TCP_IPV4,
1532	EV_RX_TCP_IPV6,
1533	EV_RX_UDP_IPV4,
1534	EV_RX_UDP_IPV6,
1535	EV_RX_OTHER_IPV4,
1536	EV_RX_OTHER_IPV6,
1537	EV_RX_NON_IP,
1538	EV_RX_BATCH,
1539	EV_TX,
1540	EV_TX_WQ_FF_FULL,
1541	EV_TX_PKT_ERR,
1542	EV_TX_PKT_TOO_BIG,
1543	EV_TX_UNEXPECTED,
1544	EV_GLOBAL,
1545	EV_GLOBAL_MNT,
1546	EV_DRIVER,
1547	EV_DRIVER_SRM_UPD_DONE,
1548	EV_DRIVER_TX_DESCQ_FLS_DONE,
1549	EV_DRIVER_RX_DESCQ_FLS_DONE,
1550	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1551	EV_DRIVER_RX_DSC_ERROR,
1552	EV_DRIVER_TX_DSC_ERROR,
1553	EV_DRV_GEN,
1554	EV_MCDI_RESPONSE,
1555	EV_NQSTATS
1556} efx_ev_qstat_t;
1557
1558/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1559
1560#endif	/* EFSYS_OPT_QSTATS */
1561
1562extern	__checkReturn	efx_rc_t
1563efx_ev_init(
1564	__in		efx_nic_t *enp);
1565
1566extern		void
1567efx_ev_fini(
1568	__in		efx_nic_t *enp);
1569
1570#define	EFX_EVQ_MAXNEVS		32768
1571#define	EFX_EVQ_MINNEVS		512
1572
1573#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1574#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1575
1576#define	EFX_EVQ_FLAGS_TYPE_MASK		(0x3)
1577#define	EFX_EVQ_FLAGS_TYPE_AUTO		(0x0)
1578#define	EFX_EVQ_FLAGS_TYPE_THROUGHPUT	(0x1)
1579#define	EFX_EVQ_FLAGS_TYPE_LOW_LATENCY	(0x2)
1580
1581#define	EFX_EVQ_FLAGS_NOTIFY_MASK	(0xC)
1582#define	EFX_EVQ_FLAGS_NOTIFY_INTERRUPT	(0x0)	/* Interrupting (default) */
1583#define	EFX_EVQ_FLAGS_NOTIFY_DISABLED	(0x4)	/* Non-interrupting */
1584
1585extern	__checkReturn	efx_rc_t
1586efx_ev_qcreate(
1587	__in		efx_nic_t *enp,
1588	__in		unsigned int index,
1589	__in		efsys_mem_t *esmp,
1590	__in		size_t n,
1591	__in		uint32_t id,
1592	__in		uint32_t us,
1593	__in		uint32_t flags,
1594	__deref_out	efx_evq_t **eepp);
1595
1596extern		void
1597efx_ev_qpost(
1598	__in		efx_evq_t *eep,
1599	__in		uint16_t data);
1600
1601typedef __checkReturn	boolean_t
1602(*efx_initialized_ev_t)(
1603	__in_opt	void *arg);
1604
1605#define	EFX_PKT_UNICAST		0x0004
1606#define	EFX_PKT_START		0x0008
1607
1608#define	EFX_PKT_VLAN_TAGGED	0x0010
1609#define	EFX_CKSUM_TCPUDP	0x0020
1610#define	EFX_CKSUM_IPV4		0x0040
1611#define	EFX_PKT_CONT		0x0080
1612
1613#define	EFX_CHECK_VLAN		0x0100
1614#define	EFX_PKT_TCP		0x0200
1615#define	EFX_PKT_UDP		0x0400
1616#define	EFX_PKT_IPV4		0x0800
1617
1618#define	EFX_PKT_IPV6		0x1000
1619#define	EFX_PKT_PREFIX_LEN	0x2000
1620#define	EFX_ADDR_MISMATCH	0x4000
1621#define	EFX_DISCARD		0x8000
1622
1623#define	EFX_EV_RX_NLABELS	32
1624#define	EFX_EV_TX_NLABELS	32
1625
1626typedef	__checkReturn	boolean_t
1627(*efx_rx_ev_t)(
1628	__in_opt	void *arg,
1629	__in		uint32_t label,
1630	__in		uint32_t id,
1631	__in		uint32_t size,
1632	__in		uint16_t flags);
1633
1634typedef	__checkReturn	boolean_t
1635(*efx_tx_ev_t)(
1636	__in_opt	void *arg,
1637	__in		uint32_t label,
1638	__in		uint32_t id);
1639
1640#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1641#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1642#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1643#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1644#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1645#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1646#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1647#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1648#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1649
1650typedef	__checkReturn	boolean_t
1651(*efx_exception_ev_t)(
1652	__in_opt	void *arg,
1653	__in		uint32_t label,
1654	__in		uint32_t data);
1655
1656typedef	__checkReturn	boolean_t
1657(*efx_rxq_flush_done_ev_t)(
1658	__in_opt	void *arg,
1659	__in		uint32_t rxq_index);
1660
1661typedef	__checkReturn	boolean_t
1662(*efx_rxq_flush_failed_ev_t)(
1663	__in_opt	void *arg,
1664	__in		uint32_t rxq_index);
1665
1666typedef	__checkReturn	boolean_t
1667(*efx_txq_flush_done_ev_t)(
1668	__in_opt	void *arg,
1669	__in		uint32_t txq_index);
1670
1671typedef	__checkReturn	boolean_t
1672(*efx_software_ev_t)(
1673	__in_opt	void *arg,
1674	__in		uint16_t magic);
1675
1676typedef	__checkReturn	boolean_t
1677(*efx_sram_ev_t)(
1678	__in_opt	void *arg,
1679	__in		uint32_t code);
1680
1681#define	EFX_SRAM_CLEAR		0
1682#define	EFX_SRAM_UPDATE		1
1683#define	EFX_SRAM_ILLEGAL_CLEAR	2
1684
1685typedef	__checkReturn	boolean_t
1686(*efx_wake_up_ev_t)(
1687	__in_opt	void *arg,
1688	__in		uint32_t label);
1689
1690typedef	__checkReturn	boolean_t
1691(*efx_timer_ev_t)(
1692	__in_opt	void *arg,
1693	__in		uint32_t label);
1694
1695typedef __checkReturn	boolean_t
1696(*efx_link_change_ev_t)(
1697	__in_opt	void *arg,
1698	__in		efx_link_mode_t	link_mode);
1699
1700#if EFSYS_OPT_MON_STATS
1701
1702typedef __checkReturn	boolean_t
1703(*efx_monitor_ev_t)(
1704	__in_opt	void *arg,
1705	__in		efx_mon_stat_t id,
1706	__in		efx_mon_stat_value_t value);
1707
1708#endif	/* EFSYS_OPT_MON_STATS */
1709
1710#if EFSYS_OPT_MAC_STATS
1711
1712typedef __checkReturn	boolean_t
1713(*efx_mac_stats_ev_t)(
1714	__in_opt	void *arg,
1715	__in		uint32_t generation
1716	);
1717
1718#endif	/* EFSYS_OPT_MAC_STATS */
1719
1720typedef struct efx_ev_callbacks_s {
1721	efx_initialized_ev_t		eec_initialized;
1722	efx_rx_ev_t			eec_rx;
1723	efx_tx_ev_t			eec_tx;
1724	efx_exception_ev_t		eec_exception;
1725	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1726	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1727	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1728	efx_software_ev_t		eec_software;
1729	efx_sram_ev_t			eec_sram;
1730	efx_wake_up_ev_t		eec_wake_up;
1731	efx_timer_ev_t			eec_timer;
1732	efx_link_change_ev_t		eec_link_change;
1733#if EFSYS_OPT_MON_STATS
1734	efx_monitor_ev_t		eec_monitor;
1735#endif	/* EFSYS_OPT_MON_STATS */
1736#if EFSYS_OPT_MAC_STATS
1737	efx_mac_stats_ev_t		eec_mac_stats;
1738#endif	/* EFSYS_OPT_MAC_STATS */
1739} efx_ev_callbacks_t;
1740
1741extern	__checkReturn	boolean_t
1742efx_ev_qpending(
1743	__in		efx_evq_t *eep,
1744	__in		unsigned int count);
1745
1746#if EFSYS_OPT_EV_PREFETCH
1747
1748extern			void
1749efx_ev_qprefetch(
1750	__in		efx_evq_t *eep,
1751	__in		unsigned int count);
1752
1753#endif	/* EFSYS_OPT_EV_PREFETCH */
1754
1755extern			void
1756efx_ev_qpoll(
1757	__in		efx_evq_t *eep,
1758	__inout		unsigned int *countp,
1759	__in		const efx_ev_callbacks_t *eecp,
1760	__in_opt	void *arg);
1761
1762extern	__checkReturn	efx_rc_t
1763efx_ev_usecs_to_ticks(
1764	__in		efx_nic_t *enp,
1765	__in		unsigned int usecs,
1766	__out		unsigned int *ticksp);
1767
1768extern	__checkReturn	efx_rc_t
1769efx_ev_qmoderate(
1770	__in		efx_evq_t *eep,
1771	__in		unsigned int us);
1772
1773extern	__checkReturn	efx_rc_t
1774efx_ev_qprime(
1775	__in		efx_evq_t *eep,
1776	__in		unsigned int count);
1777
1778#if EFSYS_OPT_QSTATS
1779
1780#if EFSYS_OPT_NAMES
1781
1782extern		const char *
1783efx_ev_qstat_name(
1784	__in	efx_nic_t *enp,
1785	__in	unsigned int id);
1786
1787#endif	/* EFSYS_OPT_NAMES */
1788
1789extern					void
1790efx_ev_qstats_update(
1791	__in				efx_evq_t *eep,
1792	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1793
1794#endif	/* EFSYS_OPT_QSTATS */
1795
1796extern		void
1797efx_ev_qdestroy(
1798	__in	efx_evq_t *eep);
1799
1800/* RX */
1801
1802extern	__checkReturn	efx_rc_t
1803efx_rx_init(
1804	__inout		efx_nic_t *enp);
1805
1806extern		void
1807efx_rx_fini(
1808	__in		efx_nic_t *enp);
1809
1810#if EFSYS_OPT_RX_SCATTER
1811	__checkReturn	efx_rc_t
1812efx_rx_scatter_enable(
1813	__in		efx_nic_t *enp,
1814	__in		unsigned int buf_size);
1815#endif	/* EFSYS_OPT_RX_SCATTER */
1816
1817#if EFSYS_OPT_RX_SCALE
1818
1819typedef enum efx_rx_hash_alg_e {
1820	EFX_RX_HASHALG_LFSR = 0,
1821	EFX_RX_HASHALG_TOEPLITZ
1822} efx_rx_hash_alg_t;
1823
1824#define	EFX_RX_HASH_IPV4	(1U << 0)
1825#define	EFX_RX_HASH_TCPIPV4	(1U << 1)
1826#define	EFX_RX_HASH_IPV6	(1U << 2)
1827#define	EFX_RX_HASH_TCPIPV6	(1U << 3)
1828
1829typedef unsigned int efx_rx_hash_type_t;
1830
1831typedef enum efx_rx_hash_support_e {
1832	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1833	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1834} efx_rx_hash_support_t;
1835
1836#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1837#define	EFX_MAXRSS		64	/* RX indirection entry range */
1838#define	EFX_MAXRSS_LEGACY	16	/* See bug16611 and bug17213 */
1839
1840typedef enum efx_rx_scale_support_e {
1841	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1842	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1843	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1844} efx_rx_scale_support_t;
1845
1846extern	__checkReturn	efx_rc_t
1847efx_rx_hash_support_get(
1848	__in		efx_nic_t *enp,
1849	__out		efx_rx_hash_support_t *supportp);
1850
1851
1852extern	__checkReturn	efx_rc_t
1853efx_rx_scale_support_get(
1854	__in		efx_nic_t *enp,
1855	__out		efx_rx_scale_support_t *supportp);
1856
1857extern	__checkReturn	efx_rc_t
1858efx_rx_scale_mode_set(
1859	__in	efx_nic_t *enp,
1860	__in	efx_rx_hash_alg_t alg,
1861	__in	efx_rx_hash_type_t type,
1862	__in	boolean_t insert);
1863
1864extern	__checkReturn	efx_rc_t
1865efx_rx_scale_tbl_set(
1866	__in		efx_nic_t *enp,
1867	__in_ecount(n)	unsigned int *table,
1868	__in		size_t n);
1869
1870extern	__checkReturn	efx_rc_t
1871efx_rx_scale_key_set(
1872	__in		efx_nic_t *enp,
1873	__in_ecount(n)	uint8_t *key,
1874	__in		size_t n);
1875
1876extern	__checkReturn	uint32_t
1877efx_pseudo_hdr_hash_get(
1878	__in		efx_rxq_t *erp,
1879	__in		efx_rx_hash_alg_t func,
1880	__in		uint8_t *buffer);
1881
1882#endif	/* EFSYS_OPT_RX_SCALE */
1883
1884extern	__checkReturn	efx_rc_t
1885efx_pseudo_hdr_pkt_length_get(
1886	__in		efx_rxq_t *erp,
1887	__in		uint8_t *buffer,
1888	__out		uint16_t *pkt_lengthp);
1889
1890#define	EFX_RXQ_MAXNDESCS		4096
1891#define	EFX_RXQ_MINNDESCS		512
1892
1893#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1894#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1895#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1896#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1897
1898typedef enum efx_rxq_type_e {
1899	EFX_RXQ_TYPE_DEFAULT,
1900	EFX_RXQ_TYPE_SCATTER,
1901	EFX_RXQ_NTYPES
1902} efx_rxq_type_t;
1903
1904extern	__checkReturn	efx_rc_t
1905efx_rx_qcreate(
1906	__in		efx_nic_t *enp,
1907	__in		unsigned int index,
1908	__in		unsigned int label,
1909	__in		efx_rxq_type_t type,
1910	__in		efsys_mem_t *esmp,
1911	__in		size_t n,
1912	__in		uint32_t id,
1913	__in		efx_evq_t *eep,
1914	__deref_out	efx_rxq_t **erpp);
1915
1916typedef struct efx_buffer_s {
1917	efsys_dma_addr_t	eb_addr;
1918	size_t			eb_size;
1919	boolean_t		eb_eop;
1920} efx_buffer_t;
1921
1922typedef struct efx_desc_s {
1923	efx_qword_t ed_eq;
1924} efx_desc_t;
1925
1926extern			void
1927efx_rx_qpost(
1928	__in		efx_rxq_t *erp,
1929	__in_ecount(n)	efsys_dma_addr_t *addrp,
1930	__in		size_t size,
1931	__in		unsigned int n,
1932	__in		unsigned int completed,
1933	__in		unsigned int added);
1934
1935extern		void
1936efx_rx_qpush(
1937	__in	efx_rxq_t *erp,
1938	__in	unsigned int added,
1939	__inout	unsigned int *pushedp);
1940
1941extern	__checkReturn	efx_rc_t
1942efx_rx_qflush(
1943	__in	efx_rxq_t *erp);
1944
1945extern		void
1946efx_rx_qenable(
1947	__in	efx_rxq_t *erp);
1948
1949extern		void
1950efx_rx_qdestroy(
1951	__in	efx_rxq_t *erp);
1952
1953/* TX */
1954
1955typedef struct efx_txq_s	efx_txq_t;
1956
1957#if EFSYS_OPT_QSTATS
1958
1959/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1960typedef enum efx_tx_qstat_e {
1961	TX_POST,
1962	TX_POST_PIO,
1963	TX_NQSTATS
1964} efx_tx_qstat_t;
1965
1966/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1967
1968#endif	/* EFSYS_OPT_QSTATS */
1969
1970extern	__checkReturn	efx_rc_t
1971efx_tx_init(
1972	__in		efx_nic_t *enp);
1973
1974extern		void
1975efx_tx_fini(
1976	__in	efx_nic_t *enp);
1977
1978#define	EFX_BUG35388_WORKAROUND(_encp)					\
1979	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1980
1981#define	EFX_TXQ_MAXNDESCS(_encp)					\
1982	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1983
1984#define	EFX_TXQ_MINNDESCS		512
1985
1986#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1987#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1988#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1989#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1990
1991#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1992
1993#define	EFX_TXQ_CKSUM_IPV4	0x0001
1994#define	EFX_TXQ_CKSUM_TCPUDP	0x0002
1995#define	EFX_TXQ_FATSOV2		0x0004
1996
1997extern	__checkReturn	efx_rc_t
1998efx_tx_qcreate(
1999	__in		efx_nic_t *enp,
2000	__in		unsigned int index,
2001	__in		unsigned int label,
2002	__in		efsys_mem_t *esmp,
2003	__in		size_t n,
2004	__in		uint32_t id,
2005	__in		uint16_t flags,
2006	__in		efx_evq_t *eep,
2007	__deref_out	efx_txq_t **etpp,
2008	__out		unsigned int *addedp);
2009
2010extern	__checkReturn	efx_rc_t
2011efx_tx_qpost(
2012	__in		efx_txq_t *etp,
2013	__in_ecount(n)	efx_buffer_t *eb,
2014	__in		unsigned int n,
2015	__in		unsigned int completed,
2016	__inout		unsigned int *addedp);
2017
2018extern	__checkReturn	efx_rc_t
2019efx_tx_qpace(
2020	__in		efx_txq_t *etp,
2021	__in		unsigned int ns);
2022
2023extern			void
2024efx_tx_qpush(
2025	__in		efx_txq_t *etp,
2026	__in		unsigned int added,
2027	__in		unsigned int pushed);
2028
2029extern	__checkReturn	efx_rc_t
2030efx_tx_qflush(
2031	__in		efx_txq_t *etp);
2032
2033extern			void
2034efx_tx_qenable(
2035	__in		efx_txq_t *etp);
2036
2037extern	__checkReturn	efx_rc_t
2038efx_tx_qpio_enable(
2039	__in		efx_txq_t *etp);
2040
2041extern			void
2042efx_tx_qpio_disable(
2043	__in		efx_txq_t *etp);
2044
2045extern	__checkReturn	efx_rc_t
2046efx_tx_qpio_write(
2047	__in			efx_txq_t *etp,
2048	__in_ecount(buf_length)	uint8_t *buffer,
2049	__in			size_t buf_length,
2050	__in			size_t pio_buf_offset);
2051
2052extern	__checkReturn	efx_rc_t
2053efx_tx_qpio_post(
2054	__in			efx_txq_t *etp,
2055	__in			size_t pkt_length,
2056	__in			unsigned int completed,
2057	__inout			unsigned int *addedp);
2058
2059extern	__checkReturn	efx_rc_t
2060efx_tx_qdesc_post(
2061	__in		efx_txq_t *etp,
2062	__in_ecount(n)	efx_desc_t *ed,
2063	__in		unsigned int n,
2064	__in		unsigned int completed,
2065	__inout		unsigned int *addedp);
2066
2067extern	void
2068efx_tx_qdesc_dma_create(
2069	__in	efx_txq_t *etp,
2070	__in	efsys_dma_addr_t addr,
2071	__in	size_t size,
2072	__in	boolean_t eop,
2073	__out	efx_desc_t *edp);
2074
2075extern	void
2076efx_tx_qdesc_tso_create(
2077	__in	efx_txq_t *etp,
2078	__in	uint16_t ipv4_id,
2079	__in	uint32_t tcp_seq,
2080	__in	uint8_t  tcp_flags,
2081	__out	efx_desc_t *edp);
2082
2083/* Number of FATSOv2 option descriptors */
2084#define	EFX_TX_FATSOV2_OPT_NDESCS		2
2085
2086/* Maximum number of DMA segments per TSO packet (not superframe) */
2087#define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2088
2089extern	void
2090efx_tx_qdesc_tso2_create(
2091	__in			efx_txq_t *etp,
2092	__in			uint16_t ipv4_id,
2093	__in			uint32_t tcp_seq,
2094	__in			uint16_t tcp_mss,
2095	__out_ecount(count)	efx_desc_t *edp,
2096	__in			int count);
2097
2098extern	void
2099efx_tx_qdesc_vlantci_create(
2100	__in	efx_txq_t *etp,
2101	__in	uint16_t tci,
2102	__out	efx_desc_t *edp);
2103
2104#if EFSYS_OPT_QSTATS
2105
2106#if EFSYS_OPT_NAMES
2107
2108extern		const char *
2109efx_tx_qstat_name(
2110	__in	efx_nic_t *etp,
2111	__in	unsigned int id);
2112
2113#endif	/* EFSYS_OPT_NAMES */
2114
2115extern					void
2116efx_tx_qstats_update(
2117	__in				efx_txq_t *etp,
2118	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2119
2120#endif	/* EFSYS_OPT_QSTATS */
2121
2122extern		void
2123efx_tx_qdestroy(
2124	__in	efx_txq_t *etp);
2125
2126
2127/* FILTER */
2128
2129#if EFSYS_OPT_FILTER
2130
2131#define	EFX_ETHER_TYPE_IPV4 0x0800
2132#define	EFX_ETHER_TYPE_IPV6 0x86DD
2133
2134#define	EFX_IPPROTO_TCP 6
2135#define	EFX_IPPROTO_UDP 17
2136
2137/* Use RSS to spread across multiple queues */
2138#define	EFX_FILTER_FLAG_RX_RSS		0x01
2139/* Enable RX scatter */
2140#define	EFX_FILTER_FLAG_RX_SCATTER	0x02
2141/*
2142 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2143 * May only be set by the filter implementation for each type.
2144 * A removal request will restore the automatic filter in its place.
2145 */
2146#define	EFX_FILTER_FLAG_RX_OVER_AUTO	0x04
2147/* Filter is for RX */
2148#define	EFX_FILTER_FLAG_RX		0x08
2149/* Filter is for TX */
2150#define	EFX_FILTER_FLAG_TX		0x10
2151
2152typedef unsigned int efx_filter_flags_t;
2153
2154typedef enum efx_filter_match_flags_e {
2155	EFX_FILTER_MATCH_REM_HOST = 0x0001,	/* Match by remote IP host
2156						 * address */
2157	EFX_FILTER_MATCH_LOC_HOST = 0x0002,	/* Match by local IP host
2158						 * address */
2159	EFX_FILTER_MATCH_REM_MAC = 0x0004,	/* Match by remote MAC address */
2160	EFX_FILTER_MATCH_REM_PORT = 0x0008,	/* Match by remote TCP/UDP port */
2161	EFX_FILTER_MATCH_LOC_MAC = 0x0010,	/* Match by remote TCP/UDP port */
2162	EFX_FILTER_MATCH_LOC_PORT = 0x0020,	/* Match by local TCP/UDP port */
2163	EFX_FILTER_MATCH_ETHER_TYPE = 0x0040,	/* Match by Ether-type */
2164	EFX_FILTER_MATCH_INNER_VID = 0x0080,	/* Match by inner VLAN ID */
2165	EFX_FILTER_MATCH_OUTER_VID = 0x0100,	/* Match by outer VLAN ID */
2166	EFX_FILTER_MATCH_IP_PROTO = 0x0200,	/* Match by IP transport
2167						 * protocol */
2168	/* Match otherwise-unmatched multicast and broadcast packets */
2169	EFX_FILTER_MATCH_UNKNOWN_MCAST_DST = 0x40000000,
2170	/* Match otherwise-unmatched unicast packets */
2171	EFX_FILTER_MATCH_UNKNOWN_UCAST_DST = 0x80000000,
2172} efx_filter_match_flags_t;
2173
2174typedef enum efx_filter_priority_s {
2175	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2176	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2177					 * address list or hardware
2178					 * requirements. This may only be used
2179					 * by the filter implementation for
2180					 * each NIC type. */
2181	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2182	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2183					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2184					 */
2185} efx_filter_priority_t;
2186
2187/*
2188 * FIXME: All these fields are assumed to be in little-endian byte order.
2189 * It may be better for some to be big-endian. See bug42804.
2190 */
2191
2192typedef struct efx_filter_spec_s {
2193	uint32_t	efs_match_flags;
2194	uint32_t	efs_priority:2;
2195	uint32_t	efs_flags:6;
2196	uint32_t	efs_dmaq_id:12;
2197	uint32_t	efs_rss_context;
2198	uint16_t	efs_outer_vid;
2199	uint16_t	efs_inner_vid;
2200	uint8_t		efs_loc_mac[EFX_MAC_ADDR_LEN];
2201	uint8_t		efs_rem_mac[EFX_MAC_ADDR_LEN];
2202	uint16_t	efs_ether_type;
2203	uint8_t		efs_ip_proto;
2204	uint16_t	efs_loc_port;
2205	uint16_t	efs_rem_port;
2206	efx_oword_t	efs_rem_host;
2207	efx_oword_t	efs_loc_host;
2208} efx_filter_spec_t;
2209
2210
2211/* Default values for use in filter specifications */
2212#define	EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT	0xffffffff
2213#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2214#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2215
2216extern	__checkReturn	efx_rc_t
2217efx_filter_init(
2218	__in		efx_nic_t *enp);
2219
2220extern			void
2221efx_filter_fini(
2222	__in		efx_nic_t *enp);
2223
2224extern	__checkReturn	efx_rc_t
2225efx_filter_insert(
2226	__in		efx_nic_t *enp,
2227	__inout		efx_filter_spec_t *spec);
2228
2229extern	__checkReturn	efx_rc_t
2230efx_filter_remove(
2231	__in		efx_nic_t *enp,
2232	__inout		efx_filter_spec_t *spec);
2233
2234extern	__checkReturn	efx_rc_t
2235efx_filter_restore(
2236	__in		efx_nic_t *enp);
2237
2238extern	__checkReturn	efx_rc_t
2239efx_filter_supported_filters(
2240	__in				efx_nic_t *enp,
2241	__out_ecount(buffer_length)	uint32_t *buffer,
2242	__in				size_t buffer_length,
2243	__out				size_t *list_lengthp);
2244
2245extern			void
2246efx_filter_spec_init_rx(
2247	__out		efx_filter_spec_t *spec,
2248	__in		efx_filter_priority_t priority,
2249	__in		efx_filter_flags_t flags,
2250	__in		efx_rxq_t *erp);
2251
2252extern			void
2253efx_filter_spec_init_tx(
2254	__out		efx_filter_spec_t *spec,
2255	__in		efx_txq_t *etp);
2256
2257extern	__checkReturn	efx_rc_t
2258efx_filter_spec_set_ipv4_local(
2259	__inout		efx_filter_spec_t *spec,
2260	__in		uint8_t proto,
2261	__in		uint32_t host,
2262	__in		uint16_t port);
2263
2264extern	__checkReturn	efx_rc_t
2265efx_filter_spec_set_ipv4_full(
2266	__inout		efx_filter_spec_t *spec,
2267	__in		uint8_t proto,
2268	__in		uint32_t lhost,
2269	__in		uint16_t lport,
2270	__in		uint32_t rhost,
2271	__in		uint16_t rport);
2272
2273extern	__checkReturn	efx_rc_t
2274efx_filter_spec_set_eth_local(
2275	__inout		efx_filter_spec_t *spec,
2276	__in		uint16_t vid,
2277	__in		const uint8_t *addr);
2278
2279extern	__checkReturn	efx_rc_t
2280efx_filter_spec_set_uc_def(
2281	__inout		efx_filter_spec_t *spec);
2282
2283extern	__checkReturn	efx_rc_t
2284efx_filter_spec_set_mc_def(
2285	__inout		efx_filter_spec_t *spec);
2286
2287#endif	/* EFSYS_OPT_FILTER */
2288
2289/* HASH */
2290
2291extern	__checkReturn		uint32_t
2292efx_hash_dwords(
2293	__in_ecount(count)	uint32_t const *input,
2294	__in			size_t count,
2295	__in			uint32_t init);
2296
2297extern	__checkReturn		uint32_t
2298efx_hash_bytes(
2299	__in_ecount(length)	uint8_t const *input,
2300	__in			size_t length,
2301	__in			uint32_t init);
2302
2303#if EFSYS_OPT_LICENSING
2304
2305/* LICENSING */
2306
2307typedef struct efx_key_stats_s {
2308	uint32_t	eks_valid;
2309	uint32_t	eks_invalid;
2310	uint32_t	eks_blacklisted;
2311	uint32_t	eks_unverifiable;
2312	uint32_t	eks_wrong_node;
2313	uint32_t	eks_licensed_apps_lo;
2314	uint32_t	eks_licensed_apps_hi;
2315	uint32_t	eks_licensed_features_lo;
2316	uint32_t	eks_licensed_features_hi;
2317} efx_key_stats_t;
2318
2319extern	__checkReturn		efx_rc_t
2320efx_lic_init(
2321	__in			efx_nic_t *enp);
2322
2323extern				void
2324efx_lic_fini(
2325	__in			efx_nic_t *enp);
2326
2327extern	__checkReturn	boolean_t
2328efx_lic_check_support(
2329	__in			efx_nic_t *enp);
2330
2331extern	__checkReturn	efx_rc_t
2332efx_lic_update_licenses(
2333	__in		efx_nic_t *enp);
2334
2335extern	__checkReturn	efx_rc_t
2336efx_lic_get_key_stats(
2337	__in		efx_nic_t *enp,
2338	__out		efx_key_stats_t *ksp);
2339
2340extern	__checkReturn	efx_rc_t
2341efx_lic_app_state(
2342	__in		efx_nic_t *enp,
2343	__in		uint64_t app_id,
2344	__out		boolean_t *licensedp);
2345
2346extern	__checkReturn	efx_rc_t
2347efx_lic_get_id(
2348	__in		efx_nic_t *enp,
2349	__in		size_t buffer_size,
2350	__out		uint32_t *typep,
2351	__out		size_t *lengthp,
2352	__out_opt	uint8_t *bufferp);
2353
2354
2355extern	__checkReturn		efx_rc_t
2356efx_lic_find_start(
2357	__in			efx_nic_t *enp,
2358	__in_bcount(buffer_size)
2359				caddr_t bufferp,
2360	__in			size_t buffer_size,
2361	__out			uint32_t *startp
2362	);
2363
2364extern	__checkReturn		efx_rc_t
2365efx_lic_find_end(
2366	__in			efx_nic_t *enp,
2367	__in_bcount(buffer_size)
2368				caddr_t bufferp,
2369	__in			size_t buffer_size,
2370	__in			uint32_t offset,
2371	__out			uint32_t *endp
2372	);
2373
2374extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2375efx_lic_find_key(
2376	__in			efx_nic_t *enp,
2377	__in_bcount(buffer_size)
2378				caddr_t bufferp,
2379	__in			size_t buffer_size,
2380	__in			uint32_t offset,
2381	__out			uint32_t *startp,
2382	__out			uint32_t *lengthp
2383	);
2384
2385extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2386efx_lic_validate_key(
2387	__in			efx_nic_t *enp,
2388	__in_bcount(length)	caddr_t keyp,
2389	__in			uint32_t length
2390	);
2391
2392extern	__checkReturn		efx_rc_t
2393efx_lic_read_key(
2394	__in			efx_nic_t *enp,
2395	__in_bcount(buffer_size)
2396				caddr_t bufferp,
2397	__in			size_t buffer_size,
2398	__in			uint32_t offset,
2399	__in			uint32_t length,
2400	__out_bcount_part(key_max_size, *lengthp)
2401				caddr_t keyp,
2402	__in			size_t key_max_size,
2403	__out			uint32_t *lengthp
2404	);
2405
2406extern	__checkReturn		efx_rc_t
2407efx_lic_write_key(
2408	__in			efx_nic_t *enp,
2409	__in_bcount(buffer_size)
2410				caddr_t bufferp,
2411	__in			size_t buffer_size,
2412	__in			uint32_t offset,
2413	__in_bcount(length)	caddr_t keyp,
2414	__in			uint32_t length,
2415	__out			uint32_t *lengthp
2416	);
2417
2418	__checkReturn		efx_rc_t
2419efx_lic_delete_key(
2420	__in			efx_nic_t *enp,
2421	__in_bcount(buffer_size)
2422				caddr_t bufferp,
2423	__in			size_t buffer_size,
2424	__in			uint32_t offset,
2425	__in			uint32_t length,
2426	__in			uint32_t end,
2427	__out			uint32_t *deltap
2428	);
2429
2430extern	__checkReturn		efx_rc_t
2431efx_lic_create_partition(
2432	__in			efx_nic_t *enp,
2433	__in_bcount(buffer_size)
2434				caddr_t bufferp,
2435	__in			size_t buffer_size
2436	);
2437
2438extern	__checkReturn		efx_rc_t
2439efx_lic_finish_partition(
2440	__in			efx_nic_t *enp,
2441	__in_bcount(buffer_size)
2442				caddr_t bufferp,
2443	__in			size_t buffer_size
2444	);
2445
2446#endif	/* EFSYS_OPT_LICENSING */
2447
2448
2449
2450#ifdef	__cplusplus
2451}
2452#endif
2453
2454#endif	/* _SYS_EFX_H */
2455