if_krreg.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (C) 2007
5 *	Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: stable/11/sys/mips/idt/if_krreg.h 330897 2018-03-14 03:19:51Z eadler $
29 *
30 */
31
32#ifndef __IF_KRREG_H__
33#define __IF_KRREG_H__
34
35#define	KR_ETHINTFC 	0x0000	/* Ethernet interface control             */
36#define		ETH_INTFC_EN 	0x0001
37#define		ETH_INTFC_RIP 	0x0004
38#define		ETH_INTFC_EN 	0x0001
39#define	KR_ETHFIFOTT	0x0004	/* Ethernet FIFO transmit threshold       */
40#define	KR_ETHARC   	0x0008	/* Ethernet address recognition control   */
41#define	KR_ETHHASH0 	0x000C	/* Ethernet hash table 0                  */
42#define	KR_ETHHASH1 	0x0010	/* Ethernet hash table 1                  */
43#define	KR_ETHPFS   	0x0024	/* Ethernet pause frame status            */
44#define	KR_ETHMCP   	0x0028	/* Ethernet management clock prescalar    */
45#define	KR_ETHSAL0  	0x0100	/* Ethernet station address 0 low         */
46#define	KR_ETHSAH0  	0x0104	/* Ethernet station address 0 high        */
47#define	KR_ETHSAL1  	0x0108	/* Ethernet station address 1 low         */
48#define	KR_ETHSAH1  	0x010C	/* Ethernet station address 1 high        */
49#define	KR_ETHSAL2  	0x0110	/* Ethernet station address 2 low         */
50#define	KR_ETHSAH2  	0x0114	/* Ethernet station address 2 high        */
51#define	KR_ETHSAL3  	0x0118	/* Ethernet station address 3 low         */
52#define	KR_ETHSAH3  	0x011C	/* Ethernet station address 3 high        */
53#define	KR_ETHRBC   	0x0120	/* Ethernet receive byte count            */
54#define	KR_ETHRPC   	0x0124	/* Ethernet receive packet count          */
55#define	KR_ETHRUPC  	0x0128	/* Ethernet receive undersized packet cnt */
56#define	KR_ETHRFC   	0x012C	/* Ethernet receive fragment count        */
57#define	KR_ETHTBC   	0x0130	/* Ethernet transmit byte count           */
58#define	KR_ETHGPF   	0x0134	/* Ethernet generate pause frame          */
59#define	KR_ETHMAC1 	0x0200	/* Ethernet MAC configuration 1           */
60#define		KR_ETH_MAC1_RE	0x01
61#define		KR_ETH_MAC1_PAF	0x02
62#define		KR_ETH_MAC1_MR	0x80
63#define	KR_ETHMAC2 	0x0204	/* Ethernet MAC configuration 2           */
64#define		KR_ETH_MAC2_FD	0x01
65#define		KR_ETH_MAC2_FLC	0x02
66#define		KR_ETH_MAC2_HFE	0x04
67#define		KR_ETH_MAC2_DC	0x08
68#define		KR_ETH_MAC2_CEN	0x10
69#define		KR_ETH_MAC2_PEN	0x20
70#define		KR_ETH_MAC2_VPE	0x08
71#define	KR_ETHIPGT 	0x0208	/* Ethernet back-to-back inter-packet gap */
72#define	KR_ETHIPGR 	0x020C	/* Ethernet non back-to-back inter-packet gap */
73#define	KR_ETHCLRT 	0x0210	/* Ethernet collision window retry        */
74#define	KR_ETHMAXF 	0x0214	/* Ethernet maximum frame length          */
75#define	KR_ETHMTEST	0x021C	/* Ethernet MAC test                      */
76#define	KR_MIIMCFG 	0x0220	/* MII management configuration           */
77#define		KR_MIIMCFG_R	0x8000
78#define	KR_MIIMCMD 	0x0224	/* MII management command                 */
79#define		KR_MIIMCMD_RD 	0x01
80#define		KR_MIIMCMD_SCN 	0x02
81#define	KR_MIIMADDR	0x0228	/* MII management address                 */
82#define	KR_MIIMWTD 	0x022C	/* MII management write data              */
83#define	KR_MIIMRDD 	0x0230	/* MII management read data               */
84#define	KR_MIIMIND 	0x0234	/* MII management indicators              */
85#define		KR_MIIMIND_BSY 	0x1
86#define		KR_MIIMIND_SCN 	0x2
87#define		KR_MIIMIND_NV 	0x4
88#define	KR_ETHCFSA0	0x0240	/* Ethernet control frame station address 0   */
89#define	KR_ETHCFSA1	0x0244	/* Ethernet control frame station address 1   */
90#define	KR_ETHCFSA2	0x0248	/* Ethernet control frame station address 2   */
91
92#define	KR_ETHIPGT_HALF_DUPLEX	0x12
93#define	KR_ETHIPGT_FULL_DUPLEX	0x15
94
95#define KR_TIMEOUT	0xf000
96#define KR_MII_TIMEOUT	0xf000
97
98#define KR_RX_IRQ	40
99#define KR_TX_IRQ	41
100#define KR_RX_UND_IRQ	42
101#define KR_TX_OVR_IRQ	43
102#define RC32434_DMA_BASE_ADDR	MIPS_PHYS_TO_KSEG1(0x18040000)
103#define		DMA_C		0x00
104#define			DMA_C_R		0x01
105#define			DMA_C_ABORT	0x10
106#define		DMA_S		0x04
107#define			DMA_S_F		0x01
108#define			DMA_S_D		0x02
109#define			DMA_S_C		0x04
110#define			DMA_S_E		0x08
111#define			DMA_S_H		0x10
112#define		DMA_SM		0x08
113#define			DMA_SM_F	0x01
114#define			DMA_SM_D	0x02
115#define			DMA_SM_C	0x04
116#define			DMA_SM_E	0x08
117#define			DMA_SM_H	0x10
118#define		DMA_DPTR	0x0C
119#define		DMA_NDPTR	0x10
120
121#define	RC32434_DMA_CHAN_SIZE	0x14
122#define KR_DMA_RXCHAN		0
123#define KR_DMA_TXCHAN		1
124
125#define	KR_DMA_READ_REG(chan, reg) \
126	(*(volatile uint32_t *)	\
127	    (RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg))
128
129#define	KR_DMA_WRITE_REG(chan, reg, val) \
130	((*(volatile uint32_t *)	\
131	    (RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg)) = val)
132
133#define	KR_DMA_SETBITS_REG(chan, reg, bits) \
134	KR_DMA_WRITE_REG((chan), (reg), KR_DMA_READ_REG((chan), (reg)) | (bits))
135
136#define	KR_DMA_CLEARBITS_REG(chan, reg, bits)		\
137	KR_DMA_WRITE_REG((chan), (reg),			\
138	    KR_DMA_READ_REG((chan), (reg)) & ~(bits))
139
140struct kr_desc {
141	uint32_t	kr_ctl;
142	uint32_t	kr_ca;
143	uint32_t	kr_devcs;
144	uint32_t	kr_link;
145};
146
147
148#define KR_DMASIZE(len)		((len)  & ((1 << 18)-1))
149#define KR_PKTSIZE(len)		((len & 0xffff0000) >> 16)
150
151#define	KR_CTL_COF	0x02000000
152#define	KR_CTL_COD	0x04000000
153#define	KR_CTL_IOF	0x08000000
154#define	KR_CTL_IOD	0x10000000
155#define	KR_CTL_T	0x20000000
156#define	KR_CTL_D	0x40000000
157#define	KR_CTL_F	0x80000000
158
159#define	KR_DMARX_DEVCS_RSV	0x00000001
160#define	KR_DMARX_DEVCS_LD	0x00000002
161#define	KR_DMARX_DEVCS_ROK	0x00000004
162#define	KR_DMARX_DEVCS_FM	0x00000008
163#define	KR_DMARX_DEVCS_MP	0x00000010
164#define	KR_DMARX_DEVCS_BP	0x00000020
165#define	KR_DMARX_DEVCS_VLT	0x00000040
166#define	KR_DMARX_DEVCS_CF	0x00000080
167#define	KR_DMARX_DEVCS_OVR	0x00000100
168#define	KR_DMARX_DEVCS_CRC	0x00000200
169#define	KR_DMARX_DEVCS_CV	0x00000400
170#define	KR_DMARX_DEVCS_DB	0x00000800
171#define	KR_DMARX_DEVCS_LE	0x00001000
172#define	KR_DMARX_DEVCS_LOR	0x00002000
173#define	KR_DMARX_DEVCS_CES	0x00004000
174
175#define	KR_DMATX_DEVCS_FD	0x00000001
176#define	KR_DMATX_DEVCS_LD	0x00000002
177#define	KR_DMATX_DEVCS_OEN	0x00000004
178#define	KR_DMATX_DEVCS_PEN	0x00000008
179#define	KR_DMATX_DEVCS_CEN	0x00000010
180#define	KR_DMATX_DEVCS_HEN	0x00000020
181#define	KR_DMATX_DEVCS_TOK	0x00000040
182#define	KR_DMATX_DEVCS_MP	0x00000080
183#define	KR_DMATX_DEVCS_BP	0x00000100
184#define	KR_DMATX_DEVCS_UND	0x00000200
185#define	KR_DMATX_DEVCS_OF	0x00000400
186#define	KR_DMATX_DEVCS_ED	0x00000800
187#define	KR_DMATX_DEVCS_EC	0x00001000
188#define	KR_DMATX_DEVCS_LC	0x00002000
189#define	KR_DMATX_DEVCS_TD	0x00004000
190#define	KR_DMATX_DEVCS_CRC	0x00008000
191#define	KR_DMATX_DEVCS_LE	0x00010000
192
193#define KR_RX_RING_CNT		128
194#define KR_TX_RING_CNT		128
195#define KR_TX_RING_SIZE		sizeof(struct kr_desc) * KR_TX_RING_CNT
196#define KR_RX_RING_SIZE		sizeof(struct kr_desc) * KR_RX_RING_CNT
197#define KR_RING_ALIGN		sizeof(struct kr_desc)
198#define KR_RX_ALIGN		sizeof(uint32_t)
199#define KR_MAXFRAGS		8
200#define KR_TX_INTR_THRESH	8
201
202#define	KR_TX_RING_ADDR(sc, i)	\
203    ((sc)->kr_rdata.kr_tx_ring_paddr + sizeof(struct kr_desc) * (i))
204#define	KR_RX_RING_ADDR(sc, i)	\
205    ((sc)->kr_rdata.kr_rx_ring_paddr + sizeof(struct kr_desc) * (i))
206#define	KR_INC(x,y)		(x) = (((x) + 1) % y)
207
208struct kr_txdesc {
209	struct mbuf	*tx_m;
210	bus_dmamap_t	tx_dmamap;
211};
212
213struct kr_rxdesc {
214	struct mbuf	*rx_m;
215	bus_dmamap_t	rx_dmamap;
216	struct kr_desc	*desc;
217	/* Use this values on error instead of allocating new mbuf */
218	uint32_t	saved_ctl, saved_ca;
219};
220
221struct kr_chain_data {
222	bus_dma_tag_t		kr_parent_tag;
223	bus_dma_tag_t		kr_tx_tag;
224	struct kr_txdesc	kr_txdesc[KR_TX_RING_CNT];
225	bus_dma_tag_t		kr_rx_tag;
226	struct kr_rxdesc	kr_rxdesc[KR_RX_RING_CNT];
227	bus_dma_tag_t		kr_tx_ring_tag;
228	bus_dma_tag_t		kr_rx_ring_tag;
229	bus_dmamap_t		kr_tx_ring_map;
230	bus_dmamap_t		kr_rx_ring_map;
231	bus_dmamap_t		kr_rx_sparemap;
232	int			kr_tx_pkts;
233	int			kr_tx_prod;
234	int			kr_tx_cons;
235	int			kr_tx_cnt;
236	int			kr_rx_cons;
237};
238
239struct kr_ring_data {
240	struct kr_desc		*kr_rx_ring;
241	struct kr_desc		*kr_tx_ring;
242	bus_addr_t		kr_rx_ring_paddr;
243	bus_addr_t		kr_tx_ring_paddr;
244};
245
246struct kr_softc {
247	struct ifnet		*kr_ifp;	/* interface info */
248	bus_space_handle_t	kr_bhandle;	/* bus space handle */
249	bus_space_tag_t		kr_btag;	/* bus space tag */
250	device_t		kr_dev;
251	struct resource		*kr_res;
252	int			kr_rid;
253	struct resource		*kr_rx_irq;
254	void			*kr_rx_intrhand;
255	struct resource		*kr_tx_irq;
256	void			*kr_tx_intrhand;
257	struct resource		*kr_rx_und_irq;
258	void			*kr_rx_und_intrhand;
259	struct resource		*kr_tx_ovr_irq;
260	void			*kr_tx_ovr_intrhand;
261	device_t		kr_miibus;
262	bus_dma_tag_t		kr_parent_tag;
263	bus_dma_tag_t		kr_tag;
264	struct mtx		kr_mtx;
265	struct callout		kr_stat_callout;
266	struct task		kr_link_task;
267	struct kr_chain_data	kr_cdata;
268	struct kr_ring_data	kr_rdata;
269	int			kr_link_status;
270	int			kr_detach;
271};
272
273#define	KR_LOCK(_sc)		mtx_lock(&(_sc)->kr_mtx)
274#define	KR_UNLOCK(_sc)		mtx_unlock(&(_sc)->kr_mtx)
275#define	KR_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->kr_mtx, MA_OWNED)
276
277/*
278 * register space access macros
279 */
280#define CSR_WRITE_4(sc, reg, val)	\
281	bus_space_write_4(sc->kr_btag, sc->kr_bhandle, reg, val)
282
283#define CSR_READ_4(sc, reg)		\
284	bus_space_read_4(sc->kr_btag, sc->kr_bhandle, reg)
285
286#endif /* __IF_KRREG_H__ */
287