if_xereg.h revision 331722
1/*- 2 * Copyright (c) 1998, 1999 Scott Mitchell 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: if_xereg.h,v 1.5 1999/05/20 21:53:58 scott Exp $ 27 * $FreeBSD: stable/11/sys/dev/xe/if_xereg.h 331722 2018-03-29 02:50:57Z eadler $ 28 */ 29#ifndef DEV_XE_IF_XEREG_H 30#define DEV_XE_IF_XEREG_H 31 32/* 33 * Register definitions for Xircom PCMCIA Ethernet controllers, based on 34 * Rev. B of the "Dingo" 10/100 controller used in Xircom CEM56 and RealPort 35 * Ethernet/modem cards. The Dingo can be configured to be register 36 * compatible with the "Mohawk" 10/100 controller used in Xircom CE3 cards 37 * (also some Intel and Compaq OEM versions of the CE3). The older 10Mbps CE2 38 * cards seem to use earlier revisions of the same device. Some registers and 39 * bits below are marked 'CE2 only'; these are used by Werner Koch's xirc2ps 40 * driver that was originally for the CE2 but, according to the spec, aren't 41 * present on the Dingo. They often seem to relate to operation on coax 42 * cables, which Mohawk can do in theory (it has the SSI interface) so they 43 * _might_ also work on Mohawk. I've also noted the few registers that are 44 * specific to Dingo. 45 * 46 * As far as I can tell, the Dingo is basically a Mohawk device with a few 47 * registers and support for a second PCMCIA function (the modem) added. In 48 * Dingo mode the SSI (non-MII) PHY interface of the Mohawk is not available. 49 * The CE2 chip is most likely a Mohawk without the MII and definitely with a 50 * slightly different register set. 51 * 52 * In all cases, the controller uses a paged model of register access. The 53 * first eight registers are always the same, the function of the second eight 54 * is selected by the value in the Page Register (reg 0x01). 55 * 56 * References: 57 * 1. Dingo External Reference Specification, Revision B. Xircom Inc., 58 * Thousand Oaks, California. August 1998. Available under licence from 59 * Xircom, http://www.xircom.com/ 60 * 2. ML6692 100BASE-TX Physical Layer with MII specification. MicroLinear 61 * Corp, San Jose, California. May 1997. Available for download from 62 * http://www.microlinear.com/ 63 * 3. DP83840 10/100 Mb/s Ethernet Physical Layer specification. National 64 * Semiconductor Corp., Arlington, Texas. March 1997. Available for 65 * download from http://www.ns.com/ 66 * 4. Werner Koch's xirc2ps driver for Linux, for all the CE2 and CE3 frobs 67 * that aren't documented in the Xircom spec. Available for download from 68 * http://www.d.shuttle.de/isil/xircom/xirc2ps.html 69 */ 70 71/******************* 72 * PCMCIA registers 73 *******************/ 74 75/* 76 * These are probably Dingo-specific, but you won't need them unless you have 77 * a CEM card that needs a bit of hackery to get the Ethernet function to 78 * operate. All addresses are in card attribute space. 79 */ 80#define DINGO_CIS 0x0000 /* Start of CIS tuples */ 81#define DINGO_ETH 0x0800 /* Ethernet configuration registers */ 82#define DINGO_COR 0x0820 /* Dingo configuration option registers */ 83#define DINGO_2ND 0x0840 /* 2nd function configuration registers */ 84 85 86/* 87 * Ethernet configuration registers 88 */ 89#define DINGO_ECOR (DINGO_ETH+0) /* Ethernet Configuration Option Register */ 90#define DINGO_ECSR (DINGO_ETH+2) /* Ethernet Configuration Status Register */ 91#define DINGO_EBAR0 (DINGO_ETH+10) /* Ethernet Base Address Register bits 7:4 (3:0 always 0) */ 92#define DINGO_EBAR1 (DINGO_ETH+12) /* Ethernet Base Address Register bits 15:8 */ 93 94/* DINGO_ECOR bits */ 95#define DINGO_ECOR_ETH_ENABLE 0x01 /* 1 = Enable Ethernet part of adapter */ 96#define DINGO_ECOR_IOB_ENABLE 0x02 /* 1 = Enable EBAR, else use INDEX bits */ 97#define DINGO_ECOR_INT_ENABLE 0x04 /* 1 = Enable Ethernet interrupts */ 98#define DINGO_ECOR_IOB_INDEX 0x18 /* 00 = 0x300; 01 = 0x310; 10 = 0x320; 11 = no IO base */ 99#define DINGO_ECOR_IOB_SHIFT 0x03 100#define DINGO_ECOR_IRQ_STSCHG 0x20 /* 1 = Route interrupts to -STSCHG pin, else use -INT pin */ 101#define DINGO_ECOR_IRQ_LEVEL 0x40 /* 1 = Level-triggered interrupts, else edge-triggered */ 102#define DINGO_ECOR_SRESET 0x80 /* 1 = Soft reset Ethernet adpater. Must write to 0 */ 103 104/* DINGO_ECSR bits */ 105#define DINGO_ECSR_INT_ACK 0x01 /* 1 = Host must acknowledge interrupts (Clear ECSR_INT bit) */ 106#define DINGO_ECSR_INT 0x02 /* 1 = Interrupt service requested */ 107#define DINGO_ECSR_POWER_DOWN 0x04 /* 1 = Power down Ethernet adapter */ 108 109/* 110 * EBAR0/EBAR1 set the I/O base address of the Ethernet adapter when 111 * ECOR_IOB_ENABLE is set. 12 significant bits. 112 */ 113 114 115/* 116 * Dingo configuration registers 117 */ 118#define DINGO_DCOR0 (DINGO_COR+0) /* Dingo Configuration Options Register 0 */ 119#define DINGO_DCOR1 (DINGO_COR+2) /* Dingo Configuration Options Register 1 */ 120#define DINGO_DCOR2 (DINGO_COR+4) /* Dingo Configuration Options Register 2 */ 121#define DINGO_DCOR3 (DINGO_COR+6) /* Dingo Configuration Options Register 3 */ 122#define DINGO_DCOR4 (DINGO_COR+8) /* Dingo Configuration Options Register 4 */ 123 124/* DINGO_DCOR0 bits */ 125#define DINGO_DCOR0_SF_INT 0x01 /* 1 = Enable 2ndF interrupts (alternate to SFCOR:2) */ 126#define DINGO_DCOR0_DECODE 0x04 /* 1 = Decode 2ndF interrupts in Dingo, else in 2ndF */ 127#define DINGO_DCOR0_BUS 0x08 /* 1 = 2ndF bus is ISA, else PCMCIA */ 128#define DINGO_DCOR0_LED3_POWER 0x10 /* 1 = Drive LED3 line from SFCSR:2 */ 129#define DINGO_DCOR0_LED3_RESET 0x20 /* 1 = Drive LED3 line from SFCOR:7 */ 130#define DINGO_DCOR0_MR_POWER 0x40 /* 1 = Drive MRESET line from SFCSR:2 */ 131#define DINGO_DCOR0_MR_RESET 0x80 /* 1 = Drive MRESET line from SFCOR:7 */ 132 133/* DINGO_DCOR1 bits */ 134#define DINGO_DCOR1_INT_STSCHG 0x01 /* 1 = Route 2ndF interrupts to -STSCHG (alternate to SFCOR:5) */ 135#define DINGO_DCOR1_MSTSCHG 0x02 /* 1 = Route 2ndF -MSTSCHG line to -STSCHG */ 136#define DINGO_DCOR1_EEDIO 0x04 /* 1 = Use EEDIO pin as data line 6 to 2ndF */ 137#define DINGO_DCOR1_INT_LEVEL 0x08 /* 1 = Force level-triggered interrupts from 2ndF */ 138#define DINGO_DCOR1_SHADOW_CSR 0x10 /* Reserved, always write 0 */ 139#define DINGO_DCOR1_SHADOW_IOB 0x20 /* Reserved, always write 0 */ 140#define DINGO_DCOR1_CSR_WAIT 0xC0 /* Reserved, always write 0 */ 141#define DINGO_DCOR1_CSR_SHIFT 0x06 142 143/* DINGO_DCOR2 bits */ 144#define DINGO_DCOR2_SHM_BASE 0x0f /* Bits 15-12 of Ethernet shared memory window */ 145#define DINGO_DCOR2_SHM_SHIFT 0x00 146#define DINGO_DCOR2_SHADOW_COR 0x10 /* Reserved, always write 0 */ 147 148/* 149 * DCOR3/DCOR4 configure Dingo to assert -IOIS16 on any access to each pair of 150 * ports in the range SFIOB+0 .. SFIOB+31. Each pair can be set individually, 151 * eg. DCOR3:0 enables this function on ports SFIOB+0 and SFIOB+1. 152 */ 153 154 155/* 156 * Second function configuration registers 157 */ 158#define DINGO_SFCOR (DINGO_2ND+0) /* 2nd Function Configuration Option Register */ 159#define DINGO_SFCSR (DINGO_2ND+2) /* 2nd Function Configuration Status Register */ 160#define DINGO_SFBAR0 (DINGO_2ND+10) /* 2nd Function Base Address Register bits 7:0 */ 161#define DINGO_SFBAR1 (DINGO_2ND+12) /* 2nd Function Base Address Register bits 15:8 */ 162#define DINGO_SFILR (DINGO_2ND+18) /* 2nd Function I/O Limit Register */ 163 164/* DINGO_SFCOR bits */ 165#define DINGO_SFCOR_SF_ENABLE 0x01 /* 1 = Enable second fuction */ 166#define DINGO_SFCOR_IOB_ENABLE 0x02 /* 1 = Enable SFBAR, else use COM_SELECT bits */ 167#define DINGO_SFCOR_INT_ENABLE 0x04 /* 1 = Enable second function interrupts */ 168#define DINGO_SFCOR_COM_SELECT 0x18 /* 00 = 0x3f8; 01 = 0x2f8; 10 = 0x3e8; 11 = 0x2e8 */ 169#define DINGO_SFCOR_COM_SHIFT 0x03 170#define DINGO_SFCOR_IRQ_STSCHG 0x20 /* 1 = Route interrupts to -STSCHG pin, else use -INT pin */ 171#define DINGO_SFCOR_IRQ_LEVEL 0x40 /* 1 = Level-triggered interrupts, else edge-triggered */ 172#define DINGO_SFCOR_SRESET 0x80 /* 1 = Soft reset second function. Must write to 0 */ 173 174/* DINGO_SFCSR bits */ 175#define DINGO_SFCSR_INT_ACK 0x01 /* 1 = Host must acknowledge interrupts (Clear SFCSR_INT bit) */ 176#define DINGO_SFCSR_INT 0x02 /* 1 = Interrupt service requested */ 177#define DINGO_SFCSR_POWER_DOWN 0x04 /* 1 = Power down second function */ 178 179/* 180 * SFBAR0/SFBAR1 set the I/O base address of the second function when 181 * SFCOR_IOB_ENABLE is set. 16 significant bits. 182 */ 183 184/* 185 * SFILR is a bitmap of address lines 7:0 decoded by the second function 186 * device. Eg. a device with 16 ports should write 0x0f to this register. 187 */ 188 189 190 191/******************************** 192 * Ethernet controller registers 193 ********************************/ 194 195/* 196 * Common registers (available from any register page) 197 * 198 * Note: The EDP is actually 32 bits wide, occupying registers 2-5. In PCMCIA 199 * operation we can only access 16 bits at once, through registers 4 & 5. 200 */ 201#define XE_CR 0x00 /* Command register (write) */ 202#define XE_ESR 0x00 /* Ethernet status register (read) */ 203#define XE_PR 0x01 /* Page select register */ 204#define XE_EDP 0x04 /* Ethernet data port */ 205#define XE_ISR 0x06 /* Ethernet interrupt status register (read) */ 206#define XE_GIR 0x07 /* Global interrupt register (Dingo only) */ 207 208/* XE_CR bits */ 209#define XE_CR_TX_PACKET 0x01 /* Transmit packet */ 210#define XE_CR_SOFT_RESET 0x02 /* Software reset */ 211#define XE_CR_ENABLE_INTR 0x04 /* Enable interrupts */ 212#define XE_CR_FORCE_INTR 0x08 /* Force an interrupt */ 213#define XE_CR_CLEAR_FIFO 0x10 /* Clear FIFO after transmit overrun */ 214#define XE_CR_CLEAR_OVERRUN 0x20 /* Clear receive overrun condition */ 215#define XE_CR_RESTART_TX 0x40 /* Restart TX after 16 collisions or TX underrun */ 216 217/* XE_ESR bits */ 218#define XE_ESR_FULL_PACKET_RX 0x01 /* At least one full packet received */ 219#define XE_ESR_PART_PACKET_RX 0x02 /* At least 64 bytes of packet received */ 220#define XE_ESR_REJECT_PACKET 0x04 /* Partial packet rejected */ 221#define XE_ESR_TX_PENDING 0x08 /* At least one packet waiting to transmit */ 222#define XE_ESR_BAD_POLARITY 0x10 /* Bad cable polarity? (CE2 only) */ 223#define XE_ESR_MEDIA_SELECT 0x20 /* SSI(?) media select: 1 = Twisted pair; 0 = AUI */ 224 225/* XE_ISR bits */ 226#define XE_ISR_TX_OVERFLOW 0x01 /* No space in transmit buffer */ 227#define XE_ISR_TX_PACKET 0x02 /* Packet sent successfully */ 228#define XE_ISR_MAC_INTR 0x04 /* Some kind of MAC interrupt happened */ 229#define XE_ISR_RX_EARLY 0x10 /* Incoming packet in early receive mode */ 230#define XE_ISR_RX_PACKET 0x20 /* Complete packet received successfully */ 231#define XE_ISR_RX_REJECT 0x40 /* Partial incoming packet rejected by MAC */ 232#define XE_ISR_FORCE_INTR 0x80 /* Interrupt forced */ 233 234/* XE_GIR bits */ 235#define XE_GIR_ETH_IRQ 0x01 /* Ethernet IRQ pending */ 236#define XE_GIR_ETH_MASK 0x02 /* 1 = Mask Ethernet interrupts to host */ 237#define XE_GIR_SF_IRQ 0x04 /* Second function IRQ pending */ 238#define XE_GIR_SF_MASK 0x08 /* 1 = Mask second function interrupts to host */ 239 240 241/* 242 * Page 0 registers 243 */ 244#define XE_TSO 0x08 /* Transmit space open (17 bits) */ 245#define XE_TRS 0x0a /* Transmit reservation size (CE2 only, removed in rev. 1) */ 246#define XE_DO 0x0c /* Data offset register (13 bits/3 flags, write) */ 247#define XE_RSR 0x0c /* Receive status register (read) */ 248#define XE_TPR 0x0d /* Packets transmitted register (read) */ 249#define XE_RBC 0x0e /* Received byte count (13 bits/3 flags, read) */ 250 251/* XE_DO bits */ 252#define XE_DO_OFFSET 0x1fff /* First byte fetched when CHANGE_OFFSET issued */ 253#define XE_DO_OFFSET_SHIFT 0x00 254#define XE_DO_CHANGE_OFFSET 0x2000 /* Flush RX FIFO, start fetching from OFFSET */ 255#define XE_DO_SHARED_MEM 0x4000 /* Enable shared memory mode */ 256#define XE_DO_SKIP_RX_PACKET 0x8000 /* Skip to next packet in buffer memory */ 257 258/* XE_RSR bits */ 259#define XE_RSR_PHYS_PACKET 0x01 /* 1 = Physical packet, 0 = Multicast packet */ 260#define XE_RSR_BCAST_PACKET 0x02 /* Broadcast packet */ 261#define XE_RSR_LONG_PACKET 0x04 /* Packet >1518 bytes */ 262#define XE_RSR_ADDR_MATCH 0x08 /* Packet matched one of our node addresses */ 263#define XE_RSR_ALIGN_ERROR 0x10 /* Bad alignment? (CE2 only) */ 264#define XE_RSR_CRC_ERROR 0x20 /* Incorrect CRC */ 265#define XE_RSR_RX_OK 0x80 /* No errors on received packet */ 266 267/* XE_RBC bits */ 268#define XE_RBC_BYTE_COUNT 0x1fff /* Bytes received for current packet */ 269#define XE_RBC_COUNT_SHIFT 0x00 270#define XE_RBC_FULL_PACKET_RX 0x2000 /* These mirror bits 2:0 of ESR, if ECR:7 is set */ 271#define XE_RBC_PART_PACKET_RX 0x4000 272#define XE_RBC_REJECT_PACKET 0x8000 273 274 275/* 276 * Page 1 registers 277 */ 278#define XE_IMR0 0x0c /* Interrupt mask register 0 */ 279#define XE_IMR1 0x0d /* Interrupt mask register 1 (CE2 only) */ 280#define XE_ECR 0x0e /* Ethernet configuration register */ 281 282/* XE_IMR0 bits */ 283#define XE_IMR0_TX_OVERFLOW 0x01 /* Masks for bits in ISR */ 284#define XE_IMR0_TX_PACKET 0x02 285#define XE_IMR0_MAC_INTR 0x04 286#define XE_IMR0_TX_RESGRANT 0x08 /* Tx reservation granted (CE2) */ 287#define XE_IMR0_RX_EARLY 0x10 288#define XE_IMR0_RX_PACKET 0x20 289#define XE_IMR0_RX_REJECT 0x40 290#define XE_IMR0_FORCE_INTR 0x80 291 292/* XE_IMR1 bits */ 293#define XE_IMR1_TX_UNDERRUN 0x01 294 295/* XE_ECR bits */ 296#define XE_ECR_EARLY_TX 0x01 /* Enable early transmit mode */ 297#define XE_ECR_EARLY_RX 0x02 /* Enable early receive mode */ 298#define XE_ECR_FULL_DUPLEX 0x04 /* Enable full-duplex (disable collision detection) */ 299#define XE_ECR_LONG_TPCABLE 0x08 /* CE2 only */ 300#define XE_ECR_NO_POL_COL 0x10 /* CE2 only */ 301#define XE_ECR_NO_LINK_PULSE 0x20 /* Don't check/send link pulses (not 10BT compliant) */ 302#define XE_ECR_NO_AUTO_TX 0x40 /* CE2 only */ 303#define XE_ECR_SOFT_COMPAT 0x80 /* Map ESR bits 2:0 to RBC bits 15:13 */ 304 305 306/* 307 * Page 2 registers 308 */ 309#define XE_RBS 0x08 /* Receive buffer start (16 bits) */ 310#define XE_LED 0x0a /* LED control register */ 311#define XE_LED3 0x0b /* LED3 control register */ 312#define XE_MSR 0x0c /* Misc. setup register (Mohawk specific register?) */ 313#define XE_GPR2 0x0d /* General purpose register 2 */ 314 315/* 316 * LED function selection: 317 * 000 - Disabled 318 * 001 - Collision activity 319 * 010 - !Collision activity 320 * 011 - 10Mbit link detected 321 * 100 - 100Mbit link detected 322 * 101 - 10/100Mbit link detected 323 * 110 - Automatic assertion 324 * 111 - Transmit activity 325 */ 326 327/* XE_LED bits */ 328#define XE_LED_LED0_MASK 0x07 /* LED0 function selection */ 329#define XE_LED_LED0_SHIFT 0x00 330#define XE_LED_LED1_MASK 0x38 /* LED1 function selection */ 331#define XE_LED_LED1_SHIFT 0x03 332#define XE_LED_LED0_RX 0x40 /* Add receive activity to LED0 */ 333#define XE_LED_LED1_RX 0x80 /* Add receive activity to LED1 */ 334 335/* XE_LED3 bits */ 336#define XE_LED3_MASK 0x07 /* LED3 function selection */ 337#define XE_LED3_SHIFT 0x00 338#define XE_LED3_RX 0x40 /* Add receive activity to LED3 */ 339 340/* XE_MSR bits */ 341#define XE_MSR_128K_SRAM 0x01 /* Select 128K SRAM */ 342#define XE_MSR_RBS_BIT16 0x02 /* Bit 16 of RBS (only useful with big SRAM) */ 343#define XE_MSR_MII_SELECT 0x08 /* Select MII instead of SSI interface */ 344#define XE_MSR_HASH_TABLE 0x20 /* Enable hash table filtering */ 345 346/* XE_GPR2 bits */ 347#define XE_GPR2_GP3_OUT 0x01 /* Value written to GP3 line */ 348#define XE_GPR2_GP4_OUT 0x02 /* Value written to GP4 line */ 349#define XE_GPR2_GP3_SELECT 0x04 /* 1 = GP3 is output, 0 = GP3 is input */ 350#define XE_GPR2_GP4_SELECT 0x08 /* 1 = GP4 is output, 0 = GP3 is input */ 351#define XE_GPR2_GP3_IN 0x10 /* Value read from GP3 line */ 352#define XE_GPR2_GP4_IN 0x20 /* Value read from GP4 line */ 353 354 355/* 356 * Page 3 registers 357 */ 358#define XE_TPT 0x0a /* Transmit packet threshold (13 bits) */ 359 360 361/* 362 * Page 4 registers 363 */ 364#define XE_GPR0 0x08 /* General purpose register 0 */ 365#define XE_GPR1 0x09 /* General purpose register 1 */ 366#define XE_BOV 0x0a /* Bonding version register (read) */ 367#define XE_EES 0x0b /* EEPROM control register */ 368#define XE_LMA 0x0c /* Local memory address (CE2 only) */ 369#define XE_LMD 0x0e /* Local memory data (CE2 only) */ 370 371/* XE_GPR0 bits */ 372#define XE_GPR0_GP1_OUT 0x01 /* Value written to GP1 line */ 373#define XE_GPR0_GP2_OUT 0x02 /* Value written to GP2 line */ 374#define XE_GPR0_GP1_SELECT 0x04 /* 1 = GP1 is output, 0 = GP1 is input */ 375#define XE_GPR0_GP2_SELECT 0x08 /* 1 = GP2 is output, 0 = GP2 is input */ 376#define XE_GPR0_GP1_IN 0x10 /* Value read from GP1 line */ 377#define XE_GPR0_GP2_IN 0x20 /* Value read from GP2 line */ 378 379/* XE_GPR1 bits */ 380#define XE_GPR1_POWER_DOWN 0x01 /* 0 = Power down analog section */ 381#define XE_GPR1_AIC 0x04 /* AIC bit (CE2 only) */ 382 383/* XE_BOV values */ 384#define XE_BOV_DINGO 0x55 /* Dingo in Dingo mode */ 385#define XE_BOV_MOHAWK 0x41 /* Original Mohawk */ 386#define XE_BOV_MOHAWK_REV1 0x45 /* Rev. 1 Mohawk, or Dingo in Mohawk mode */ 387#define XE_BOV_CEM28 0x11 /* CEM28 */ 388 389/* XE_EES bits */ 390#define XE_EES_SCL_OUTPUT 0x01 /* Value written to SCL line, when MANUAL_ROM set */ 391#define XE_EES_SDA_OUTPUT 0x02 /* Value written to SDA line, when MANUAL_ROM set */ 392#define XE_EES_SDA_INPUT 0x04 /* Value read from SDA line */ 393#define XE_EES_SDA_TRISTATE 0x08 /* 1 = SDA is output, 0 = SDA is input */ 394#define XE_EES_MANUAL_ROM 0x20 /* Enable manual contro of serial EEPROM */ 395 396 397/* 398 * Page 5 registers (all read only) 399 */ 400#define XE_CRHA 0x08 /* Current Rx host address (16 bits) */ 401#define XE_RHSA 0x0a /* Rx host start address (16 bits) */ 402#define XE_RNSA 0x0c /* Rx network start address (16 bits) */ 403#define XE_CRNA 0x0e /* Current Rx network address (16 bits) */ 404 405 406/* 407 * Page 6 registers (all read only) 408 */ 409#define XE_CTHA 0x08 /* Current Tx host address (16 bits) */ 410#define XE_THSA 0x0a /* Tx host start address (16 bits) */ 411#define XE_TNSA 0x0c /* Tx network statr address (16 bits) */ 412#define XE_CTNA 0x0e /* Current Tx network address (16 bits) */ 413 414 415/* 416 * Page 8 registers (all read only) 417 */ 418#define XE_THBC 0x08 /* Tx host byte count (16 bits) */ 419#define XE_THPS 0x0a /* Tx host packet size (16 bits) */ 420#define XE_TNBC 0x0c /* Tx network byte count (16 bits) */ 421#define XE_TNPS 0x0e /* Tx network packet size (16 bits) */ 422 423 424/* 425 * Page 0x10 registers (all read only) 426 */ 427#define XE_DINGOID 0x08 /* Dingo ID register (16 bits) (Dingo only) */ 428#define XE_RevID 0x0a /* Dingo revision ID (16 bits) (Dingo only) */ 429#define XE_VendorID 0x0c /* Dingo vendor ID (16 bits) (Dingo only) */ 430 431/* Values for the above registers */ 432#define XE_DINGOID_DINGO3 0x444b /* In both Dingo and Mohawk modes */ 433#define XE_RevID_DINGO3 0x0001 434#define XE_VendorID_DINGO3 0x0041 435 436 437/* 438 * Page 0x40 registers 439 */ 440#define XE_CMD0 0x08 /* MAC Command register (write) */ 441#define XE_RST0 0x09 /* Receive status register */ 442#define XE_TXST0 0x0b /* Transmit status register 0 */ 443#define XE_TXST1 0x0c /* Transmit status register 1 */ 444#define XE_RX0Msk 0x0d /* Receive status mask register */ 445#define XE_TX0Msk 0x0e /* Transmit status 0 mask register */ 446#define XE_TX1Msk 0x0f /* Transmit status 1 mask register */ 447 448/* CMD0 bits */ 449#define XE_CMD0_TX 0x01 /* CE2 only */ 450#define XE_CMD0_RX_ENABLE 0x04 /* Enable receiver */ 451#define XE_CMD0_RX_DISABLE 0x08 /* Disable receiver */ 452#define XE_CMD0_ABORT 0x10 /* CE2 only */ 453#define XE_CMD0_ONLINE 0x20 /* Take MAC online */ 454#define XE_CMD0_ACK_INTR 0x40 /* CE2 only */ 455#define XE_CMD0_OFFLINE 0x80 /* Take MAC offline */ 456 457/* RST0 bits */ 458#define XE_RST0_LONG_PACKET 0x02 /* Packet received with >1518 and <8184 bytes */ 459#define XE_RST0_CRC_ERROR 0x08 /* Packet received with incorrect CRC */ 460#define XE_RST0_RX_OVERRUN 0x10 /* Receiver overrun, byte(s) dropped */ 461#define XE_RST0_RX_ENABLE 0x20 /* Receiver enabled */ 462#define XE_RST0_RX_ABORT 0x40 /* Receive aborted: CRC, FIFO overrun or addr mismatch */ 463#define XE_RST0_RX_OK 0x80 /* Complete packet received OK */ 464 465/* TXST0 bits */ 466#define XE_TXST0_NO_CARRIER 0x01 /* Lost carrier. Only valid in 10Mbit half-duplex */ 467#define XE_TXST0_16_COLLISIONS 0x02 /* Packet aborted after 16 collisions */ 468#define XE_TXST0_TX_UNDERRUN 0x08 /* MAC ran out of data to send */ 469#define XE_TXST0_LATE_COLLISION 0x10 /* Collision later than 512 bits */ 470#define XE_TXST0_SQE_FAIL 0x20 /* SQE test failed. */ 471#define XE_TXST0_TX_ABORT 0x40 /* Transmit aborted: collisions, underrun or overrun */ 472#define XE_TXST0_TX_OK 0x80 /* Complete packet sent OK */ 473 474/* TXST1 bits */ 475#define XE_TXST1_RETRY_COUNT 0x0f /* Collision counter for current packet */ 476#define XE_TXST1_LINK_STATUS 0x10 /* Valid link status */ 477 478/* RX0Msk bits */ 479#define XE_RX0M_MP 0x01 /* Multicast packet? (CE2 only) */ 480#define XE_RX0M_LONG_PACKET 0x02 /* Masks for bits in RXST0 */ 481#define XE_RX0M_ALIGN_ERROR 0x04 /* Alignment error (CE2 only) */ 482#define XE_RX0M_CRC_ERROR 0x08 483#define XE_RX0M_RX_OVERRUN 0x10 484#define XE_RX0M_RX_ABORT 0x40 485#define XE_RX0M_RX_OK 0x80 486 487/* TX0Msk bits */ 488#define XE_TX0M_NO_CARRIER 0x01 /* Masks for bits in TXST0 */ 489#define XE_TX0M_16_COLLISIONS 0x02 490#define XE_TX0M_TX_UNDERRUN 0x08 491#define XE_TX0M_LATE_COLLISION 0x10 492#define XE_TX0M_SQE_FAIL 0x20 493#define XE_TX0M_TX_ABORT 0x40 494#define XE_TX0M_TX_OK 0x80 495 496/* TX1Msk bits */ 497#define XE_TX1M_PKTDEF 0x20 498 499 500/* 501 * Page 0x42 registers 502 */ 503#define XE_SWC0 0x08 /* Software configuration 0 */ 504#define XE_SWC1 0x09 /* Software configuration 1 */ 505#define XE_BOC 0x0a /* Back-off configuration */ 506#define XE_TCD 0x0b /* Transmit collision deferral */ 507 508/* SWC0 bits */ 509#define XE_SWC0_LOOPBACK_ENABLE 0x01 /* Enable loopback operation */ 510#define XE_SWC0_LOOPBACK_SOURCE 0x02 /* 1 = Transceiver, 0 = MAC */ 511#define XE_SWC0_ACCEPT_ERROR 0x04 /* Accept otherwise OK packets with CRC errors */ 512#define XE_SWC0_ACCEPT_SHORT 0x08 /* Accept otherwise OK packets that are too short */ 513#define XE_SWC0_NO_SRC_INSERT 0x20 /* Disable source insertion (CE2) */ 514#define XE_SWC0_NO_CRC_INSERT 0x40 /* Don't add CRC to outgoing packets */ 515 516/* SWC1 bits */ 517#define XE_SWC1_IA_ENABLE 0x01 /* Enable individual address filters */ 518#define XE_SWC1_ALLMULTI 0x02 /* Accept all multicast packets */ 519#define XE_SWC1_PROMISCUOUS 0x04 /* Accept all non-multicast packets */ 520#define XE_SWC1_BCAST_DISABLE 0x08 /* Reject broadcast packets */ 521#define XE_SWC1_MEDIA_SELECT 0x40 /* AUI media select (Mohawk only) */ 522#define XE_SWC1_AUTO_MEDIA 0x80 /* Auto media select (Mohawk only) */ 523 524 525/* 526 * Page 0x44 registers (CE2 only) 527 */ 528#define XE_TDR0 0x08 /* Time domain reflectometry register 0 */ 529#define XE_TDR1 0x09 /* Time domain reflectometry register 1 */ 530#define XE_RXC0 0x0a /* Receive byte count low */ 531#define XE_RXC1 0x0b /* Receive byte count high */ 532 533 534/* 535 * Page 0x45 registers (CE2 only) 536 */ 537#define XE_REV 0x0f /* Revision (read) */ 538 539 540/* 541 * Page 0x50-0x57: Individual address 0-9 542 * 543 * Used to filter incoming packets by matching against individual node 544 * addresses. If IA matching is enabled (SWC1, bit0) any incoming packet with 545 * a destination matching one of these 10 addresses will be received. IA0 is 546 * always enabled and usually matches the card's unique address. 547 * 548 * Addresses are stored LSB first, ie. IA00 (reg. 8 on page 0x50) contains the 549 * LSB of IA0, and so on. The data is stored contiguously, in that addresses 550 * can be broken across page boundaries. That is: 551 * 552 * Reg: 50/8 50/9 50/a 50/b 50/c 50/d 50/e 50/f 51/8 51/9 ... 57/a 57/b 553 * IA00 IA01 IA02 IA03 IA04 IA05 IA10 IA11 IA12 IA13 ... IA94 IA95 554 */ 555 556/* 557 * Page 0x58: Multicast hash table filter 558 * 559 * In case the 10 individual addresses aren't enough, we also have a multicast 560 * hash filter, enabled through MSR:5. The most significant six bits of the 561 * CRC on each incoming packet are reversed and used as an index into the 64 562 * bits of the hash table. If the appropriate bit is set the packet it 563 * received, although higher layers may still need to filter it out. The CRC 564 * calculation is as follows: 565 * 566 * crc = 0xffffffff; 567 * poly = 0x04c11db6; 568 * for (i = 0; i < 6; i++) { 569 * current = mcast_addr[i]; 570 * for (k = 1; k <= 8; k++) { 571 * if (crc & 0x80000000) 572 * crc31 = 0x01; 573 * else 574 * crc31 = 0; 575 * bit = crc31 ^ (current & 0x01); 576 * crc <<= 1; 577 * current >>= 1; 578 * if (bit) 579 * crc = (crc ^ poly)|1 580 * } 581 * } 582 */ 583 584 585 586/**************** 587 * MII registers 588 ****************/ 589 590/* 591 * Basic MII-compliant PHY register definitions. According to the Dingo spec, 592 * PHYs from (at least) MicroLinear, National Semiconductor, ICS, TDK and 593 * Quality Semiconductor have been used. These apparently all come up with 594 * PHY ID 0x00 unless the "interceptor module" on the Dingo 3 is in use. With 595 * the interceptor enabled, the PHY is faked up to look like an ICS unit with 596 * ID 0x16. The interceptor can be enabled/disabled in software. 597 * 598 * The ML6692 (and maybe others) doesn't have a 10Mbps mode -- this is handled 599 * by an internal 10Mbps transceiver that we know nothing about... some cards 600 * seem to work with the MII in 10Mbps mode, so I guess some PHYs must support 601 * it. The question is, how can you figure out which one you have? Just to 602 * add to the fun there are also 10Mbps _only_ Mohawk/Dingo cards. Aaargh! 603 */ 604 605/* 606 * Masks for the MII-related bits in GPR2 607 */ 608#define XE_MII_CLK XE_GPR2_GP3_OUT 609#define XE_MII_DIR XE_GPR2_GP4_SELECT 610#define XE_MII_WRD XE_GPR2_GP4_OUT 611#define XE_MII_RDD XE_GPR2_GP4_IN 612 613/* 614 * MII PHY ID register values 615 */ 616#define PHY_ID_ML6692 0x0000 /* MicroLinear ML6692? Or unknown */ 617#define PHY_ID_ICS1890 0x0015 /* ICS1890 */ 618#define PHY_ID_QS6612 0x0181 /* Quality QS6612 */ 619#define PHY_ID_DP83840 0x2000 /* National DP83840 */ 620 621/* 622 * MII command (etc) bit strings. 623 */ 624#define XE_MII_STARTDELIM 0x01 625#define XE_MII_READOP 0x02 626#define XE_MII_WRITEOP 0x01 627#define XE_MII_TURNAROUND 0x02 628 629/* 630 * PHY registers. 631 */ 632#define PHY_BMCR 0x00 /* Basic Mode Control Register */ 633#define PHY_BMSR 0x01 /* Basic Mode Status Register */ 634#define PHY_ID1 0x02 /* PHY ID 1 */ 635#define PHY_ID2 0x03 /* PHY ID 2 */ 636#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ 637#define PHY_LPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */ 638#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ 639 640/* BMCR bits */ 641#define PHY_BMCR_RESET 0x8000 /* Soft reset PHY. Self-clearing */ 642#define PHY_BMCR_LOOPBK 0x4000 /* Enable loopback */ 643#define PHY_BMCR_SPEEDSEL 0x2000 /* 1=100Mbps, 0=10Mbps */ 644#define PHY_BMCR_AUTONEGENBL 0x1000 /* Auto-negotiation enabled */ 645#define PHY_BMCR_ISOLATE 0x0400 /* Isolate ML6692 from MII */ 646#define PHY_BMCR_AUTONEGRSTR 0x0200 /* Restart auto-negotiation. Self-clearing */ 647#define PHY_BMCR_DUPLEX 0x0100 /* Full duplex operation */ 648#define PHY_BMCR_COLLTEST 0x0080 /* Enable collision test */ 649 650/* BMSR bits */ 651#define PHY_BMSR_100BT4 0x8000 /* 100Base-T4 capable */ 652#define PHY_BMSR_100BTXFULL 0x4000 /* 100Base-TX full duplex capable */ 653#define PHY_BMSR_100BTXHALF 0x2000 /* 100Base-TX half duplex capable */ 654#define PHY_BMSR_10BTFULL 0x1000 /* 10Base-T full duplex capable */ 655#define PHY_BMSR_10BTHALF 0x0800 /* 10Base-T half duplex capable */ 656#define PHY_BMSR_AUTONEGCOMP 0x0020 /* Auto-negotiation complete */ 657#define PHY_BMSR_CANAUTONEG 0x0008 /* Auto-negotiation supported */ 658#define PHY_BMSR_LINKSTAT 0x0004 /* Link is up */ 659#define PHY_BMSR_EXTENDED 0x0001 /* Extended register capabilities */ 660 661/* ANAR bits */ 662#define PHY_ANAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 663#define PHY_ANAR_TLRFLT 0x2000 /* Remote wire fault detected */ 664#define PHY_ANAR_100BT4 0x0200 /* 100Base-T4 capable */ 665#define PHY_ANAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 666#define PHY_ANAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 667#define PHY_ANAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 668#define PHY_ANAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 669#define PHY_ANAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 670#define PHY_ANAR_PROTO3 0x0008 671#define PHY_ANAR_PROTO2 0x0004 672#define PHY_ANAR_PROTO1 0x0002 673#define PHY_ANAR_PROTO0 0x0001 674#define PHY_ANAR_8023 PHY_ANAR_PROTO0 675#define PHY_ANAR_DINGO PHY_ANAR_100BT+PHY_ANAR_10BT_FD+PHY_ANAR_10BT+PHY_ANAR_8023 676#define PHY_ANAR_MOHAWK PHY_ANAR_100BT+PHY_ANAR_10BT_FD+PHY_ANAR_10BT+PHY_ANAR_8023 677 678/* LPAR bits */ 679#define PHY_LPAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 680#define PHY_LPAR_LPACK 0x4000 /* Link partner acknowledged receipt */ 681#define PHY_LPAR_TLRFLT 0x2000 /* Remote wire fault detected */ 682#define PHY_LPAR_100BT4 0x0200 /* 100Base-T4 capable */ 683#define PHY_LPAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 684#define PHY_LPAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 685#define PHY_LPAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 686#define PHY_LPAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 687#define PHY_LPAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 688#define PHY_LPAR_PROTO3 0x0008 689#define PHY_LPAR_PROTO2 0x0004 690#define PHY_LPAR_PROTO1 0x0002 691#define PHY_LPAR_PROTO0 0x0001 692 693/* ANER bits */ 694#define PHY_ANER_MLFAULT 0x0010 /* More than one link is up! */ 695#define PHY_ANER_LPNPABLE 0x0008 /* Link partner supports next page */ 696#define PHY_ANER_NPABLE 0x0004 /* Local port supports next page */ 697#define PHY_ANER_PAGERX 0x0002 /* Page received */ 698#define PHY_ANER_LPAUTONEG 0x0001 /* Link partner can auto-negotiate */ 699 700#endif /* DEV_XE_IF_XEREG_H */ 701