if_smscreg.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 5 * Ben Gray <bgray@freebsd.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/dev/usb/net/if_smscreg.h 330897 2018-03-14 03:19:51Z eadler $ 30 */ 31#ifndef _IF_SMSCREG_H_ 32#define _IF_SMSCREG_H_ 33 34/* 35 * Definitions for the SMSC LAN9514 and LAN9514 USB to ethernet controllers. 36 * 37 * This information was gleaned from the SMSC driver in the linux kernel, where 38 * it is Copyrighted (C) 2007-2008 SMSC. 39 * 40 */ 41 42/** 43 * TRANSMIT FRAMES 44 * --------------- 45 * Tx frames are prefixed with an 8-byte header which describes the frame 46 * 47 * 4 bytes 4 bytes variable 48 * +------------+------------+--- . . . . . . . . . . . . ---+ 49 * | TX_CTRL_0 | TX_CTRL_1 | Ethernet frame data | 50 * +------------+------------+--- . . . . . . . . . . . . ---+ 51 * 52 * Where the headers have the following fields: 53 * 54 * TX_CTRL_0 <20:16> Data offset 55 * TX_CTRL_0 <13> First segment of frame indicator 56 * TX_CTRL_0 <12> Last segment of frame indicator 57 * TX_CTRL_0 <10:0> Buffer size (?) 58 * 59 * TX_CTRL_1 <14> Perform H/W checksuming on IP packets 60 * TX_CTRL_1 <13> Disable automatic ethernet CRC generation 61 * TX_CTRL_1 <12> Disable padding (?) 62 * TX_CTRL_1 <10:0> Packet byte length 63 * 64 */ 65#define SMSC_TX_CTRL_0_OFFSET(x) (((x) & 0x1FUL) << 16) 66#define SMSC_TX_CTRL_0_FIRST_SEG (0x1UL << 13) 67#define SMSC_TX_CTRL_0_LAST_SEG (0x1UL << 12) 68#define SMSC_TX_CTRL_0_BUF_SIZE(x) ((x) & 0x000007FFUL) 69 70#define SMSC_TX_CTRL_1_CSUM_ENABLE (0x1UL << 14) 71#define SMSC_TX_CTRL_1_CRC_DISABLE (0x1UL << 13) 72#define SMSC_TX_CTRL_1_PADDING_DISABLE (0x1UL << 12) 73#define SMSC_TX_CTRL_1_PKT_LENGTH(x) ((x) & 0x000007FFUL) 74 75/** 76 * RECEIVE FRAMES 77 * -------------- 78 * Rx frames are prefixed with an 4-byte status header which describes any 79 * errors with the frame as well as things like the length 80 * 81 * 4 bytes variable 82 * +------------+--- . . . . . . . . . . . . ---+ 83 * | RX_STAT | Ethernet frame data | 84 * +------------+--- . . . . . . . . . . . . ---+ 85 * 86 * Where the status header has the following fields: 87 * 88 * RX_STAT <30> Filter Fail 89 * RX_STAT <29:16> Frame Length 90 * RX_STAT <15> Error Summary 91 * RX_STAT <13> Broadcast Frame 92 * RX_STAT <12> Length Error 93 * RX_STAT <11> Runt Frame 94 * RX_STAT <10> Multicast Frame 95 * RX_STAT <7> Frame too long 96 * RX_STAT <6> Collision Seen 97 * RX_STAT <5> Frame Type 98 * RX_STAT <4> Receive Watchdog 99 * RX_STAT <3> Mii Error 100 * RX_STAT <2> Dribbling 101 * RX_STAT <1> CRC Error 102 * 103 */ 104#define SMSC_RX_STAT_FILTER_FAIL (0x1UL << 30) 105#define SMSC_RX_STAT_FRM_LENGTH(x) (((x) >> 16) & 0x3FFFUL) 106#define SMSC_RX_STAT_ERROR (0x1UL << 15) 107#define SMSC_RX_STAT_BROADCAST (0x1UL << 13) 108#define SMSC_RX_STAT_LENGTH_ERROR (0x1UL << 12) 109#define SMSC_RX_STAT_RUNT (0x1UL << 11) 110#define SMSC_RX_STAT_MULTICAST (0x1UL << 10) 111#define SMSC_RX_STAT_FRM_TO_LONG (0x1UL << 7) 112#define SMSC_RX_STAT_COLLISION (0x1UL << 6) 113#define SMSC_RX_STAT_FRM_TYPE (0x1UL << 5) 114#define SMSC_RX_STAT_WATCHDOG (0x1UL << 4) 115#define SMSC_RX_STAT_MII_ERROR (0x1UL << 3) 116#define SMSC_RX_STAT_DRIBBLING (0x1UL << 2) 117#define SMSC_RX_STAT_CRC_ERROR (0x1UL << 1) 118 119/** 120 * REGISTERS 121 * 122 */ 123#define SMSC_ID_REV 0x000 124#define SMSC_INTR_STATUS 0x008 125#define SMSC_RX_CFG 0x00C 126#define SMSC_TX_CFG 0x010 127#define SMSC_HW_CFG 0x014 128#define SMSC_PM_CTRL 0x020 129#define SMSC_LED_GPIO_CFG 0x024 130#define SMSC_GPIO_CFG 0x028 131#define SMSC_AFC_CFG 0x02C 132#define SMSC_EEPROM_CMD 0x030 133#define SMSC_EEPROM_DATA 0x034 134#define SMSC_BURST_CAP 0x038 135#define SMSC_GPIO_WAKE 0x064 136#define SMSC_INTR_CFG 0x068 137#define SMSC_BULK_IN_DLY 0x06C 138#define SMSC_MAC_CSR 0x100 139#define SMSC_MAC_ADDRH 0x104 140#define SMSC_MAC_ADDRL 0x108 141#define SMSC_HASHH 0x10C 142#define SMSC_HASHL 0x110 143#define SMSC_MII_ADDR 0x114 144#define SMSC_MII_DATA 0x118 145#define SMSC_FLOW 0x11C 146#define SMSC_VLAN1 0x120 147#define SMSC_VLAN2 0x124 148#define SMSC_WUFF 0x128 149#define SMSC_WUCSR 0x12C 150#define SMSC_COE_CTRL 0x130 151 152/* ID / Revision register */ 153#define SMSC_ID_REV_CHIP_ID_MASK 0xFFFF0000UL 154#define SMSC_ID_REV_CHIP_REV_MASK 0x0000FFFFUL 155 156#define SMSC_RX_FIFO_FLUSH (0x1UL << 0) 157 158#define SMSC_TX_CFG_ON (0x1UL << 2) 159#define SMSC_TX_CFG_STOP (0x1UL << 1) 160#define SMSC_TX_CFG_FIFO_FLUSH (0x1UL << 0) 161 162#define SMSC_HW_CFG_BIR (0x1UL << 12) 163#define SMSC_HW_CFG_LEDB (0x1UL << 11) 164#define SMSC_HW_CFG_RXDOFF (0x3UL << 9) /* RX pkt alignment */ 165#define SMSC_HW_CFG_DRP (0x1UL << 6) 166#define SMSC_HW_CFG_MEF (0x1UL << 5) 167#define SMSC_HW_CFG_LRST (0x1UL << 3) /* Lite reset */ 168#define SMSC_HW_CFG_PSEL (0x1UL << 2) 169#define SMSC_HW_CFG_BCE (0x1UL << 1) 170#define SMSC_HW_CFG_SRST (0x1UL << 0) 171 172#define SMSC_PM_CTRL_PHY_RST (0x1UL << 4) /* PHY reset */ 173 174#define SMSC_LED_GPIO_CFG_SPD_LED (0x1UL << 24) 175#define SMSC_LED_GPIO_CFG_LNK_LED (0x1UL << 20) 176#define SMSC_LED_GPIO_CFG_FDX_LED (0x1UL << 16) 177 178/* Hi watermark = 15.5Kb (~10 mtu pkts) */ 179/* low watermark = 3k (~2 mtu pkts) */ 180/* backpressure duration = ~ 350us */ 181/* Apply FC on any frame. */ 182#define AFC_CFG_DEFAULT (0x00F830A1) 183 184#define SMSC_EEPROM_CMD_BUSY (0x1UL << 31) 185#define SMSC_EEPROM_CMD_MASK (0x7UL << 28) 186#define SMSC_EEPROM_CMD_READ (0x0UL << 28) 187#define SMSC_EEPROM_CMD_WRITE (0x3UL << 28) 188#define SMSC_EEPROM_CMD_ERASE (0x5UL << 28) 189#define SMSC_EEPROM_CMD_RELOAD (0x7UL << 28) 190#define SMSC_EEPROM_CMD_TIMEOUT (0x1UL << 10) 191#define SMSC_EEPROM_CMD_ADDR_MASK 0x000001FFUL 192 193/* MAC Control and Status Register */ 194#define SMSC_MAC_CSR_RCVOWN (0x1UL << 23) /* Half duplex */ 195#define SMSC_MAC_CSR_LOOPBK (0x1UL << 21) /* Loopback */ 196#define SMSC_MAC_CSR_FDPX (0x1UL << 20) /* Full duplex */ 197#define SMSC_MAC_CSR_MCPAS (0x1UL << 19) /* Multicast mode */ 198#define SMSC_MAC_CSR_PRMS (0x1UL << 18) /* Promiscuous mode */ 199#define SMSC_MAC_CSR_INVFILT (0x1UL << 17) /* Inverse filtering */ 200#define SMSC_MAC_CSR_PASSBAD (0x1UL << 16) /* Pass on bad frames */ 201#define SMSC_MAC_CSR_HPFILT (0x1UL << 13) /* Hash filtering */ 202#define SMSC_MAC_CSR_BCAST (0x1UL << 11) /* Broadcast */ 203#define SMSC_MAC_CSR_TXEN (0x1UL << 3) /* TX enable */ 204#define SMSC_MAC_CSR_RXEN (0x1UL << 2) /* RX enable */ 205 206/* Interrupt control register */ 207#define SMSC_INTR_NTEP (0x1UL << 31) 208#define SMSC_INTR_MACRTO (0x1UL << 19) 209#define SMSC_INTR_TX_STOP (0x1UL << 17) 210#define SMSC_INTR_RX_STOP (0x1UL << 16) 211#define SMSC_INTR_PHY_INT (0x1UL << 15) 212#define SMSC_INTR_TXE (0x1UL << 14) 213#define SMSC_INTR_TDFU (0x1UL << 13) 214#define SMSC_INTR_TDFO (0x1UL << 12) 215#define SMSC_INTR_RXDF (0x1UL << 11) 216#define SMSC_INTR_GPIOS 0x000007FFUL 217 218/* Phy MII interface register */ 219#define SMSC_MII_WRITE (0x1UL << 1) 220#define SMSC_MII_READ (0x0UL << 1) 221#define SMSC_MII_BUSY (0x1UL << 0) 222 223/* H/W checksum register */ 224#define SMSC_COE_CTRL_TX_EN (0x1UL << 16) /* Tx H/W csum enable */ 225#define SMSC_COE_CTRL_RX_MODE (0x1UL << 1) 226#define SMSC_COE_CTRL_RX_EN (0x1UL << 0) /* Rx H/W csum enable */ 227 228/* Registers on the phy, accessed via MII/MDIO */ 229#define SMSC_PHY_INTR_STAT (29) 230#define SMSC_PHY_INTR_MASK (30) 231 232#define SMSC_PHY_INTR_ENERGY_ON (0x1U << 7) 233#define SMSC_PHY_INTR_ANEG_COMP (0x1U << 6) 234#define SMSC_PHY_INTR_REMOTE_FAULT (0x1U << 5) 235#define SMSC_PHY_INTR_LINK_DOWN (0x1U << 4) 236 237/* USB Vendor Requests */ 238#define SMSC_UR_WRITE_REG 0xA0 239#define SMSC_UR_READ_REG 0xA1 240#define SMSC_UR_GET_STATS 0xA2 241 242#define SMSC_CONFIG_INDEX 0 /* config number 1 */ 243#define SMSC_IFACE_IDX 0 244 245/* 246 * USB endpoints. 247 */ 248enum { 249 SMSC_BULK_DT_RD, 250 SMSC_BULK_DT_WR, 251 /* the LAN9514 device does support interrupt endpoints, however I couldn't 252 * get then to work reliably and since they are unneeded (poll the mii 253 * status) they are unused. 254 * SMSC_INTR_DT_WR, 255 * SMSC_INTR_DT_RD, 256 */ 257 SMSC_N_TRANSFER, 258}; 259 260struct smsc_softc { 261 struct usb_ether sc_ue; 262 struct mtx sc_mtx; 263 struct usb_xfer *sc_xfer[SMSC_N_TRANSFER]; 264 int sc_phyno; 265 266 /* The following stores the settings in the mac control (MAC_CSR) register */ 267 uint32_t sc_mac_csr; 268 uint32_t sc_rev_id; 269 270 uint32_t sc_flags; 271#define SMSC_FLAG_LINK 0x0001 272#define SMSC_FLAG_LAN9514 0x1000 /* LAN9514 */ 273}; 274 275#define SMSC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 276#define SMSC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 277#define SMSC_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 278 279#endif /* _IF_SMSCREG_H_ */ 280