vxgehal-ring.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright(c) 2002-2011 Exar Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification are permitted provided the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Exar Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33/*$FreeBSD: stable/11/sys/dev/vxge/vxgehal/vxgehal-ring.h 330897 2018-03-14 03:19:51Z eadler $*/ 34 35#ifndef VXGE_HAL_RING_H 36#define VXGE_HAL_RING_H 37 38__EXTERN_BEGIN_DECLS 39 40typedef u8 vxge_hal_ring_block_t[VXGE_OS_HOST_PAGE_SIZE]; 41 42#define VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET (VXGE_OS_HOST_PAGE_SIZE-8) 43#define VXGE_HAL_RING_MEMBLOCK_IDX_OFFSET (VXGE_OS_HOST_PAGE_SIZE-16) 44 45/* 46 * struct __hal_ring_rxd_priv_t - Receive descriptor HAL-private data. 47 * @dma_addr: DMA (mapped) address of _this_ descriptor. 48 * @dma_handle: DMA handle used to map the descriptor onto device. 49 * @dma_offset: Descriptor's offset in the memory block. HAL allocates 50 * descriptors in memory blocks of %VXGE_OS_HOST_PAGE_SIZE 51 * bytes. Each memblock is contiguous DMA-able memory. Each 52 * memblock contains 1 or more 4KB RxD blocks visible to the 53 * X3100 hardware. 54 * @dma_object: DMA address and handle of the memory block that contains 55 * the descriptor. This member is used only in the "checked" 56 * version of the HAL (to enforce certain assertions); 57 * otherwise it gets compiled out. 58 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 59 * @db_bytes: Number of doorbell bytes to be posted for this Rxd. This includes 60 * next RxD block pointers 61 * 62 * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA 63 * information associated with the descriptor. Note that ULD can ask HAL 64 * to allocate additional per-descriptor space for its own (ULD-specific) 65 * purposes. 66 */ 67typedef struct __hal_ring_rxd_priv_t { 68 dma_addr_t dma_addr; 69 pci_dma_h dma_handle; 70 ptrdiff_t dma_offset; 71#if defined(VXGE_DEBUG_ASSERT) 72 vxge_hal_mempool_dma_t *dma_object; 73#endif 74#if defined(VXGE_OS_MEMORY_CHECK) 75 u32 allocated; 76#endif 77 u32 db_bytes; 78} __hal_ring_rxd_priv_t; 79 80 81/* 82 * struct __hal_ring_t - Ring channel. 83 * @channel: Channel "base" of this ring, the common part of all HAL 84 * channels. 85 * @mempool: Memory pool, the pool from which descriptors get allocated. 86 * (See vxge_hal_mm.h). 87 * @config: Ring configuration, part of device configuration 88 * (see vxge_hal_device_config_t {}). 89 * @ring_length: Length of the ring 90 * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode, 91 * as per X3100 User Guide. 92 * @indicate_max_pkts: Maximum number of packets processed within a single 93 * interrupt. Can be used to limit the time spent inside hw interrupt. 94 * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per X3100 spec, 95 * 1-buffer mode descriptor is 32 byte long, etc. 96 * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor 97 * data (e.g., DMA handle for Solaris) 98 * @per_rxd_space: Per rxd space requested by ULD 99 * @rxds_per_block: Number of descriptors per hardware-defined RxD 100 * block. Depends on the (1-, 3-, 5-) buffer mode. 101 * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal 102 * usage. Not to confuse with @rxd_priv_size. 103 * @rxd_mem_avail: Available RxD memory 104 * @db_byte_count: Number of doorbell bytes to be posted 105 * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR. 106 * Used in conjunction with @indicate_max_pkts. 107 * @active_sw_lros: List of Software LRO sessions in progess 108 * @active_sw_lro_count: Number of Software LRO sessions in progess 109 * @free_sw_lros: List of Software LRO sessions free 110 * @free_sw_lro_count: Number of Software LRO sessions free 111 * @sw_lro_lock: LRO session lists' lock 112 * @callback: Channel completion callback. HAL invokes the callback when there 113 * are new completions on that channel. In many implementations 114 * the @callback executes in the hw interrupt context. 115 * @rxd_init: Channel's descriptor-initialize callback. 116 * See vxge_hal_ring_rxd_init_f {}. 117 * If not NULL, HAL invokes the callback when opening the ring. 118 * @rxd_term: Channel's descriptor-terminate callback. If not NULL, 119 * HAL invokes the callback when closing the corresponding channel. 120 * See also vxge_hal_channel_rxd_term_f {}. 121 * @stats: Statistics for ring 122 * Ring channel. 123 * 124 * Note: The structure is cache line aligned to better utilize 125 * CPU cache performance. 126 */ 127typedef struct __hal_ring_t { 128 __hal_channel_t channel; 129 vxge_hal_mempool_t *mempool; 130 vxge_hal_ring_config_t *config; 131 u32 ring_length; 132 u32 buffer_mode; 133 u32 indicate_max_pkts; 134 u32 rxd_size; 135 u32 rxd_priv_size; 136 u32 per_rxd_space; 137 u32 rxds_per_block; 138 u32 rxdblock_priv_size; 139 u32 rxd_mem_avail; 140 u32 db_byte_count; 141 u32 cmpl_cnt; 142 vxge_hal_ring_callback_f callback; 143 vxge_hal_ring_rxd_init_f rxd_init; 144 vxge_hal_ring_rxd_term_f rxd_term; 145 vxge_hal_vpath_stats_sw_ring_info_t *stats; 146} __vxge_os_attr_cacheline_aligned __hal_ring_t; 147 148#define VXGE_HAL_RING_ULD_PRIV(ring, rxdh) \ 149 ring->channel.dtr_arr[ \ 150 ((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].uld_priv 151 152#define VXGE_HAL_RING_HAL_PRIV(ring, rxdh) \ 153 ((__hal_ring_rxd_priv_t *)(ring->channel.dtr_arr[ \ 154 ((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].hal_priv)) 155 156#define VXGE_HAL_RING_POST_DOORBELL(vph, ringh) \ 157{ \ 158 if (((__hal_ring_t *)(ringh))->config->post_mode == \ 159 VXGE_HAL_RING_POST_MODE_DOORBELL) { \ 160 vxge_hal_ring_rxd_post_post_db(vph); \ 161 } \ 162} 163 164#define VXGE_HAL_RING_RXD_INDEX(rxdp) \ 165 (u32)((vxge_hal_ring_rxd_5_t *)rxdp)->host_control 166 167/* ========================== RING PRIVATE API ============================ */ 168 169u64 170__hal_ring_first_block_address_get( 171 vxge_hal_ring_h ringh); 172 173vxge_hal_status_e 174__hal_ring_create( 175 vxge_hal_vpath_h vpath_handle, 176 vxge_hal_ring_attr_t *attr); 177 178void 179__hal_ring_abort( 180 vxge_hal_ring_h ringh, 181 vxge_hal_reopen_e reopen); 182 183vxge_hal_status_e 184__hal_ring_reset( 185 vxge_hal_ring_h ringh); 186 187void 188__hal_ring_delete( 189 vxge_hal_vpath_h vpath_handle); 190 191vxge_hal_status_e 192vxge_hal_ring_initial_replenish( 193 __hal_ring_t *ring, 194 vxge_hal_reopen_e reopen); 195 196vxge_hal_status_e 197__hal_ring_frame_length_set( 198 __hal_virtualpath_t *vpath, 199 u32 new_frmlen); 200 201__EXTERN_END_DECLS 202 203#endif /* VXGE_HAL_RING_H */ 204