glxiic.c revision 331722
1/*- 2 * Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/11/sys/dev/glxiic/glxiic.c 331722 2018-03-29 02:50:57Z eadler $"); 28/* 29 * AMD Geode LX CS5536 System Management Bus controller. 30 * 31 * Although AMD refers to this device as an SMBus controller, it 32 * really is an I2C controller (It lacks SMBus ALERT# and Alert 33 * Response support). 34 * 35 * The driver is implemented as an interrupt-driven state machine, 36 * supporting both master and slave mode. 37 */ 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/lock.h> 44#include <sys/mutex.h> 45#include <sys/sysctl.h> 46#ifdef GLXIIC_DEBUG 47#include <sys/syslog.h> 48#endif 49 50#include <dev/pci/pcireg.h> 51#include <dev/pci/pcivar.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <dev/iicbus/iiconf.h> 58#include <dev/iicbus/iicbus.h> 59 60#include "iicbus_if.h" 61 62/* CS5536 PCI-ISA ID. */ 63#define GLXIIC_CS5536_DEV_ID 0x20901022 64 65/* MSRs. */ 66#define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021 67 68/* Bus speeds. */ 69#define GLXIIC_SLOW 0x0258 /* 10 kHz. */ 70#define GLXIIC_FAST 0x0078 /* 50 kHz. */ 71#define GLXIIC_FASTEST 0x003c /* 100 kHz. */ 72 73/* Default bus activity timeout in milliseconds. */ 74#define GLXIIC_DEFAULT_TIMEOUT 35 75 76/* GPIO register offsets. */ 77#define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10 78#define GLXIIC_GPIOL_IN_AUX1_SEL 0x34 79 80/* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */ 81#define GLXIIC_GPIO_14_15_ENABLE 0x0000c000 82#define GLXIIC_GPIO_14_15_DISABLE 0xc0000000 83 84/* SMB register offsets. */ 85#define GLXIIC_SMB_SDA 0x00 86#define GLXIIC_SMB_STS 0x01 87#define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7) 88#define GLXIIC_SMB_STS_SDAST_BIT (1 << 6) 89#define GLXIIC_SMB_STS_BER_BIT (1 << 5) 90#define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4) 91#define GLXIIC_SMB_STS_STASTR_BIT (1 << 3) 92#define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2) 93#define GLXIIC_SMB_STS_MASTER_BIT (1 << 1) 94#define GLXIIC_SMB_STS_XMIT_BIT (1 << 0) 95#define GLXIIC_SMB_CTRL_STS 0x02 96#define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5) 97#define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4) 98#define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3) 99#define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2) 100#define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1) 101#define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0) 102#define GLXIIC_SMB_CTRL1 0x03 103#define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7) 104#define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6) 105#define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5) 106#define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4) 107#define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2) 108#define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1) 109#define GLXIIC_SMB_CTRL1_START_BIT (1 << 0) 110#define GLXIIC_SMB_ADDR 0x04 111#define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7) 112#define GLXIIC_SMB_CTRL2 0x05 113#define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0) 114#define GLXIIC_SMB_CTRL3 0x06 115 116typedef enum { 117 GLXIIC_STATE_IDLE, 118 GLXIIC_STATE_SLAVE_TX, 119 GLXIIC_STATE_SLAVE_RX, 120 GLXIIC_STATE_MASTER_ADDR, 121 GLXIIC_STATE_MASTER_TX, 122 GLXIIC_STATE_MASTER_RX, 123 GLXIIC_STATE_MASTER_STOP, 124 GLXIIC_STATE_MAX, 125} glxiic_state_t; 126 127struct glxiic_softc { 128 device_t dev; /* Myself. */ 129 device_t iicbus; /* IIC bus. */ 130 struct mtx mtx; /* Lock. */ 131 glxiic_state_t state; /* Driver state. */ 132 struct callout callout; /* Driver state timeout callout. */ 133 int timeout; /* Driver state timeout (ms). */ 134 135 int smb_rid; /* SMB controller resource ID. */ 136 struct resource *smb_res; /* SMB controller resource. */ 137 int gpio_rid; /* GPIO resource ID. */ 138 struct resource *gpio_res; /* GPIO resource. */ 139 140 int irq_rid; /* IRQ resource ID. */ 141 struct resource *irq_res; /* IRQ resource. */ 142 void *irq_handler; /* IRQ handler cookie. */ 143 int old_irq; /* IRQ mapped by board firmware. */ 144 145 struct iic_msg *msg; /* Current master mode message. */ 146 uint32_t nmsgs; /* Number of messages remaining. */ 147 uint8_t *data; /* Current master mode data byte. */ 148 uint16_t ndata; /* Number of data bytes remaining. */ 149 int error; /* Last master mode error. */ 150 151 uint8_t addr; /* Own address. */ 152 uint16_t sclfrq; /* Bus frequency. */ 153}; 154 155#ifdef GLXIIC_DEBUG 156#define GLXIIC_DEBUG_LOG(fmt, args...) \ 157 log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args) 158#else 159#define GLXIIC_DEBUG_LOG(fmt, args...) 160#endif 161 162#define GLXIIC_SCLFRQ(n) ((n << 1)) 163#define GLXIIC_SMBADDR(n) ((n >> 1)) 164#define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16)) 165#define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf) 166 167#define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx) 168#define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx) 169#define GLXIIC_LOCK_INIT(_sc) \ 170 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF) 171#define GLXIIC_SLEEP(_sc) \ 172 mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0) 173#define GLXIIC_WAKEUP(_sc) wakeup(_sc); 174#define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 175#define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 176 177typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc, 178 uint8_t status); 179 180static glxiic_state_callback_t glxiic_state_idle_callback; 181static glxiic_state_callback_t glxiic_state_slave_tx_callback; 182static glxiic_state_callback_t glxiic_state_slave_rx_callback; 183static glxiic_state_callback_t glxiic_state_master_addr_callback; 184static glxiic_state_callback_t glxiic_state_master_tx_callback; 185static glxiic_state_callback_t glxiic_state_master_rx_callback; 186static glxiic_state_callback_t glxiic_state_master_stop_callback; 187 188struct glxiic_state_table_entry { 189 glxiic_state_callback_t *callback; 190 boolean_t master; 191}; 192typedef struct glxiic_state_table_entry glxiic_state_table_entry_t; 193 194static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = { 195 [GLXIIC_STATE_IDLE] = { 196 .callback = &glxiic_state_idle_callback, 197 .master = FALSE, 198 }, 199 200 [GLXIIC_STATE_SLAVE_TX] = { 201 .callback = &glxiic_state_slave_tx_callback, 202 .master = FALSE, 203 }, 204 205 [GLXIIC_STATE_SLAVE_RX] = { 206 .callback = &glxiic_state_slave_rx_callback, 207 .master = FALSE, 208 }, 209 210 [GLXIIC_STATE_MASTER_ADDR] = { 211 .callback = &glxiic_state_master_addr_callback, 212 .master = TRUE, 213 }, 214 215 [GLXIIC_STATE_MASTER_TX] = { 216 .callback = &glxiic_state_master_tx_callback, 217 .master = TRUE, 218 }, 219 220 [GLXIIC_STATE_MASTER_RX] = { 221 .callback = &glxiic_state_master_rx_callback, 222 .master = TRUE, 223 }, 224 225 [GLXIIC_STATE_MASTER_STOP] = { 226 .callback = &glxiic_state_master_stop_callback, 227 .master = TRUE, 228 }, 229}; 230 231static void glxiic_identify(driver_t *driver, device_t parent); 232static int glxiic_probe(device_t dev); 233static int glxiic_attach(device_t dev); 234static int glxiic_detach(device_t dev); 235 236static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc); 237static void glxiic_stop_locked(struct glxiic_softc *sc); 238static void glxiic_timeout(void *arg); 239static void glxiic_start_timeout_locked(struct glxiic_softc *sc); 240static void glxiic_set_state_locked(struct glxiic_softc *sc, 241 glxiic_state_t state); 242static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc, 243 uint8_t status); 244static void glxiic_intr(void *arg); 245 246static int glxiic_reset(device_t dev, u_char speed, u_char addr, 247 u_char *oldaddr); 248static int glxiic_transfer(device_t dev, struct iic_msg *msgs, 249 uint32_t nmsgs); 250 251static void glxiic_smb_map_interrupt(int irq); 252static void glxiic_gpio_enable(struct glxiic_softc *sc); 253static void glxiic_gpio_disable(struct glxiic_softc *sc); 254static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, 255 uint8_t addr); 256static void glxiic_smb_disable(struct glxiic_softc *sc); 257 258static device_method_t glxiic_methods[] = { 259 DEVMETHOD(device_identify, glxiic_identify), 260 DEVMETHOD(device_probe, glxiic_probe), 261 DEVMETHOD(device_attach, glxiic_attach), 262 DEVMETHOD(device_detach, glxiic_detach), 263 264 DEVMETHOD(iicbus_reset, glxiic_reset), 265 DEVMETHOD(iicbus_transfer, glxiic_transfer), 266 DEVMETHOD(iicbus_callback, iicbus_null_callback), 267 268 { 0, 0 } 269}; 270 271static driver_t glxiic_driver = { 272 "glxiic", 273 glxiic_methods, 274 sizeof(struct glxiic_softc), 275}; 276 277static devclass_t glxiic_devclass; 278 279DRIVER_MODULE(glxiic, isab, glxiic_driver, glxiic_devclass, 0, 0); 280DRIVER_MODULE(iicbus, glxiic, iicbus_driver, iicbus_devclass, 0, 0); 281MODULE_DEPEND(glxiic, iicbus, 1, 1, 1); 282 283static void 284glxiic_identify(driver_t *driver, device_t parent) 285{ 286 287 /* Prevent child from being added more than once. */ 288 if (device_find_child(parent, driver->name, -1) != NULL) 289 return; 290 291 if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) { 292 if (device_add_child(parent, driver->name, -1) == NULL) 293 device_printf(parent, "Could not add glxiic child\n"); 294 } 295} 296 297static int 298glxiic_probe(device_t dev) 299{ 300 301 if (resource_disabled("glxiic", device_get_unit(dev))) 302 return (ENXIO); 303 304 device_set_desc(dev, "AMD Geode CS5536 SMBus controller"); 305 306 return (BUS_PROBE_DEFAULT); 307} 308 309static int 310glxiic_attach(device_t dev) 311{ 312 struct glxiic_softc *sc; 313 struct sysctl_ctx_list *ctx; 314 struct sysctl_oid *tree; 315 int error, irq, unit; 316 uint32_t irq_map; 317 318 sc = device_get_softc(dev); 319 sc->dev = dev; 320 sc->state = GLXIIC_STATE_IDLE; 321 error = 0; 322 323 GLXIIC_LOCK_INIT(sc); 324 callout_init_mtx(&sc->callout, &sc->mtx, 0); 325 326 sc->smb_rid = PCIR_BAR(0); 327 sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid, 328 RF_ACTIVE); 329 if (sc->smb_res == NULL) { 330 device_printf(dev, "Could not allocate SMBus I/O port\n"); 331 error = ENXIO; 332 goto out; 333 } 334 335 sc->gpio_rid = PCIR_BAR(1); 336 sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 337 &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE); 338 if (sc->gpio_res == NULL) { 339 device_printf(dev, "Could not allocate GPIO I/O port\n"); 340 error = ENXIO; 341 goto out; 342 } 343 344 /* Ensure the controller is not enabled by firmware. */ 345 glxiic_smb_disable(sc); 346 347 /* Read the existing IRQ map. */ 348 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 349 sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 350 351 unit = device_get_unit(dev); 352 if (resource_int_value("glxiic", unit, "irq", &irq) == 0) { 353 if (irq < 1 || irq > 15) { 354 device_printf(dev, "Bad value %d for glxiic.%d.irq\n", 355 irq, unit); 356 error = ENXIO; 357 goto out; 358 } 359 360 if (bootverbose) 361 device_printf(dev, "Using irq %d set by hint\n", irq); 362 } else if (sc->old_irq != 0) { 363 if (bootverbose) 364 device_printf(dev, "Using irq %d set by firmware\n", 365 irq); 366 irq = sc->old_irq; 367 } else { 368 device_printf(dev, "No irq mapped by firmware"); 369 printf(" and no glxiic.%d.irq hint provided\n", unit); 370 error = ENXIO; 371 goto out; 372 } 373 374 /* Map the SMBus interrupt to the requested legacy IRQ. */ 375 glxiic_smb_map_interrupt(irq); 376 377 sc->irq_rid = 0; 378 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, 379 irq, irq, 1, RF_SHAREABLE | RF_ACTIVE); 380 if (sc->irq_res == NULL) { 381 device_printf(dev, "Could not allocate IRQ %d\n", irq); 382 error = ENXIO; 383 goto out; 384 } 385 386 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 387 NULL, glxiic_intr, sc, &(sc->irq_handler)); 388 if (error != 0) { 389 device_printf(dev, "Could not setup IRQ handler\n"); 390 error = ENXIO; 391 goto out; 392 } 393 394 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 395 device_printf(dev, "Could not allocate iicbus instance\n"); 396 error = ENXIO; 397 goto out; 398 } 399 400 ctx = device_get_sysctl_ctx(dev); 401 tree = device_get_sysctl_tree(dev); 402 403 sc->timeout = GLXIIC_DEFAULT_TIMEOUT; 404 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 405 "timeout", CTLFLAG_RWTUN, &sc->timeout, 0, 406 "activity timeout in ms"); 407 408 glxiic_gpio_enable(sc); 409 glxiic_smb_enable(sc, IIC_FASTEST, 0); 410 411 /* Probe and attach the iicbus when interrupts are available. */ 412 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); 413 error = 0; 414 415out: 416 if (error != 0) { 417 callout_drain(&sc->callout); 418 419 if (sc->iicbus != NULL) 420 device_delete_child(dev, sc->iicbus); 421 if (sc->smb_res != NULL) { 422 glxiic_smb_disable(sc); 423 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 424 sc->smb_res); 425 } 426 if (sc->gpio_res != NULL) { 427 glxiic_gpio_disable(sc); 428 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 429 sc->gpio_res); 430 } 431 if (sc->irq_handler != NULL) 432 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 433 if (sc->irq_res != NULL) 434 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 435 sc->irq_res); 436 437 /* Restore the old SMBus interrupt mapping. */ 438 glxiic_smb_map_interrupt(sc->old_irq); 439 440 GLXIIC_LOCK_DESTROY(sc); 441 } 442 443 return (error); 444} 445 446static int 447glxiic_detach(device_t dev) 448{ 449 struct glxiic_softc *sc; 450 int error; 451 452 sc = device_get_softc(dev); 453 454 error = bus_generic_detach(dev); 455 if (error != 0) 456 goto out; 457 if (sc->iicbus != NULL) 458 error = device_delete_child(dev, sc->iicbus); 459 460out: 461 callout_drain(&sc->callout); 462 463 if (sc->smb_res != NULL) { 464 glxiic_smb_disable(sc); 465 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 466 sc->smb_res); 467 } 468 if (sc->gpio_res != NULL) { 469 glxiic_gpio_disable(sc); 470 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 471 sc->gpio_res); 472 } 473 if (sc->irq_handler != NULL) 474 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 475 if (sc->irq_res != NULL) 476 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 477 sc->irq_res); 478 479 /* Restore the old SMBus interrupt mapping. */ 480 glxiic_smb_map_interrupt(sc->old_irq); 481 482 GLXIIC_LOCK_DESTROY(sc); 483 484 return (error); 485} 486 487static uint8_t 488glxiic_read_status_locked(struct glxiic_softc *sc) 489{ 490 uint8_t status; 491 492 GLXIIC_ASSERT_LOCKED(sc); 493 494 status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS); 495 496 /* Clear all status flags except SDAST and STASTR after reading. */ 497 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT | 498 GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT | 499 GLXIIC_SMB_STS_NMATCH_BIT)); 500 501 return (status); 502} 503 504static void 505glxiic_stop_locked(struct glxiic_softc *sc) 506{ 507 uint8_t status, ctrl1; 508 509 GLXIIC_ASSERT_LOCKED(sc); 510 511 status = glxiic_read_status_locked(sc); 512 513 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 514 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 515 ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT); 516 517 /* 518 * Perform a dummy read of SDA in master receive mode to clear 519 * SDAST if set. 520 */ 521 if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 && 522 (status & GLXIIC_SMB_STS_SDAST_BIT) != 0) 523 bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 524 525 /* Check stall after start bit and clear if needed */ 526 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 527 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 528 GLXIIC_SMB_STS_STASTR_BIT); 529 } 530} 531 532static void 533glxiic_timeout(void *arg) 534{ 535 struct glxiic_softc *sc; 536 uint8_t error; 537 538 sc = (struct glxiic_softc *)arg; 539 540 GLXIIC_DEBUG_LOG("timeout in state %d", sc->state); 541 542 if (glxiic_state_table[sc->state].master) { 543 sc->error = IIC_ETIMEOUT; 544 GLXIIC_WAKEUP(sc); 545 } else { 546 error = IIC_ETIMEOUT; 547 iicbus_intr(sc->iicbus, INTR_ERROR, &error); 548 } 549 550 glxiic_smb_disable(sc); 551 glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr); 552 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 553} 554 555static void 556glxiic_start_timeout_locked(struct glxiic_softc *sc) 557{ 558 559 GLXIIC_ASSERT_LOCKED(sc); 560 561 callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0, 562 glxiic_timeout, sc, 0); 563} 564 565static void 566glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state) 567{ 568 569 GLXIIC_ASSERT_LOCKED(sc); 570 571 if (state == GLXIIC_STATE_IDLE) 572 callout_stop(&sc->callout); 573 else if (sc->timeout > 0) 574 glxiic_start_timeout_locked(sc); 575 576 sc->state = state; 577} 578 579static int 580glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status) 581{ 582 uint8_t ctrl_sts, addr; 583 584 GLXIIC_ASSERT_LOCKED(sc); 585 586 ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS); 587 588 if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) { 589 if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) { 590 addr = sc->addr | LSB; 591 glxiic_set_state_locked(sc, 592 GLXIIC_STATE_SLAVE_TX); 593 } else { 594 addr = sc->addr & ~LSB; 595 glxiic_set_state_locked(sc, 596 GLXIIC_STATE_SLAVE_RX); 597 } 598 iicbus_intr(sc->iicbus, INTR_START, &addr); 599 } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) { 600 addr = 0; 601 glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX); 602 iicbus_intr(sc->iicbus, INTR_GENERAL, &addr); 603 } else { 604 GLXIIC_DEBUG_LOG("unknown slave match"); 605 return (IIC_ESTATUS); 606 } 607 608 return (IIC_NOERR); 609} 610 611static int 612glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status) 613{ 614 615 GLXIIC_ASSERT_LOCKED(sc); 616 617 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 618 GLXIIC_DEBUG_LOG("bus error in idle"); 619 return (IIC_EBUSERR); 620 } 621 622 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 623 return (glxiic_handle_slave_match_locked(sc, status)); 624 } 625 626 return (IIC_NOERR); 627} 628 629static int 630glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status) 631{ 632 uint8_t data; 633 634 GLXIIC_ASSERT_LOCKED(sc); 635 636 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 637 GLXIIC_DEBUG_LOG("bus error in slave tx"); 638 return (IIC_EBUSERR); 639 } 640 641 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 642 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 643 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 644 return (IIC_NOERR); 645 } 646 647 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 648 iicbus_intr(sc->iicbus, INTR_NOACK, NULL); 649 return (IIC_NOERR); 650 } 651 652 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 653 /* Handle repeated start in slave mode. */ 654 return (glxiic_handle_slave_match_locked(sc, status)); 655 } 656 657 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 658 GLXIIC_DEBUG_LOG("not awaiting data in slave tx"); 659 return (IIC_ESTATUS); 660 } 661 662 iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data); 663 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data); 664 665 glxiic_start_timeout_locked(sc); 666 667 return (IIC_NOERR); 668} 669 670static int 671glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status) 672{ 673 uint8_t data; 674 675 GLXIIC_ASSERT_LOCKED(sc); 676 677 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 678 GLXIIC_DEBUG_LOG("bus error in slave rx"); 679 return (IIC_EBUSERR); 680 } 681 682 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 683 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 684 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 685 return (IIC_NOERR); 686 } 687 688 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 689 /* Handle repeated start in slave mode. */ 690 return (glxiic_handle_slave_match_locked(sc, status)); 691 } 692 693 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 694 GLXIIC_DEBUG_LOG("no pending data in slave rx"); 695 return (IIC_ESTATUS); 696 } 697 698 data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 699 iicbus_intr(sc->iicbus, INTR_RECEIVE, &data); 700 701 glxiic_start_timeout_locked(sc); 702 703 return (IIC_NOERR); 704} 705 706static int 707glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status) 708{ 709 uint8_t slave; 710 uint8_t ctrl1; 711 712 GLXIIC_ASSERT_LOCKED(sc); 713 714 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 715 GLXIIC_DEBUG_LOG("bus error after master start"); 716 return (IIC_EBUSERR); 717 } 718 719 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 720 GLXIIC_DEBUG_LOG("not bus master after master start"); 721 return (IIC_ESTATUS); 722 } 723 724 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 725 GLXIIC_DEBUG_LOG("not awaiting address in master addr"); 726 return (IIC_ESTATUS); 727 } 728 729 if ((sc->msg->flags & IIC_M_RD) != 0) { 730 slave = sc->msg->slave | LSB; 731 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX); 732 } else { 733 slave = sc->msg->slave & ~LSB; 734 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX); 735 } 736 737 sc->data = sc->msg->buf; 738 sc->ndata = sc->msg->len; 739 740 /* Handle address-only transfer. */ 741 if (sc->ndata == 0) 742 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 743 744 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave); 745 746 if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) { 747 /* Last byte from slave, set NACK. */ 748 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 749 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 750 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); 751 } 752 753 return (IIC_NOERR); 754} 755 756static int 757glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status) 758{ 759 760 GLXIIC_ASSERT_LOCKED(sc); 761 762 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 763 GLXIIC_DEBUG_LOG("bus error in master tx"); 764 return (IIC_EBUSERR); 765 } 766 767 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 768 GLXIIC_DEBUG_LOG("not bus master in master tx"); 769 return (IIC_ESTATUS); 770 } 771 772 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 773 GLXIIC_DEBUG_LOG("slave nack in master tx"); 774 return (IIC_ENOACK); 775 } 776 777 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 778 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 779 GLXIIC_SMB_STS_STASTR_BIT); 780 } 781 782 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 783 GLXIIC_DEBUG_LOG("not awaiting data in master tx"); 784 return (IIC_ESTATUS); 785 } 786 787 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++); 788 if (--sc->ndata == 0) 789 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 790 else 791 glxiic_start_timeout_locked(sc); 792 793 return (IIC_NOERR); 794} 795 796static int 797glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status) 798{ 799 uint8_t ctrl1; 800 801 GLXIIC_ASSERT_LOCKED(sc); 802 803 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 804 GLXIIC_DEBUG_LOG("bus error in master rx"); 805 return (IIC_EBUSERR); 806 } 807 808 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 809 GLXIIC_DEBUG_LOG("not bus master in master rx"); 810 return (IIC_ESTATUS); 811 } 812 813 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 814 GLXIIC_DEBUG_LOG("slave nack in rx"); 815 return (IIC_ENOACK); 816 } 817 818 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 819 /* Bus is stalled, clear and wait for data. */ 820 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 821 GLXIIC_SMB_STS_STASTR_BIT); 822 return (IIC_NOERR); 823 } 824 825 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 826 GLXIIC_DEBUG_LOG("no pending data in master rx"); 827 return (IIC_ESTATUS); 828 } 829 830 *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 831 if (--sc->ndata == 0) { 832 /* Proceed with stop on reading last byte. */ 833 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 834 return (glxiic_state_table[sc->state].callback(sc, status)); 835 } 836 837 if (sc->ndata == 1) { 838 /* Last byte from slave, set NACK. */ 839 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 840 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 841 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); 842 } 843 844 glxiic_start_timeout_locked(sc); 845 846 return (IIC_NOERR); 847} 848 849static int 850glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status) 851{ 852 uint8_t ctrl1; 853 854 GLXIIC_ASSERT_LOCKED(sc); 855 856 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 857 GLXIIC_DEBUG_LOG("bus error in master stop"); 858 return (IIC_EBUSERR); 859 } 860 861 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 862 GLXIIC_DEBUG_LOG("not bus master in master stop"); 863 return (IIC_ESTATUS); 864 } 865 866 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 867 GLXIIC_DEBUG_LOG("slave nack in master stop"); 868 return (IIC_ENOACK); 869 } 870 871 if (--sc->nmsgs > 0) { 872 /* Start transfer of next message. */ 873 if ((sc->msg->flags & IIC_M_NOSTOP) == 0) { 874 glxiic_stop_locked(sc); 875 } 876 877 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 878 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 879 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 880 881 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 882 sc->msg++; 883 } else { 884 /* Last message. */ 885 glxiic_stop_locked(sc); 886 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 887 sc->error = IIC_NOERR; 888 GLXIIC_WAKEUP(sc); 889 } 890 891 return (IIC_NOERR); 892} 893 894static void 895glxiic_intr(void *arg) 896{ 897 struct glxiic_softc *sc; 898 int error; 899 uint8_t status, data; 900 901 sc = (struct glxiic_softc *)arg; 902 903 GLXIIC_LOCK(sc); 904 905 status = glxiic_read_status_locked(sc); 906 907 /* Check if this interrupt originated from the SMBus. */ 908 if ((status & 909 ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) { 910 911 error = glxiic_state_table[sc->state].callback(sc, status); 912 913 if (error != IIC_NOERR) { 914 if (glxiic_state_table[sc->state].master) { 915 glxiic_stop_locked(sc); 916 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 917 sc->error = error; 918 GLXIIC_WAKEUP(sc); 919 } else { 920 data = error & 0xff; 921 iicbus_intr(sc->iicbus, INTR_ERROR, &data); 922 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 923 } 924 } 925 } 926 927 GLXIIC_UNLOCK(sc); 928} 929 930static int 931glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 932{ 933 struct glxiic_softc *sc; 934 935 sc = device_get_softc(dev); 936 937 GLXIIC_LOCK(sc); 938 939 if (oldaddr != NULL) 940 *oldaddr = sc->addr; 941 sc->addr = addr; 942 943 /* A disable/enable cycle resets the controller. */ 944 glxiic_smb_disable(sc); 945 glxiic_smb_enable(sc, speed, addr); 946 947 if (glxiic_state_table[sc->state].master) { 948 sc->error = IIC_ESTATUS; 949 GLXIIC_WAKEUP(sc); 950 } 951 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 952 953 GLXIIC_UNLOCK(sc); 954 955 return (IIC_NOERR); 956} 957 958static int 959glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 960{ 961 struct glxiic_softc *sc; 962 int error; 963 uint8_t ctrl1; 964 965 sc = device_get_softc(dev); 966 967 GLXIIC_LOCK(sc); 968 969 if (sc->state != GLXIIC_STATE_IDLE) { 970 error = IIC_EBUSBSY; 971 goto out; 972 } 973 974 sc->msg = msgs; 975 sc->nmsgs = nmsgs; 976 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 977 978 /* Set start bit and let glxiic_intr() handle the transfer. */ 979 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 980 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 981 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 982 983 GLXIIC_SLEEP(sc); 984 error = sc->error; 985out: 986 GLXIIC_UNLOCK(sc); 987 988 return (error); 989} 990 991static void 992glxiic_smb_map_interrupt(int irq) 993{ 994 uint32_t irq_map; 995 int old_irq; 996 997 /* Protect the read-modify-write operation. */ 998 critical_enter(); 999 1000 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 1001 old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 1002 1003 if (irq != old_irq) { 1004 irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq); 1005 irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq); 1006 wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map); 1007 } 1008 1009 critical_exit(); 1010} 1011 1012static void 1013glxiic_gpio_enable(struct glxiic_softc *sc) 1014{ 1015 1016 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1017 GLXIIC_GPIO_14_15_ENABLE); 1018 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1019 GLXIIC_GPIO_14_15_ENABLE); 1020} 1021 1022static void 1023glxiic_gpio_disable(struct glxiic_softc *sc) 1024{ 1025 1026 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1027 GLXIIC_GPIO_14_15_DISABLE); 1028 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1029 GLXIIC_GPIO_14_15_DISABLE); 1030} 1031 1032static void 1033glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr) 1034{ 1035 uint8_t ctrl1; 1036 1037 ctrl1 = 0; 1038 1039 switch (speed) { 1040 case IIC_SLOW: 1041 sc->sclfrq = GLXIIC_SLOW; 1042 break; 1043 case IIC_FAST: 1044 sc->sclfrq = GLXIIC_FAST; 1045 break; 1046 case IIC_FASTEST: 1047 sc->sclfrq = GLXIIC_FASTEST; 1048 break; 1049 case IIC_UNKNOWN: 1050 default: 1051 /* Reuse last frequency. */ 1052 break; 1053 } 1054 1055 /* Set bus speed and enable controller. */ 1056 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1057 GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT); 1058 1059 if (addr != 0) { 1060 /* Enable new match and global call match interrupts. */ 1061 ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT | 1062 GLXIIC_SMB_CTRL1_GCMEN_BIT; 1063 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 1064 GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr)); 1065 } else { 1066 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0); 1067 } 1068 1069 /* Enable stall after start and interrupt. */ 1070 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 1071 ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT); 1072} 1073 1074static void 1075glxiic_smb_disable(struct glxiic_softc *sc) 1076{ 1077 uint16_t sclfrq; 1078 1079 sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2); 1080 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1081 sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT); 1082} 1083