sibareg.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007 Bruce M. Simpson. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/11/sys/dev/siba/sibareg.h 330897 2018-03-14 03:19:51Z eadler $ 29 */ 30 31/* 32 * TODO: sprom 33 * TODO: implement dma translation bits (if needed for system bus) 34 */ 35 36#ifndef _SIBA_SIBAREG_H_ 37#define _SIBA_SIBAREG_H_ 38 39#define PCI_DEVICE_ID_BCM4401 0x4401 40#define PCI_DEVICE_ID_BCM4401B0 0x4402 41#define PCI_DEVICE_ID_BCM4401B1 0x170c 42#define SIBA_PCIR_BAR PCIR_BAR(0) 43#define SIBA_CCID_BCM4710 0x4710 44#define SIBA_CCID_BCM4704 0x4704 45#define SIBA_CCID_SENTRY5 0x5365 46 47/* 48 * ChipCommon registers. 49 */ 50#define SIBA_CC_CHIPID 0x0000 51#define SIBA_CC_IDMASK 0x0000ffff 52#define SIBA_CC_ID(id) (id & SIBA_CC_IDMASK) 53#define SIBA_CC_REVMASK 0x000f0000 54#define SIBA_CC_REVSHIFT 16 55#define SIBA_CC_REV(id) \ 56 ((id & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT) 57#define SIBA_CC_PKGMASK 0x00F00000 58#define SIBA_CC_PKGSHIFT 20 59#define SIBA_CC_PKG(id) \ 60 ((id & SIBA_CC_PKGMASK) >> SIBA_CC_PKGSHIFT) 61#define SIBA_CC_NCORESMASK 0x0F000000 62#define SIBA_CC_NCORESSHIFT 24 63#define SIBA_CC_NCORES(id) \ 64 ((id & SIBA_CC_NCORESMASK) >> SIBA_CC_NCORESSHIFT) 65#define SIBA_CC_CAPS 0x0004 66#define SIBA_CC_CAPS_PWCTL 0x00040000 67#define SIBA_CC_CAPS_PMU 0x10000000 /* PMU (rev >= 20) */ 68#define SIBA_CC_CHIPCTL 0x0028 /* rev >= 11 */ 69#define SIBA_CC_CHIPSTAT 0x002C /* rev >= 11 */ 70#define SIBA_CC_BCAST_ADDR 0x0050 /* Broadcast Address */ 71#define SIBA_CC_BCAST_DATA 0x0054 /* Broadcast Data */ 72#define SIBA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ 73#define SIBA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ 74#define SIBA_CC_CLKSLOW 0x00b8 /* 6 <= Rev <= 9 only */ 75#define SIBA_CC_CLKSLOW_SRC 0x00000007 76#define SIBA_CC_CLKSLOW_SRC_CRYSTAL 0x00000001 77#define SIBA_CC_CLKSLOW_FSLOW 0x00000800 78#define SIBA_CC_CLKSLOW_IPLL 0x00001000 79#define SIBA_CC_CLKSLOW_ENXTAL 0x00002000 80#define SIBA_CC_CLKSYSCTL 0x00C0 /* Rev >= 3 only */ 81#define SIBA_CC_CLKCTLSTATUS 0x01e0 82#define SIBA_CC_CLKCTLSTATUS_HT 0x00010000 83#define SIBA_CC_UART0 0x0300 /* offset of UART0 */ 84#define SIBA_CC_UART1 0x0400 /* offset of UART1 */ 85#define SIBA_CC_PMUCTL 0x0600 /* PMU control */ 86#define SIBA_CC_PMUCTL_PLL_UPD 0x00000400 87#define SIBA_CC_PMUCTL_ILP 0xffff0000 /* mask */ 88#define SIBA_CC_PMUCTL_NOILP 0x00000200 89#define SIBA_CC_PMUCTL_XF 0x0000007c /* crystal freq */ 90#define SIBA_CC_PMUCTL_XF_VAL(id) ((id & 0x0000007c) >> 2) 91#define SIBA_CC_PMUCAPS 0x0604 92#define SIBA_CC_PMUCAPS_REV 0x000000ff 93#define SIBA_CC_PMU_MINRES 0x0618 94#define SIBA_CC_PMU_MAXRES 0x061c 95#define SIBA_CC_PMU_TABSEL 0x0620 96#define SIBA_CC_PMU_DEPMSK 0x0624 97#define SIBA_CC_PMU_UPDNTM 0x0628 98#define SIBA_CC_CHIPCTL_ADDR 0x0650 99#define SIBA_CC_CHIPCTL_DATA 0x0654 100#define SIBA_CC_REGCTL_ADDR 0x0658 101#define SIBA_CC_REGCTL_DATA 0x065c 102#define SIBA_CC_PLLCTL_ADDR 0x0660 103#define SIBA_CC_PLLCTL_DATA 0x0664 104 105#define SIBA_CC_PMU0_PLL0 0 106#define SIBA_CC_PMU0_PLL0_PDIV_MSK 0x00000001 107#define SIBA_CC_PMU0_PLL0_PDIV_FREQ 25000 108#define SIBA_CC_PMU0_PLL1 1 109#define SIBA_CC_PMU0_PLL1_IMSK 0xf0000000 110#define SIBA_CC_PMU0_PLL1_FMSK 0x0fffff00 111#define SIBA_CC_PMU0_PLL1_STOPMOD 0x00000040 112#define SIBA_CC_PMU0_PLL2 2 113#define SIBA_CC_PMU0_PLL2_IMSKHI 0x0000000f 114#define SIBA_CC_PMU1_PLL0 0 115#define SIBA_CC_PMU1_PLL0_P1DIV 0x00f00000 116#define SIBA_CC_PMU1_PLL0_P2DIV 0x0f000000 117#define SIBA_CC_PMU1_PLL1 1 118#define SIBA_CC_PMU1_PLL2 2 119#define SIBA_CC_PMU1_PLL2_NDIVMODE 0x000e0000 120#define SIBA_CC_PMU1_PLL2_NDIVINT 0x1ff00000 121#define SIBA_CC_PMU1_PLL3 3 122#define SIBA_CC_PMU1_PLL3_NDIVFRAC 0x00ffffff 123#define SIBA_CC_PMU1_PLL4 4 124#define SIBA_CC_PMU1_PLL5 5 125#define SIBA_CC_PMU1_PLL5_CLKDRV 0xffffff00 126 127#define SIBA_CC_PMU0_DEFAULT_XTALFREQ 20000 128#define SIBA_CC_PMU1_DEFAULT_FREQ 15360 129 130#define SIBA_CC_PMU1_PLLTAB_ENTRY \ 131{ \ 132 { 12000, 1, 3, 22, 0x9, 0xffffef }, \ 133 { 13000, 2, 1, 6, 0xb, 0x483483 }, \ 134 { 14400, 3, 1, 10, 0xa, 0x1c71c7 }, \ 135 { 15360, 4, 1, 5, 0xb, 0x755555 }, \ 136 { 16200, 5, 1, 10, 0x5, 0x6e9e06 }, \ 137 { 16800, 6, 1, 10, 0x5, 0x3cf3cf }, \ 138 { 19200, 7, 1, 9, 0x5, 0x17b425 }, \ 139 { 19800, 8, 1, 11, 0x4, 0xa57eb }, \ 140 { 20000, 9, 1, 11, 0x4, 0 }, \ 141 { 24000, 10, 3, 11, 0xa, 0 }, \ 142 { 25000, 11, 5, 16, 0xb, 0 }, \ 143 { 26000, 12, 1, 2, 0x10, 0xec4ec4 }, \ 144 { 30000, 13, 3, 8, 0xb, 0 }, \ 145 { 38400, 14, 1, 5, 0x4, 0x955555 }, \ 146 { 40000, 15, 1, 2, 0xb, 0 } \ 147} 148 149#define SIBA_CC_PMU0_PLLTAB_ENTRY \ 150{ \ 151 { 12000, 1, 73, 349525, }, { 13000, 2, 67, 725937, }, \ 152 { 14400, 3, 61, 116508, }, { 15360, 4, 57, 305834, }, \ 153 { 16200, 5, 54, 336579, }, { 16800, 6, 52, 399457, }, \ 154 { 19200, 7, 45, 873813, }, { 19800, 8, 44, 466033, }, \ 155 { 20000, 9, 44, 0, }, { 25000, 10, 70, 419430, }, \ 156 { 26000, 11, 67, 725937, }, { 30000, 12, 58, 699050, }, \ 157 { 38400, 13, 45, 873813, }, { 40000, 14, 45, 0, }, \ 158} 159 160#define SIBA_CC_PMU_4312_PA_REF 2 161#define SIBA_CC_PMU_4325_BURST 1 162#define SIBA_CC_PMU_4325_CLBURST 3 163#define SIBA_CC_PMU_4325_LN 10 164#define SIBA_CC_PMU_4325_CRYSTAL 13 165#define SIBA_CC_PMU_4325_RX_PWR 15 166#define SIBA_CC_PMU_4325_TX_PWR 16 167#define SIBA_CC_PMU_4325_LOGEN_PWR 18 168#define SIBA_CC_PMU_4325_AFE_PWR 19 169#define SIBA_CC_PMU_4325_BBPLL_PWR 20 170#define SIBA_CC_PMU_4325_HT 21 171#define SIBA_CC_PMU_4328_EXT_SWITCH_PWM 0 172#define SIBA_CC_PMU_4328_BB_SWITCH_PWM 1 173#define SIBA_CC_PMU_4328_BB_SWITCH_BURST 2 174#define SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST 3 175#define SIBA_CC_PMU_4328_ILP_REQUEST 4 176#define SIBA_CC_PMU_4328_RADSWITCH_PWM 5 /* radio switch */ 177#define SIBA_CC_PMU_4328_RADSWITCH_BURST 6 178#define SIBA_CC_PMU_4328_ROM_SWITCH 7 179#define SIBA_CC_PMU_4328_PA_REF 8 180#define SIBA_CC_PMU_4328_RADIO 9 181#define SIBA_CC_PMU_4328_AFE 10 182#define SIBA_CC_PMU_4328_PLL 11 183#define SIBA_CC_PMU_4328_BG_FILTBYP 12 184#define SIBA_CC_PMU_4328_TX_FILTBYP 13 185#define SIBA_CC_PMU_4328_RX_FILTBYP 14 186#define SIBA_CC_PMU_4328_CRYSTAL_PU 15 187#define SIBA_CC_PMU_4328_CRYSTAL_EN 16 188#define SIBA_CC_PMU_4328_BB_PLL_FILTBYP 17 189#define SIBA_CC_PMU_4328_RF_PLL_FILTBYP 18 190#define SIBA_CC_PMU_4328_BB_PLL_PU 19 191#define SIBA_CC_PMU_5354_PA_REF 8 192#define SIBA_CC_PMU_5354_BB_PLL_PU 19 193 194#define SIBA_CC_PMU_4325_RES_UPDOWN \ 195{ \ 196 { SIBA_CC_PMU_4325_CRYSTAL, 0x1501 } \ 197} 198 199#define SIBA_CC_PMU_4325_RES_DEPEND \ 200{ \ 201 { SIBA_CC_PMU_4325_HT, SIBA_CC_PMU_DEP_ADD, \ 202 ((1 << SIBA_CC_PMU_4325_RX_PWR) | \ 203 (1 << SIBA_CC_PMU_4325_TX_PWR) | \ 204 (1 << SIBA_CC_PMU_4325_LOGEN_PWR) | \ 205 (1 << SIBA_CC_PMU_4325_AFE_PWR)) } \ 206} 207 208#define SIBA_CC_PMU_4328_RES_UPDOWN \ 209{ \ 210 { SIBA_CC_PMU_4328_EXT_SWITCH_PWM, 0x0101 }, \ 211 { SIBA_CC_PMU_4328_BB_SWITCH_PWM, 0x1f01 }, \ 212 { SIBA_CC_PMU_4328_BB_SWITCH_BURST, 0x010f }, \ 213 { SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST, 0x0101 }, \ 214 { SIBA_CC_PMU_4328_ILP_REQUEST, 0x0202 }, \ 215 { SIBA_CC_PMU_4328_RADSWITCH_PWM, 0x0f01 }, \ 216 { SIBA_CC_PMU_4328_RADSWITCH_BURST, 0x0f01 }, \ 217 { SIBA_CC_PMU_4328_ROM_SWITCH, 0x0101 }, \ 218 { SIBA_CC_PMU_4328_PA_REF, 0x0f01 }, \ 219 { SIBA_CC_PMU_4328_RADIO, 0x0f01 }, \ 220 { SIBA_CC_PMU_4328_AFE, 0x0f01 }, \ 221 { SIBA_CC_PMU_4328_PLL, 0x0f01 }, \ 222 { SIBA_CC_PMU_4328_BG_FILTBYP, 0x0101 }, \ 223 { SIBA_CC_PMU_4328_TX_FILTBYP, 0x0101 }, \ 224 { SIBA_CC_PMU_4328_RX_FILTBYP, 0x0101 }, \ 225 { SIBA_CC_PMU_4328_CRYSTAL_PU, 0x0101 }, \ 226 { SIBA_CC_PMU_4328_CRYSTAL_EN, 0xa001 }, \ 227 { SIBA_CC_PMU_4328_BB_PLL_FILTBYP, 0x0101 }, \ 228 { SIBA_CC_PMU_4328_RF_PLL_FILTBYP, 0x0101 }, \ 229 { SIBA_CC_PMU_4328_BB_PLL_PU, 0x0701 }, \ 230} 231 232#define SIBA_CC_PMU_4328_RES_DEPEND \ 233{ \ 234 { SIBA_CC_PMU_4328_ILP_REQUEST, SIBA_CC_PMU_DEP_SET, \ 235 ((1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | \ 236 (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM)) }, \ 237} 238 239#define SIBA_CC_CHST_4325_PMUTOP_2B 0x00000200 240 241#define SIBA_BAR0 0x80 242#define SIBA_IRQMASK 0x94 243#define SIBA_GPIO_IN 0xb0 244#define SIBA_GPIO_OUT 0xb4 245#define SIBA_GPIO_OUT_EN 0xb8 246#define SIBA_GPIO_CRYSTAL 0x40 247#define SIBA_GPIO_PLL 0x80 248 249#define SIBA_REGWIN(x) \ 250 (SIBA_ENUM_START + ((x) * SIBA_CORE_LEN)) 251#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ 252#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ 253#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ 254#define SIBA_ENUM_START 0x18000000U 255#define SIBA_ENUM_END 0x18010000U 256 257#define SIBA_DMA_TRANSLATION_MASK 0xc0000000 258 259#define SIBA_PCI_DMA 0x40000000U 260#define SIBA_TPS 0x0f18 261#define SIBA_TPS_BPFLAG 0x0000003f 262#define SIBA_IAS 0x0f90 /* Initiator Agent State */ 263#define SIBA_IAS_INBAND_ERR 0x00020000 264#define SIBA_IAS_TIMEOUT 0x00040000 265#define SIBA_INTR_MASK 0x0f94 266#define SIBA_TGSLOW 0x0f98 267#define SIBA_TGSLOW_RESET 0x00000001 /* target state low */ 268#define SIBA_TGSLOW_REJECT_22 0x00000002 269#define SIBA_TGSLOW_REJECT_23 0x00000004 270#define SIBA_TGSLOW_CLOCK 0x00010000 271#define SIBA_TGSLOW_FGC 0x00020000 272#define SIBA_TGSHIGH 0x0f9c 273#define SIBA_TGSHIGH_SERR 0x00000001 274#define SIBA_TGSHIGH_BUSY 0x00000004 275#define SIBA_TGSHIGH_DMA64 0x10000000 276#define SIBA_IMCFGLO 0x0fa8 277#define SIBA_IMCFGLO_SERTO 0x00000007 278#define SIBA_IMCFGLO_REQTO 0x00000070 279#define SIBA_IDLOW 0x0ff8 280#define SIBA_IDLOW_SSBREV 0xf0000000 281#define SIBA_IDLOW_SSBREV_22 0x00000000 282#define SIBA_IDLOW_SSBREV_23 0x10000000 283#define SIBA_IDLOW_SSBREV_24 0x40000000 284#define SIBA_IDLOW_SSBREV_25 0x50000000 285#define SIBA_IDLOW_SSBREV_26 0x60000000 286#define SIBA_IDLOW_SSBREV_27 0x70000000 287#define SIBA_IDHIGH 0x0ffc 288#define SIBA_IDHIGH_CORECODEMASK 0x00008FF0 /* Core Code */ 289#define SIBA_IDHIGH_CORECODE_SHIFT 4 290#define SIBA_IDHIGH_CORECODE(id) \ 291 ((id & SIBA_IDHIGH_CORECODEMASK) >> SIBA_IDHIGH_CORECODE_SHIFT) 292/* Revision Code (low part) */ 293#define SIBA_IDHIGH_REVLO 0x0000000f 294/* Revision Code (high part) */ 295#define SIBA_IDHIGH_REVHI 0x00007000 296#define SIBA_IDHIGH_REVHI_SHIFT 8 297#define SIBA_IDHIGH_REV(id) \ 298 ((id & SIBA_IDHIGH_REVLO) | ((id & SIBA_IDHIGH_REVHI) >> \ 299 SIBA_IDHIGH_REVHI_SHIFT)) 300#define SIBA_IDHIGH_VENDORMASK 0xFFFF0000 /* Vendor Code */ 301#define SIBA_IDHIGH_VENDOR_SHIFT 16 302#define SIBA_IDHIGH_VENDOR(id) \ 303 ((id & SIBA_IDHIGH_VENDORMASK) >> SIBA_IDHIGH_VENDOR_SHIFT) 304 305#define SIBA_SPROMSIZE_R123 64 306#define SIBA_SPROMSIZE_R4 220 307#define SIBA_SPROM_BASE 0x1000 308#define SIBA_SPROM_REV_CRC 0xff00 309 310#define SIBA_SPROM1_MAC_80211BG 0x1048 311#define SIBA_SPROM1_MAC_ETH 0x104e 312#define SIBA_SPROM1_MAC_80211A 0x1054 313#define SIBA_SPROM1_ETHPHY 0x105a 314#define SIBA_SPROM1_ETHPHY_MII_ETH0 0x001f 315#define SIBA_SPROM1_ETHPHY_MII_ETH1 0x03e0 316#define SIBA_SPROM1_ETHPHY_MDIO_ETH0 (1 << 14) 317#define SIBA_SPROM1_ETHPHY_MDIO_ETH1 (1 << 15) 318#define SIBA_SPROM1_BOARDINFO 0x105c 319#define SIBA_SPROM1_BOARDINFO_BREV 0x00ff 320#define SIBA_SPROM1_BOARDINFO_CCODE 0x0f00 321#define SIBA_SPROM1_BOARDINFO_ANTBG 0x3000 322#define SIBA_SPROM1_BOARDINFO_ANTA 0xc000 323#define SIBA_SPROM1_PA0B0 0x105e 324#define SIBA_SPROM1_PA0B1 0x1060 325#define SIBA_SPROM1_PA0B2 0x1062 326#define SIBA_SPROM1_GPIOA 0x1064 327#define SIBA_SPROM1_GPIOA_P0 0x00ff 328#define SIBA_SPROM1_GPIOA_P1 0xff00 329#define SIBA_SPROM1_GPIOB 0x1066 330#define SIBA_SPROM1_GPIOB_P2 0x00ff 331#define SIBA_SPROM1_GPIOB_P3 0xff00 332#define SIBA_SPROM1_MAXPWR 0x1068 333#define SIBA_SPROM1_MAXPWR_BG 0x00ff 334#define SIBA_SPROM1_MAXPWR_A 0xff00 335#define SIBA_SPROM1_PA1B0 0x106a 336#define SIBA_SPROM1_PA1B1 0x106c 337#define SIBA_SPROM1_PA1B2 0x106e 338#define SIBA_SPROM1_TSSI 0x1070 339#define SIBA_SPROM1_TSSI_BG 0x00ff 340#define SIBA_SPROM1_TSSI_A 0xff00 341#define SIBA_SPROM1_BFLOW 0x1072 342#define SIBA_SPROM1_AGAIN 0x1074 343#define SIBA_SPROM1_AGAIN_BG 0x00ff 344#define SIBA_SPROM1_AGAIN_A 0xff00 345 346#define SIBA_SPROM2_BFHIGH 0x1038 347 348#define SIBA_SPROM3_MAC_80211BG 0x104a 349 350#define SIBA_SPROM4_MAC_80211BG 0x104c 351#define SIBA_SPROM4_ETHPHY 0x105a 352#define SIBA_SPROM4_ETHPHY_ET0A 0x001f 353#define SIBA_SPROM4_ETHPHY_ET1A 0x03e0 354#define SIBA_SPROM4_CCODE 0x1052 355#define SIBA_SPROM4_ANTAVAIL 0x105d 356#define SIBA_SPROM4_ANTAVAIL_A 0x00ff 357#define SIBA_SPROM4_ANTAVAIL_BG 0xff00 358#define SIBA_SPROM4_BFLOW 0x1044 359#define SIBA_SPROM4_AGAIN01 0x105e 360#define SIBA_SPROM4_AGAIN0 0x00ff 361#define SIBA_SPROM4_AGAIN1 0xff00 362#define SIBA_SPROM4_AGAIN23 0x1060 363#define SIBA_SPROM4_AGAIN2 0x00ff 364#define SIBA_SPROM4_AGAIN3 0xff00 365#define SIBA_SPROM4_TXPID2G01 0x0062 366#define SIBA_SPROM4_TXPID2G0 0x00ff 367#define SIBA_SPROM4_TXPID2G1 0xff00 368#define SIBA_SPROM4_TXPID2G23 0x0064 369#define SIBA_SPROM4_TXPID2G2 0x00ff 370#define SIBA_SPROM4_TXPID2G3 0xff00 371#define SIBA_SPROM4_TXPID5G01 0x0066 372#define SIBA_SPROM4_TXPID5G0 0x00ff 373#define SIBA_SPROM4_TXPID5G1 0xff00 374#define SIBA_SPROM4_TXPID5G23 0x0068 375#define SIBA_SPROM4_TXPID5G2 0x00ff 376#define SIBA_SPROM4_TXPID5G3 0xff00 377#define SIBA_SPROM4_TXPID5GL01 0x006a 378#define SIBA_SPROM4_TXPID5GL0 0x00ff 379#define SIBA_SPROM4_TXPID5GL1 0xff00 380#define SIBA_SPROM4_TXPID5GL23 0x006c 381#define SIBA_SPROM4_TXPID5GL2 0x00ff 382#define SIBA_SPROM4_TXPID5GL3 0xff00 383#define SIBA_SPROM4_TXPID5GH01 0x006e 384#define SIBA_SPROM4_TXPID5GH0 0x00ff 385#define SIBA_SPROM4_TXPID5GH1 0xff00 386#define SIBA_SPROM4_TXPID5GH23 0x0070 387#define SIBA_SPROM4_TXPID5GH2 0x00ff 388#define SIBA_SPROM4_TXPID5GH3 0xff00 389#define SIBA_SPROM4_BFHIGH 0x1046 390#define SIBA_SPROM4_MAXP_BG 0x1080 391#define SIBA_SPROM4_MAXP_BG_MASK 0x00ff 392#define SIBA_SPROM4_TSSI_BG 0xff00 393#define SIBA_SPROM4_MAXP_A 0x108a 394#define SIBA_SPROM4_MAXP_A_MASK 0x00ff 395#define SIBA_SPROM4_TSSI_A 0xff00 396#define SIBA_SPROM4_GPIOA 0x1056 397#define SIBA_SPROM4_GPIOA_P0 0x00ff 398#define SIBA_SPROM4_GPIOA_P1 0xff00 399#define SIBA_SPROM4_GPIOB 0x1058 400#define SIBA_SPROM4_GPIOB_P2 0x00ff 401#define SIBA_SPROM4_GPIOB_P3 0xff00 402 403/* The following four blocks share the same structure */ 404#define SIBA_SPROM4_PWR_INFO_CORE0 0x1080 405#define SIBA_SPROM4_PWR_INFO_CORE1 0x10AE 406#define SIBA_SPROM4_PWR_INFO_CORE2 0x10DC 407#define SIBA_SPROM4_PWR_INFO_CORE3 0x110A 408 409#define SIBA_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */ 410#define SIBA_SPROM4_2G_MAXP 0x00FF 411#define SIBA_SPROM4_2G_ITSSI 0xFF00 412#define SIBA_SPROM4_2G_ITSSI_SHIFT 8 413#define SIBA_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */ 414#define SIBA_SPROM4_2G_PA_1 0x04 415#define SIBA_SPROM4_2G_PA_2 0x06 416#define SIBA_SPROM4_2G_PA_3 0x08 417#define SIBA_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */ 418#define SIBA_SPROM4_5G_MAXP 0x00FF 419#define SIBA_SPROM4_5G_ITSSI 0xFF00 420#define SIBA_SPROM4_5G_ITSSI_SHIFT 8 421#define SIBA_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */ 422#define SIBA_SPROM4_5GH_MAXP 0x00FF 423#define SIBA_SPROM4_5GL_MAXP 0xFF00 424#define SIBA_SPROM4_5GL_MAXP_SHIFT 8 425#define SIBA_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */ 426#define SIBA_SPROM4_5G_PA_1 0x10 427#define SIBA_SPROM4_5G_PA_2 0x12 428#define SIBA_SPROM4_5G_PA_3 0x14 429#define SIBA_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */ 430#define SIBA_SPROM4_5GL_PA_1 0x18 431#define SIBA_SPROM4_5GL_PA_2 0x1A 432#define SIBA_SPROM4_5GL_PA_3 0x1C 433#define SIBA_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */ 434#define SIBA_SPROM4_5GH_PA_1 0x20 435#define SIBA_SPROM4_5GH_PA_2 0x22 436#define SIBA_SPROM4_5GH_PA_3 0x24 437 438#define SIBA_SPROM5_BFLOW 0x104a 439#define SIBA_SPROM5_BFHIGH 0x104c 440#define SIBA_SPROM5_MAC_80211BG 0x1052 441#define SIBA_SPROM5_CCODE 0x1044 442#define SIBA_SPROM5_GPIOA 0x1076 443#define SIBA_SPROM5_GPIOA_P0 0x00ff 444#define SIBA_SPROM5_GPIOA_P1 0xff00 445#define SIBA_SPROM5_GPIOB 0x1078 446#define SIBA_SPROM5_GPIOB_P2 0x00ff 447#define SIBA_SPROM5_GPIOB_P3 0xff00 448 449#define SIBA_SPROM8_BFLOW 0x1084 450#define SIBA_SPROM8_BFHIGH 0x1086 451#define SIBA_SPROM8_BFL2LO 0x1088 452#define SIBA_SPROM8_BFL2HI 0x108a 453#define SIBA_SPROM8_MAC_80211BG 0x108c 454#define SIBA_SPROM8_CCODE 0x1092 455#define SIBA_SPROM8_ANTAVAIL 0x109c 456#define SIBA_SPROM8_ANTAVAIL_A 0xff00 457#define SIBA_SPROM8_ANTAVAIL_BG 0x00ff 458#define SIBA_SPROM8_AGAIN01 0x109e 459#define SIBA_SPROM8_AGAIN0 0x00ff 460#define SIBA_SPROM8_AGAIN1 0xff00 461#define SIBA_SPROM8_GPIOA 0x1096 462#define SIBA_SPROM8_GPIOA_P0 0x00ff 463#define SIBA_SPROM8_GPIOA_P1 0xff00 464#define SIBA_SPROM8_GPIOB 0x1098 465#define SIBA_SPROM8_GPIOB_P2 0x00ff 466#define SIBA_SPROM8_GPIOB_P3 0xff00 467#define SIBA_SPROM8_AGAIN23 0x10a0 468#define SIBA_SPROM8_AGAIN2 0x00ff 469#define SIBA_SPROM8_AGAIN3 0xff00 470#define SIBA_SPROM8_RSSIPARM2G 0x10a4 471#define SIBA_SPROM8_RSSISMF2G 0x000f 472#define SIBA_SPROM8_RSSISMC2G 0x00f0 473#define SIBA_SPROM8_RSSISAV2G 0x0700 /* BITMASK */ 474#define SIBA_SPROM8_BXA2G 0x1800 /* BITMASK */ 475#define SIBA_SPROM8_RSSIPARM5G 0x10a6 476#define SIBA_SPROM8_RSSISMF5G 0x000f 477#define SIBA_SPROM8_RSSISMC5G 0x00f0 478#define SIBA_SPROM8_RSSISAV5G 0x0700 /* BITMASK */ 479#define SIBA_SPROM8_BXA5G 0x1800 /* BITMASK */ 480#define SIBA_SPROM8_TRI25G 0x10a8 481#define SIBA_SPROM8_TRI2G 0x00ff 482#define SIBA_SPROM8_TRI5G 0xff00 483#define SIBA_SPROM8_TRI5GHL 0x10aa 484#define SIBA_SPROM8_TRI5GL 0x00ff 485#define SIBA_SPROM8_TRI5GH 0xff00 486#define SIBA_SPROM8_RXPO 0x10ac 487#define SIBA_SPROM8_RXPO2G 0x00ff 488#define SIBA_SPROM8_RXPO5G 0xff00 489 490/* The FEM blocks share the same structure */ 491#define SIBA_SPROM8_FEM2G 0x10ae 492#define SIBA_SPROM8_FEM5G 0x10b0 493#define SIBA_SROM8_FEM_TSSIPOS 0x0001 494#define SIBA_SROM8_FEM_EXTPA_GAIN 0x0006 495#define SIBA_SROM8_FEM_PDET_RANGE 0x00F8 496#define SIBA_SROM8_FEM_TR_ISO 0x0700 497#define SIBA_SROM8_FEM_ANTSWLUT 0xF800 498 499#define SIBA_SPROM8_MAXP_BG 0x10c0 500#define SIBA_SPROM8_MAXP_BG_MASK 0x00ff 501#define SIBA_SPROM8_TSSI_BG 0xff00 502#define SIBA_SPROM8_PA0B0 0x10c2 503#define SIBA_SPROM8_PA0B1 0x10c4 504#define SIBA_SPROM8_PA0B2 0x10c6 505#define SIBA_SPROM8_MAXP_A 0x10c8 506#define SIBA_SPROM8_MAXP_A_MASK 0x00ff 507#define SIBA_SPROM8_TSSI_A 0xff00 508#define SIBA_SPROM8_MAXP_AHL 0x10ca 509#define SIBA_SPROM8_MAXP_AH_MASK 0x00ff 510#define SIBA_SPROM8_MAXP_AL_MASK 0xff00 511#define SIBA_SPROM8_PA1B0 0x10cc 512#define SIBA_SPROM8_PA1B1 0x10ce 513#define SIBA_SPROM8_PA1B2 0x10d0 514#define SIBA_SPROM8_PA1LOB0 0x10d2 515#define SIBA_SPROM8_PA1LOB1 0x10d4 516#define SIBA_SPROM8_PA1LOB2 0x10d6 517#define SIBA_SPROM8_PA1HIB0 0x10d8 518#define SIBA_SPROM8_PA1HIB1 0x10da 519#define SIBA_SPROM8_PA1HIB2 0x10dc 520#define SIBA_SPROM8_CCK2GPO 0x1140 521#define SIBA_SPROM8_OFDM2GPO 0x1142 522#define SIBA_SPROM8_OFDM5GPO 0x1146 523#define SIBA_SPROM8_OFDM5GLPO 0x114a 524#define SIBA_SPROM8_OFDM5GHPO 0x114e 525#define SIBA_SPROM8_CDDPO 0x0192 526#define SIBA_SPROM8_STBCPO 0x0194 527#define SIBA_SPROM8_BW40PO 0x0196 528#define SIBA_SPROM8_BWDUPPO 0x0198 529 530/* There are 4 blocks with power info sharing the same layout */ 531#define SIBA_SROM8_PWR_INFO_CORE0 0x10C0 532#define SIBA_SROM8_PWR_INFO_CORE1 0x10E0 533#define SIBA_SROM8_PWR_INFO_CORE2 0x1100 534#define SIBA_SROM8_PWR_INFO_CORE3 0x1120 535 536#define SIBA_SROM8_2G_MAXP_ITSSI 0x00 537#define SIBA_SPROM8_2G_MAXP 0x00FF 538#define SIBA_SPROM8_2G_ITSSI 0xFF00 539#define SIBA_SPROM8_2G_ITSSI_SHIFT 8 540#define SIBA_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */ 541#define SIBA_SROM8_2G_PA_1 0x04 542#define SIBA_SROM8_2G_PA_2 0x06 543#define SIBA_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */ 544#define SIBA_SPROM8_5G_MAXP 0x00FF 545#define SIBA_SPROM8_5G_ITSSI 0xFF00 546#define SIBA_SPROM8_5G_ITSSI_SHIFT 8 547#define SIBA_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */ 548#define SIBA_SPROM8_5GH_MAXP 0x00FF 549#define SIBA_SPROM8_5GL_MAXP 0xFF00 550#define SIBA_SPROM8_5GL_MAXP_SHIFT 8 551#define SIBA_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */ 552#define SIBA_SROM8_5G_PA_1 0x0E 553#define SIBA_SROM8_5G_PA_2 0x10 554#define SIBA_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */ 555#define SIBA_SROM8_5GL_PA_1 0x14 556#define SIBA_SROM8_5GL_PA_2 0x16 557#define SIBA_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */ 558#define SIBA_SROM8_5GH_PA_1 0x1A 559#define SIBA_SROM8_5GH_PA_2 0x1C 560 561#define SIBA_BOARDVENDOR_DELL 0x1028 562#define SIBA_BOARDVENDOR_BCM 0x14e4 563#define SIBA_BOARD_BCM4309G 0x0421 564#define SIBA_BOARD_MP4318 0x044a 565#define SIBA_BOARD_BU4306 0x0416 566#define SIBA_BOARD_BU4309 0x040a 567#define SIBA_BOARD_BCM4321 0x046d 568 569#define SIBA_PCICORE_BCAST_ADDR SIBA_CC_BCAST_ADDR 570#define SIBA_PCICORE_BCAST_DATA SIBA_CC_BCAST_DATA 571#define SIBA_PCICORE_SBTOPCI0 0x0100 572#define SIBA_PCICORE_SBTOPCI1 0x0104 573#define SIBA_PCICORE_SBTOPCI2 0x0108 574#define SIBA_PCICORE_MDIO_CTL 0x0128 575#define SIBA_PCICORE_MDIO_DATA 0x012c 576#define SIBA_PCICORE_SBTOPCI_PREF 0x00000004 577#define SIBA_PCICORE_SBTOPCI_BURST 0x00000008 578#define SIBA_PCICORE_SBTOPCI_MRM 0x00000020 579 580#define SIBA_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */ 581 582#endif /* _SIBA_SIBAREG_H_ */ 583