fenv.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: stable/11/lib/msun/powerpc/fenv.h 330897 2018-03-14 03:19:51Z eadler $
29 */
30
31#ifndef	_FENV_H_
32#define	_FENV_H_
33
34#include <sys/_types.h>
35
36#ifndef	__fenv_static
37#define	__fenv_static	static
38#endif
39
40typedef	__uint32_t	fenv_t;
41typedef	__uint32_t	fexcept_t;
42
43/* Exception flags */
44#define	FE_INEXACT	0x02000000
45#define	FE_DIVBYZERO	0x04000000
46#define	FE_UNDERFLOW	0x08000000
47#define	FE_OVERFLOW	0x10000000
48#define	FE_INVALID	0x20000000	/* all types of invalid FP ops */
49
50/*
51 * The PowerPC architecture has extra invalid flags that indicate the
52 * specific type of invalid operation occurred.  These flags may be
53 * tested, set, and cleared---but not masked---separately.  All of
54 * these bits are cleared when FE_INVALID is cleared, but only
55 * FE_VXSOFT is set when FE_INVALID is explicitly set in software.
56 */
57#define	FE_VXCVI	0x00000100	/* invalid integer convert */
58#define	FE_VXSQRT	0x00000200	/* square root of a negative */
59#define	FE_VXSOFT	0x00000400	/* software-requested exception */
60#define	FE_VXVC		0x00080000	/* ordered comparison involving NaN */
61#define	FE_VXIMZ	0x00100000	/* inf * 0 */
62#define	FE_VXZDZ	0x00200000	/* 0 / 0 */
63#define	FE_VXIDI	0x00400000	/* inf / inf */
64#define	FE_VXISI	0x00800000	/* inf - inf */
65#define	FE_VXSNAN	0x01000000	/* operation on a signalling NaN */
66#define	FE_ALL_INVALID	(FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \
67			 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \
68			 FE_VXSNAN | FE_INVALID)
69#define	FE_ALL_EXCEPT	(FE_DIVBYZERO | FE_INEXACT | \
70			 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
71
72/* Rounding modes */
73#define	FE_TONEAREST	0x0000
74#define	FE_TOWARDZERO	0x0001
75#define	FE_UPWARD	0x0002
76#define	FE_DOWNWARD	0x0003
77#define	_ROUND_MASK	(FE_TONEAREST | FE_DOWNWARD | \
78			 FE_UPWARD | FE_TOWARDZERO)
79
80__BEGIN_DECLS
81
82/* Default floating-point environment */
83extern const fenv_t	__fe_dfl_env;
84#define	FE_DFL_ENV	(&__fe_dfl_env)
85
86/* We need to be able to map status flag positions to mask flag positions */
87#define	_FPUSW_SHIFT	22
88#define	_ENABLE_MASK	((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
89			 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
90
91#ifndef _SOFT_FLOAT
92#define	__mffs(__env)	__asm __volatile("mffs %0" : "=f" (*(__env)))
93#define	__mtfsf(__env)	__asm __volatile("mtfsf 255,%0" : : "f" (__env))
94#else
95#define	__mffs(__env)
96#define	__mtfsf(__env)
97#endif
98
99union __fpscr {
100	double __d;
101	struct {
102#if _BYTE_ORDER == _LITTLE_ENDIAN
103		fenv_t __reg;
104		__uint32_t __junk;
105#else
106		__uint32_t __junk;
107		fenv_t __reg;
108#endif
109	} __bits;
110};
111
112__fenv_static inline int
113feclearexcept(int __excepts)
114{
115	union __fpscr __r;
116
117	if (__excepts & FE_INVALID)
118		__excepts |= FE_ALL_INVALID;
119	__mffs(&__r.__d);
120	__r.__bits.__reg &= ~__excepts;
121	__mtfsf(__r.__d);
122	return (0);
123}
124
125__fenv_static inline int
126fegetexceptflag(fexcept_t *__flagp, int __excepts)
127{
128	union __fpscr __r;
129
130	__mffs(&__r.__d);
131	*__flagp = __r.__bits.__reg & __excepts;
132	return (0);
133}
134
135__fenv_static inline int
136fesetexceptflag(const fexcept_t *__flagp, int __excepts)
137{
138	union __fpscr __r;
139
140	if (__excepts & FE_INVALID)
141		__excepts |= FE_ALL_EXCEPT;
142	__mffs(&__r.__d);
143	__r.__bits.__reg &= ~__excepts;
144	__r.__bits.__reg |= *__flagp & __excepts;
145	__mtfsf(__r.__d);
146	return (0);
147}
148
149__fenv_static inline int
150feraiseexcept(int __excepts)
151{
152	union __fpscr __r;
153
154	if (__excepts & FE_INVALID)
155		__excepts |= FE_VXSOFT;
156	__mffs(&__r.__d);
157	__r.__bits.__reg |= __excepts;
158	__mtfsf(__r.__d);
159	return (0);
160}
161
162__fenv_static inline int
163fetestexcept(int __excepts)
164{
165	union __fpscr __r;
166
167	__mffs(&__r.__d);
168	return (__r.__bits.__reg & __excepts);
169}
170
171__fenv_static inline int
172fegetround(void)
173{
174	union __fpscr __r;
175
176	__mffs(&__r.__d);
177	return (__r.__bits.__reg & _ROUND_MASK);
178}
179
180__fenv_static inline int
181fesetround(int __round)
182{
183	union __fpscr __r;
184
185	if (__round & ~_ROUND_MASK)
186		return (-1);
187	__mffs(&__r.__d);
188	__r.__bits.__reg &= ~_ROUND_MASK;
189	__r.__bits.__reg |= __round;
190	__mtfsf(__r.__d);
191	return (0);
192}
193
194__fenv_static inline int
195fegetenv(fenv_t *__envp)
196{
197	union __fpscr __r;
198
199	__mffs(&__r.__d);
200	*__envp = __r.__bits.__reg;
201	return (0);
202}
203
204__fenv_static inline int
205feholdexcept(fenv_t *__envp)
206{
207	union __fpscr __r;
208
209	__mffs(&__r.__d);
210	*__envp = __r.__d;
211	__r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
212	__mtfsf(__r.__d);
213	return (0);
214}
215
216__fenv_static inline int
217fesetenv(const fenv_t *__envp)
218{
219	union __fpscr __r;
220
221	__r.__bits.__reg = *__envp;
222	__mtfsf(__r.__d);
223	return (0);
224}
225
226__fenv_static inline int
227feupdateenv(const fenv_t *__envp)
228{
229	union __fpscr __r;
230
231	__mffs(&__r.__d);
232	__r.__bits.__reg &= FE_ALL_EXCEPT;
233	__r.__bits.__reg |= *__envp;
234	__mtfsf(__r.__d);
235	return (0);
236}
237
238#if __BSD_VISIBLE
239
240/* We currently provide no external definitions of the functions below. */
241
242static inline int
243feenableexcept(int __mask)
244{
245	union __fpscr __r;
246	fenv_t __oldmask;
247
248	__mffs(&__r.__d);
249	__oldmask = __r.__bits.__reg;
250	__r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
251	__mtfsf(__r.__d);
252	return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
253}
254
255static inline int
256fedisableexcept(int __mask)
257{
258	union __fpscr __r;
259	fenv_t __oldmask;
260
261	__mffs(&__r.__d);
262	__oldmask = __r.__bits.__reg;
263	__r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
264	__mtfsf(__r.__d);
265	return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
266}
267
268static inline int
269fegetexcept(void)
270{
271	union __fpscr __r;
272
273	__mffs(&__r.__d);
274	return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
275}
276
277#endif /* __BSD_VISIBLE */
278
279__END_DECLS
280
281#endif	/* !_FENV_H_ */
282