if_ffec.c revision 331722
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/dev/ffec/if_ffec.c 331722 2018-03-29 02:50:57Z eadler $"); 30 31/* 32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34 * but the driver doesn't currently use any of the ENET advanced features other 35 * than enabling gigabit. 36 * 37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38 * (netgraph/ng_fec.c), so we use 'ffec'. 39 * 40 * Requires an FDT entry with at least these properties: 41 * fec: ethernet@02188000 { 42 * compatible = "fsl,imxNN-fec"; 43 * reg = <0x02188000 0x4000>; 44 * interrupts = <150 151>; 45 * phy-mode = "rgmii"; 46 * phy-disable-preamble; // optional 47 * }; 48 * The second interrupt number is for IEEE-1588, and is not currently used; it 49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50 * There is also an optional property, phy-disable-preamble, which if present 51 * will disable the preamble bits, cutting the size of each mdio transaction 52 * (and thus the busy-wait time) in half. 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/bus.h> 58#include <sys/endian.h> 59#include <sys/kernel.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/mbuf.h> 63#include <sys/module.h> 64#include <sys/mutex.h> 65#include <sys/rman.h> 66#include <sys/socket.h> 67#include <sys/sockio.h> 68#include <sys/sysctl.h> 69 70#include <machine/bus.h> 71 72#include <net/bpf.h> 73#include <net/if.h> 74#include <net/ethernet.h> 75#include <net/if_dl.h> 76#include <net/if_media.h> 77#include <net/if_types.h> 78#include <net/if_var.h> 79#include <net/if_vlan_var.h> 80 81#include <dev/fdt/fdt_common.h> 82#include <dev/ffec/if_ffecreg.h> 83#include <dev/ofw/ofw_bus.h> 84#include <dev/ofw/ofw_bus_subr.h> 85#include <dev/mii/mii.h> 86#include <dev/mii/miivar.h> 87#include <dev/mii/mii_fdt.h> 88#include "miibus_if.h" 89 90/* 91 * There are small differences in the hardware on various SoCs. Not every SoC 92 * we support has its own FECTYPE; most work as GENERIC and only the ones that 93 * need different handling get their own entry. In addition to the types in 94 * this list, there are some flags below that can be ORed into the upper bits. 95 */ 96enum { 97 FECTYPE_NONE, 98 FECTYPE_GENERIC, 99 FECTYPE_IMX53, 100 FECTYPE_IMX6, /* imx6 and imx7 */ 101 FECTYPE_MVF, 102}; 103 104/* 105 * Flags that describe general differences between the FEC hardware in various 106 * SoCs. These are ORed into the FECTYPE enum values in the ofw_compat_data, so 107 * the low 8 bits are reserved for the type enum. In the softc, the type and 108 * flags are put into separate members, so that you don't need to mask the flags 109 * out of the type to compare it. 110 */ 111#define FECTYPE_MASK 0x000000ff 112#define FECFLAG_GBE (1 << 8) 113#define FECFLAG_AVB (1 << 9) 114#define FECFLAG_RACC (1 << 10) 115 116/* 117 * Table of supported FDT compat strings and their associated FECTYPE values. 118 */ 119static struct ofw_compat_data compat_data[] = { 120 {"fsl,imx51-fec", FECTYPE_GENERIC}, 121 {"fsl,imx53-fec", FECTYPE_IMX53}, 122 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE }, 123 {"fsl,imx6ul-fec", FECTYPE_IMX6 | FECFLAG_RACC }, 124 {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE | 125 FECFLAG_AVB }, 126 {"fsl,mvf600-fec", FECTYPE_MVF | FECFLAG_RACC }, 127 {"fsl,mvf-fec", FECTYPE_MVF}, 128 {NULL, FECTYPE_NONE}, 129}; 130 131/* 132 * Driver data and defines. 133 */ 134#define RX_DESC_COUNT 64 135#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 136#define TX_DESC_COUNT 64 137#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 138 139#define WATCHDOG_TIMEOUT_SECS 5 140 141#define MAX_IRQ_COUNT 3 142 143struct ffec_bufmap { 144 struct mbuf *mbuf; 145 bus_dmamap_t map; 146}; 147 148struct ffec_softc { 149 device_t dev; 150 device_t miibus; 151 struct mii_data * mii_softc; 152 struct ifnet *ifp; 153 int if_flags; 154 struct mtx mtx; 155 struct resource *irq_res[MAX_IRQ_COUNT]; 156 struct resource *mem_res; 157 void * intr_cookie[MAX_IRQ_COUNT]; 158 struct callout ffec_callout; 159 mii_contype_t phy_conn_type; 160 uint32_t fecflags; 161 uint8_t fectype; 162 boolean_t link_is_up; 163 boolean_t is_attached; 164 boolean_t is_detaching; 165 int tx_watchdog_count; 166 int rxbuf_align; 167 int txbuf_align; 168 169 bus_dma_tag_t rxdesc_tag; 170 bus_dmamap_t rxdesc_map; 171 struct ffec_hwdesc *rxdesc_ring; 172 bus_addr_t rxdesc_ring_paddr; 173 bus_dma_tag_t rxbuf_tag; 174 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 175 uint32_t rx_idx; 176 177 bus_dma_tag_t txdesc_tag; 178 bus_dmamap_t txdesc_map; 179 struct ffec_hwdesc *txdesc_ring; 180 bus_addr_t txdesc_ring_paddr; 181 bus_dma_tag_t txbuf_tag; 182 struct ffec_bufmap txbuf_map[TX_DESC_COUNT]; 183 uint32_t tx_idx_head; 184 uint32_t tx_idx_tail; 185 int txcount; 186}; 187 188static struct resource_spec irq_res_spec[MAX_IRQ_COUNT + 1] = { 189 { SYS_RES_IRQ, 0, RF_ACTIVE }, 190 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 191 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 192 RESOURCE_SPEC_END 193}; 194 195#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 196#define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 197#define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 198 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 199#define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 200#define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 201#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 202 203static void ffec_init_locked(struct ffec_softc *sc); 204static void ffec_stop_locked(struct ffec_softc *sc); 205static void ffec_txstart_locked(struct ffec_softc *sc); 206static void ffec_txfinish_locked(struct ffec_softc *sc); 207 208static inline uint16_t 209RD2(struct ffec_softc *sc, bus_size_t off) 210{ 211 212 return (bus_read_2(sc->mem_res, off)); 213} 214 215static inline void 216WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 217{ 218 219 bus_write_2(sc->mem_res, off, val); 220} 221 222static inline uint32_t 223RD4(struct ffec_softc *sc, bus_size_t off) 224{ 225 226 return (bus_read_4(sc->mem_res, off)); 227} 228 229static inline void 230WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 231{ 232 233 bus_write_4(sc->mem_res, off, val); 234} 235 236static inline uint32_t 237next_rxidx(struct ffec_softc *sc, uint32_t curidx) 238{ 239 240 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 241} 242 243static inline uint32_t 244next_txidx(struct ffec_softc *sc, uint32_t curidx) 245{ 246 247 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 248} 249 250static void 251ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 252{ 253 254 if (error != 0) 255 return; 256 *(bus_addr_t *)arg = segs[0].ds_addr; 257} 258 259static void 260ffec_miigasket_setup(struct ffec_softc *sc) 261{ 262 uint32_t ifmode; 263 264 /* 265 * We only need the gasket for MII and RMII connections on certain SoCs. 266 */ 267 268 switch (sc->fectype) 269 { 270 case FECTYPE_IMX53: 271 break; 272 default: 273 return; 274 } 275 276 switch (sc->phy_conn_type) 277 { 278 case MII_CONTYPE_MII: 279 ifmode = 0; 280 break; 281 case MII_CONTYPE_RMII: 282 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 283 break; 284 default: 285 return; 286 } 287 288 /* 289 * Disable the gasket, configure for either MII or RMII, then enable. 290 */ 291 292 WR2(sc, FEC_MIIGSK_ENR, 0); 293 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 294 continue; 295 296 WR2(sc, FEC_MIIGSK_CFGR, ifmode); 297 298 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 299 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 300 continue; 301} 302 303static boolean_t 304ffec_miibus_iowait(struct ffec_softc *sc) 305{ 306 uint32_t timeout; 307 308 for (timeout = 10000; timeout != 0; --timeout) 309 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 310 return (true); 311 312 return (false); 313} 314 315static int 316ffec_miibus_readreg(device_t dev, int phy, int reg) 317{ 318 struct ffec_softc *sc; 319 int val; 320 321 sc = device_get_softc(dev); 322 323 WR4(sc, FEC_IER_REG, FEC_IER_MII); 324 325 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 326 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 327 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 328 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 329 330 if (!ffec_miibus_iowait(sc)) { 331 device_printf(dev, "timeout waiting for mii read\n"); 332 return (-1); /* All-ones is a symptom of bad mdio. */ 333 } 334 335 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 336 337 return (val); 338} 339 340static int 341ffec_miibus_writereg(device_t dev, int phy, int reg, int val) 342{ 343 struct ffec_softc *sc; 344 345 sc = device_get_softc(dev); 346 347 WR4(sc, FEC_IER_REG, FEC_IER_MII); 348 349 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 350 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 351 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 352 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 353 (val & FEC_MMFR_DATA_MASK)); 354 355 if (!ffec_miibus_iowait(sc)) { 356 device_printf(dev, "timeout waiting for mii write\n"); 357 return (-1); 358 } 359 360 return (0); 361} 362 363static void 364ffec_miibus_statchg(device_t dev) 365{ 366 struct ffec_softc *sc; 367 struct mii_data *mii; 368 uint32_t ecr, rcr, tcr; 369 370 /* 371 * Called by the MII bus driver when the PHY establishes link to set the 372 * MAC interface registers. 373 */ 374 375 sc = device_get_softc(dev); 376 377 FFEC_ASSERT_LOCKED(sc); 378 379 mii = sc->mii_softc; 380 381 if (mii->mii_media_status & IFM_ACTIVE) 382 sc->link_is_up = true; 383 else 384 sc->link_is_up = false; 385 386 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 387 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 388 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 389 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 390 391 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 392 switch (sc->phy_conn_type) { 393 case MII_CONTYPE_RMII: 394 rcr |= FEC_RCR_RMII_MODE; 395 break; 396 case MII_CONTYPE_RGMII: 397 case MII_CONTYPE_RGMII_ID: 398 case MII_CONTYPE_RGMII_RXID: 399 case MII_CONTYPE_RGMII_TXID: 400 rcr |= FEC_RCR_RGMII_EN; 401 break; 402 default: 403 break; 404 } 405 406 switch (IFM_SUBTYPE(mii->mii_media_active)) { 407 case IFM_1000_T: 408 case IFM_1000_SX: 409 ecr |= FEC_ECR_SPEED; 410 break; 411 case IFM_100_TX: 412 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 413 break; 414 case IFM_10_T: 415 rcr |= FEC_RCR_RMII_10T; 416 break; 417 case IFM_NONE: 418 sc->link_is_up = false; 419 return; 420 default: 421 sc->link_is_up = false; 422 device_printf(dev, "Unsupported media %u\n", 423 IFM_SUBTYPE(mii->mii_media_active)); 424 return; 425 } 426 427 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 428 tcr |= FEC_TCR_FDEN; 429 else 430 rcr |= FEC_RCR_DRT; 431 432 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 433 rcr |= FEC_RCR_FCE; 434 435 WR4(sc, FEC_RCR_REG, rcr); 436 WR4(sc, FEC_TCR_REG, tcr); 437 WR4(sc, FEC_ECR_REG, ecr); 438} 439 440static void 441ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 442{ 443 struct ffec_softc *sc; 444 struct mii_data *mii; 445 446 447 sc = ifp->if_softc; 448 mii = sc->mii_softc; 449 FFEC_LOCK(sc); 450 mii_pollstat(mii); 451 ifmr->ifm_active = mii->mii_media_active; 452 ifmr->ifm_status = mii->mii_media_status; 453 FFEC_UNLOCK(sc); 454} 455 456static int 457ffec_media_change_locked(struct ffec_softc *sc) 458{ 459 460 return (mii_mediachg(sc->mii_softc)); 461} 462 463static int 464ffec_media_change(struct ifnet * ifp) 465{ 466 struct ffec_softc *sc; 467 int error; 468 469 sc = ifp->if_softc; 470 471 FFEC_LOCK(sc); 472 error = ffec_media_change_locked(sc); 473 FFEC_UNLOCK(sc); 474 return (error); 475} 476 477static void ffec_clear_stats(struct ffec_softc *sc) 478{ 479 uint32_t mibc; 480 481 mibc = RD4(sc, FEC_MIBC_REG); 482 483 /* 484 * On newer hardware the statistic regs are cleared by toggling a bit in 485 * the mib control register. On older hardware the clear procedure is 486 * to disable statistics collection, zero the regs, then re-enable. 487 */ 488 if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) { 489 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR); 490 WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR); 491 } else { 492 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS); 493 494 WR4(sc, FEC_IEEE_R_DROP, 0); 495 WR4(sc, FEC_IEEE_R_MACERR, 0); 496 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 497 WR4(sc, FEC_RMON_R_FRAG, 0); 498 WR4(sc, FEC_RMON_R_JAB, 0); 499 WR4(sc, FEC_RMON_R_MC_PKT, 0); 500 WR4(sc, FEC_RMON_R_OVERSIZE, 0); 501 WR4(sc, FEC_RMON_R_PACKETS, 0); 502 WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 503 WR4(sc, FEC_RMON_T_COL, 0); 504 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 505 WR4(sc, FEC_RMON_T_FRAG, 0); 506 WR4(sc, FEC_RMON_T_JAB, 0); 507 WR4(sc, FEC_RMON_T_MC_PKT, 0); 508 WR4(sc, FEC_RMON_T_OVERSIZE , 0); 509 WR4(sc, FEC_RMON_T_PACKETS, 0); 510 WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 511 512 WR4(sc, FEC_MIBC_REG, mibc); 513 } 514} 515 516static void 517ffec_harvest_stats(struct ffec_softc *sc) 518{ 519 struct ifnet *ifp; 520 521 ifp = sc->ifp; 522 523 /* 524 * - FEC_IEEE_R_DROP is "dropped due to invalid start frame delimiter" 525 * so it's really just another type of input error. 526 * - FEC_IEEE_R_MACERR is "no receive fifo space"; count as input drops. 527 */ 528 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); 529 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); 530 if_inc_counter(ifp, IFCOUNTER_IERRORS, 531 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + 532 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + 533 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP)); 534 535 if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR)); 536 537 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS)); 538 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT)); 539 if_inc_counter(ifp, IFCOUNTER_OERRORS, 540 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + 541 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + 542 RD4(sc, FEC_RMON_T_JAB)); 543 544 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL)); 545 546 ffec_clear_stats(sc); 547} 548 549static void 550ffec_tick(void *arg) 551{ 552 struct ffec_softc *sc; 553 struct ifnet *ifp; 554 int link_was_up; 555 556 sc = arg; 557 558 FFEC_ASSERT_LOCKED(sc); 559 560 ifp = sc->ifp; 561 562 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 563 return; 564 565 /* 566 * Typical tx watchdog. If this fires it indicates that we enqueued 567 * packets for output and never got a txdone interrupt for them. Maybe 568 * it's a missed interrupt somehow, just pretend we got one. 569 */ 570 if (sc->tx_watchdog_count > 0) { 571 if (--sc->tx_watchdog_count == 0) { 572 ffec_txfinish_locked(sc); 573 } 574 } 575 576 /* Gather stats from hardware counters. */ 577 ffec_harvest_stats(sc); 578 579 /* Check the media status. */ 580 link_was_up = sc->link_is_up; 581 mii_tick(sc->mii_softc); 582 if (sc->link_is_up && !link_was_up) 583 ffec_txstart_locked(sc); 584 585 /* Schedule another check one second from now. */ 586 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 587} 588 589inline static uint32_t 590ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 591 uint32_t len) 592{ 593 uint32_t nidx; 594 uint32_t flags; 595 596 nidx = next_txidx(sc, idx); 597 598 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 599 if (paddr == 0 || len == 0) { 600 flags = 0; 601 --sc->txcount; 602 } else { 603 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 604 ++sc->txcount; 605 } 606 if (nidx == 0) 607 flags |= FEC_TXDESC_WRAP; 608 609 /* 610 * The hardware requires 32-bit physical addresses. We set up the dma 611 * tag to indicate that, so the cast to uint32_t should never lose 612 * significant bits. 613 */ 614 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 615 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 616 617 return (nidx); 618} 619 620static int 621ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 622{ 623 struct mbuf * m; 624 int error, nsegs; 625 struct bus_dma_segment seg; 626 627 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 628 return (ENOMEM); 629 *mp = m; 630 631 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 632 m, &seg, &nsegs, 0); 633 if (error != 0) { 634 return (ENOMEM); 635 } 636 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 637 BUS_DMASYNC_PREWRITE); 638 639 sc->txbuf_map[idx].mbuf = m; 640 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 641 642 return (0); 643 644} 645 646static void 647ffec_txstart_locked(struct ffec_softc *sc) 648{ 649 struct ifnet *ifp; 650 struct mbuf *m; 651 int enqueued; 652 653 FFEC_ASSERT_LOCKED(sc); 654 655 if (!sc->link_is_up) 656 return; 657 658 ifp = sc->ifp; 659 660 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 661 return; 662 663 enqueued = 0; 664 665 for (;;) { 666 if (sc->txcount == (TX_DESC_COUNT-1)) { 667 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 668 break; 669 } 670 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 671 if (m == NULL) 672 break; 673 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 674 IFQ_DRV_PREPEND(&ifp->if_snd, m); 675 break; 676 } 677 BPF_MTAP(ifp, m); 678 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 679 ++enqueued; 680 } 681 682 if (enqueued != 0) { 683 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); 684 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 685 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); 686 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 687 } 688} 689 690static void 691ffec_txstart(struct ifnet *ifp) 692{ 693 struct ffec_softc *sc = ifp->if_softc; 694 695 FFEC_LOCK(sc); 696 ffec_txstart_locked(sc); 697 FFEC_UNLOCK(sc); 698} 699 700static void 701ffec_txfinish_locked(struct ffec_softc *sc) 702{ 703 struct ifnet *ifp; 704 struct ffec_hwdesc *desc; 705 struct ffec_bufmap *bmap; 706 boolean_t retired_buffer; 707 708 FFEC_ASSERT_LOCKED(sc); 709 710 /* XXX Can't set PRE|POST right now, but we need both. */ 711 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD); 712 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD); 713 ifp = sc->ifp; 714 retired_buffer = false; 715 while (sc->tx_idx_tail != sc->tx_idx_head) { 716 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 717 if (desc->flags_len & FEC_TXDESC_READY) 718 break; 719 retired_buffer = true; 720 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 721 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 722 BUS_DMASYNC_POSTWRITE); 723 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 724 m_freem(bmap->mbuf); 725 bmap->mbuf = NULL; 726 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 727 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 728 } 729 730 /* 731 * If we retired any buffers, there will be open tx slots available in 732 * the descriptor ring, go try to start some new output. 733 */ 734 if (retired_buffer) { 735 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 736 ffec_txstart_locked(sc); 737 } 738 739 /* If there are no buffers outstanding, muzzle the watchdog. */ 740 if (sc->tx_idx_tail == sc->tx_idx_head) { 741 sc->tx_watchdog_count = 0; 742 } 743} 744 745inline static uint32_t 746ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 747{ 748 uint32_t nidx; 749 750 /* 751 * The hardware requires 32-bit physical addresses. We set up the dma 752 * tag to indicate that, so the cast to uint32_t should never lose 753 * significant bits. 754 */ 755 nidx = next_rxidx(sc, idx); 756 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 757 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 758 ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 759 760 return (nidx); 761} 762 763static int 764ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 765{ 766 int error, nsegs; 767 struct bus_dma_segment seg; 768 769 if (!(sc->fecflags & FECFLAG_RACC)) { 770 /* 771 * The RACC[SHIFT16] feature is not available. So, we need to 772 * leave at least ETHER_ALIGN bytes free at the beginning of the 773 * buffer to allow the data to be re-aligned after receiving it 774 * (by copying it backwards ETHER_ALIGN bytes in the same 775 * buffer). We also have to ensure that the beginning of the 776 * buffer is aligned to the hardware's requirements. 777 */ 778 m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align)); 779 } 780 781 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 782 m, &seg, &nsegs, 0); 783 if (error != 0) { 784 return (error); 785 } 786 787 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 788 BUS_DMASYNC_PREREAD); 789 790 sc->rxbuf_map[idx].mbuf = m; 791 ffec_setup_rxdesc(sc, idx, seg.ds_addr); 792 793 return (0); 794} 795 796static struct mbuf * 797ffec_alloc_mbufcl(struct ffec_softc *sc) 798{ 799 struct mbuf *m; 800 801 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 802 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 803 804 return (m); 805} 806 807static void 808ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 809{ 810 struct mbuf *m, *newmbuf; 811 struct ffec_bufmap *bmap; 812 uint8_t *dst, *src; 813 int error; 814 815 /* 816 * First try to get a new mbuf to plug into this slot in the rx ring. 817 * If that fails, drop the current packet and recycle the current 818 * mbuf, which is still mapped and loaded. 819 */ 820 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 821 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 822 ffec_setup_rxdesc(sc, sc->rx_idx, 823 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 824 return; 825 } 826 827 FFEC_UNLOCK(sc); 828 829 bmap = &sc->rxbuf_map[sc->rx_idx]; 830 len -= ETHER_CRC_LEN; 831 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 832 bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 833 m = bmap->mbuf; 834 bmap->mbuf = NULL; 835 m->m_len = len; 836 m->m_pkthdr.len = len; 837 m->m_pkthdr.rcvif = sc->ifp; 838 839 /* 840 * Align the protocol headers in the receive buffer on a 32-bit 841 * boundary. Newer hardware does the alignment for us. On hardware 842 * that doesn't support this feature, we have to copy-align the data. 843 * 844 * XXX for older hardware, could we speed this up by copying just the 845 * protocol headers into their own small mbuf then chaining the cluster 846 * to it? That way we'd only need to copy like 64 bytes or whatever the 847 * biggest header is, instead of the whole 1530ish-byte frame. 848 */ 849 if (sc->fecflags & FECFLAG_RACC) { 850 m->m_data = mtod(m, uint8_t *) + 2; 851 } else { 852 src = mtod(m, uint8_t*); 853 dst = src - ETHER_ALIGN; 854 bcopy(src, dst, len); 855 m->m_data = dst; 856 } 857 sc->ifp->if_input(sc->ifp, m); 858 859 FFEC_LOCK(sc); 860 861 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 862 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 863 /* XXX Now what? We've got a hole in the rx ring. */ 864 } 865 866} 867 868static void 869ffec_rxfinish_locked(struct ffec_softc *sc) 870{ 871 struct ffec_hwdesc *desc; 872 int len; 873 boolean_t produced_empty_buffer; 874 875 FFEC_ASSERT_LOCKED(sc); 876 877 /* XXX Can't set PRE|POST right now, but we need both. */ 878 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD); 879 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD); 880 produced_empty_buffer = false; 881 for (;;) { 882 desc = &sc->rxdesc_ring[sc->rx_idx]; 883 if (desc->flags_len & FEC_RXDESC_EMPTY) 884 break; 885 produced_empty_buffer = true; 886 len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 887 if (len < 64) { 888 /* 889 * Just recycle the descriptor and continue. . 890 */ 891 ffec_setup_rxdesc(sc, sc->rx_idx, 892 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 893 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 894 /* 895 * The entire frame is not in this buffer. Impossible. 896 * Recycle the descriptor and continue. 897 * 898 * XXX what's the right way to handle this? Probably we 899 * should stop/init the hardware because this should 900 * just really never happen when we have buffers bigger 901 * than the maximum frame size. 902 */ 903 device_printf(sc->dev, 904 "fec_rxfinish: received frame without LAST bit set"); 905 ffec_setup_rxdesc(sc, sc->rx_idx, 906 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 907 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 908 /* 909 * Something went wrong with receiving the frame, we 910 * don't care what (the hardware has counted the error 911 * in the stats registers already), we just reuse the 912 * same mbuf, which is still dma-mapped, by resetting 913 * the rx descriptor. 914 */ 915 ffec_setup_rxdesc(sc, sc->rx_idx, 916 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 917 } else { 918 /* 919 * Normal case: a good frame all in one buffer. 920 */ 921 ffec_rxfinish_onebuf(sc, len); 922 } 923 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 924 } 925 926 if (produced_empty_buffer) { 927 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE); 928 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 929 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE); 930 } 931} 932 933static void 934ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 935{ 936 uint32_t palr, paur, rnd; 937 938 /* 939 * Try to recover a MAC address from the running hardware. If there's 940 * something non-zero there, assume the bootloader did the right thing 941 * and just use it. 942 * 943 * Otherwise, set the address to a convenient locally assigned address, 944 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 945 * assigned bit set, and the broadcast/multicast bit clear. 946 */ 947 palr = RD4(sc, FEC_PALR_REG); 948 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 949 if ((palr | paur) != 0) { 950 hwaddr[0] = palr >> 24; 951 hwaddr[1] = palr >> 16; 952 hwaddr[2] = palr >> 8; 953 hwaddr[3] = palr >> 0; 954 hwaddr[4] = paur >> 24; 955 hwaddr[5] = paur >> 16; 956 } else { 957 rnd = arc4random() & 0x00ffffff; 958 hwaddr[0] = 'b'; 959 hwaddr[1] = 's'; 960 hwaddr[2] = 'd'; 961 hwaddr[3] = rnd >> 16; 962 hwaddr[4] = rnd >> 8; 963 hwaddr[5] = rnd >> 0; 964 } 965 966 if (bootverbose) { 967 device_printf(sc->dev, 968 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 969 hwaddr[0], hwaddr[1], hwaddr[2], 970 hwaddr[3], hwaddr[4], hwaddr[5]); 971 } 972} 973 974static void 975ffec_setup_rxfilter(struct ffec_softc *sc) 976{ 977 struct ifnet *ifp; 978 struct ifmultiaddr *ifma; 979 uint8_t *eaddr; 980 uint32_t crc; 981 uint64_t ghash, ihash; 982 983 FFEC_ASSERT_LOCKED(sc); 984 985 ifp = sc->ifp; 986 987 /* 988 * Set the multicast (group) filter hash. 989 */ 990 if ((ifp->if_flags & IFF_ALLMULTI)) 991 ghash = 0xffffffffffffffffLLU; 992 else { 993 ghash = 0; 994 if_maddr_rlock(ifp); 995 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 996 if (ifma->ifma_addr->sa_family != AF_LINK) 997 continue; 998 /* 6 bits from MSB in LE CRC32 are used for hash. */ 999 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1000 ifma->ifma_addr), ETHER_ADDR_LEN); 1001 ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 1002 } 1003 if_maddr_runlock(ifp); 1004 } 1005 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 1006 WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 1007 1008 /* 1009 * Set the individual address filter hash. 1010 * 1011 * XXX Is 0 the right value when promiscuous is off? This hw feature 1012 * seems to support the concept of MAC address aliases, does such a 1013 * thing even exist? 1014 */ 1015 if ((ifp->if_flags & IFF_PROMISC)) 1016 ihash = 0xffffffffffffffffLLU; 1017 else { 1018 ihash = 0; 1019 } 1020 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 1021 WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 1022 1023 /* 1024 * Set the primary address. 1025 */ 1026 eaddr = IF_LLADDR(ifp); 1027 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 1028 (eaddr[2] << 8) | eaddr[3]); 1029 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 1030} 1031 1032static void 1033ffec_stop_locked(struct ffec_softc *sc) 1034{ 1035 struct ifnet *ifp; 1036 struct ffec_hwdesc *desc; 1037 struct ffec_bufmap *bmap; 1038 int idx; 1039 1040 FFEC_ASSERT_LOCKED(sc); 1041 1042 ifp = sc->ifp; 1043 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1044 sc->tx_watchdog_count = 0; 1045 1046 /* 1047 * Stop the hardware, mask all interrupts, and clear all current 1048 * interrupt status bits. 1049 */ 1050 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1051 WR4(sc, FEC_IEM_REG, 0x00000000); 1052 WR4(sc, FEC_IER_REG, 0xffffffff); 1053 1054 /* 1055 * Stop the media-check callout. Do not use callout_drain() because 1056 * we're holding a mutex the callout acquires, and if it's currently 1057 * waiting to acquire it, we'd deadlock. If it is waiting now, the 1058 * ffec_tick() routine will return without doing anything when it sees 1059 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1060 */ 1061 callout_stop(&sc->ffec_callout); 1062 1063 /* 1064 * Discard all untransmitted buffers. Each buffer is simply freed; 1065 * it's as if the bits were transmitted and then lost on the wire. 1066 * 1067 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1068 * back on the queue for when we get restarted later? 1069 */ 1070 idx = sc->tx_idx_tail; 1071 while (idx != sc->tx_idx_head) { 1072 desc = &sc->txdesc_ring[idx]; 1073 bmap = &sc->txbuf_map[idx]; 1074 if (desc->buf_paddr != 0) { 1075 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1076 m_freem(bmap->mbuf); 1077 bmap->mbuf = NULL; 1078 ffec_setup_txdesc(sc, idx, 0, 0); 1079 } 1080 idx = next_txidx(sc, idx); 1081 } 1082 1083 /* 1084 * Discard all unprocessed receive buffers. This amounts to just 1085 * pretending that nothing ever got received into them. We reuse the 1086 * mbuf already mapped for each desc, simply turning the EMPTY flags 1087 * back on so they'll get reused when we start up again. 1088 */ 1089 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1090 desc = &sc->rxdesc_ring[idx]; 1091 ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1092 } 1093} 1094 1095static void 1096ffec_init_locked(struct ffec_softc *sc) 1097{ 1098 struct ifnet *ifp = sc->ifp; 1099 uint32_t maxbuf, maxfl, regval; 1100 1101 FFEC_ASSERT_LOCKED(sc); 1102 1103 /* 1104 * The hardware has a limit of 0x7ff as the max frame length (see 1105 * comments for MRBR below), and we use mbuf clusters as receive 1106 * buffers, and we currently are designed to receive an entire frame 1107 * into a single buffer. 1108 * 1109 * We start with a MCLBYTES-sized cluster, but we have to offset into 1110 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1111 * and then that value has to be rounded up to the hardware's DMA 1112 * alignment requirements, so all in all our buffer is that much smaller 1113 * than MCLBYTES. 1114 * 1115 * The resulting value is used as the frame truncation length and the 1116 * max buffer receive buffer size for now. It'll become more complex 1117 * when we support jumbo frames and receiving fragments of them into 1118 * separate buffers. 1119 */ 1120 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align); 1121 maxfl = min(maxbuf, 0x7ff); 1122 1123 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1124 return; 1125 1126 /* Mask all interrupts and clear all current interrupt status bits. */ 1127 WR4(sc, FEC_IEM_REG, 0x00000000); 1128 WR4(sc, FEC_IER_REG, 0xffffffff); 1129 1130 /* 1131 * Go set up palr/puar, galr/gaur, ialr/iaur. 1132 */ 1133 ffec_setup_rxfilter(sc); 1134 1135 /* 1136 * TFWR - Transmit FIFO watermark register. 1137 * 1138 * Set the transmit fifo watermark register to "store and forward" mode 1139 * and also set a threshold of 128 bytes in the fifo before transmission 1140 * of a frame begins (to avoid dma underruns). Recent FEC hardware 1141 * supports STRFWD and when that bit is set, the watermark level in the 1142 * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1143 * to that bit is innocuous, and the TWFR bits get used instead. 1144 */ 1145 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1146 1147 /* RCR - Receive control register. 1148 * 1149 * Set max frame length + clean out anything left from u-boot. 1150 */ 1151 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1152 1153 /* 1154 * TCR - Transmit control register. 1155 * 1156 * Clean out anything left from u-boot. Any necessary values are set in 1157 * ffec_miibus_statchg() based on the media type. 1158 */ 1159 WR4(sc, FEC_TCR_REG, 0); 1160 1161 /* 1162 * OPD - Opcode/pause duration. 1163 * 1164 * XXX These magic numbers come from u-boot. 1165 */ 1166 WR4(sc, FEC_OPD_REG, 0x00010020); 1167 1168 /* 1169 * FRSR - Fifo receive start register. 1170 * 1171 * This register does not exist on imx6, it is present on earlier 1172 * hardware. The u-boot code sets this to a non-default value that's 32 1173 * bytes larger than the default, with no clue as to why. The default 1174 * value should work fine, so there's no code to init it here. 1175 */ 1176 1177 /* 1178 * MRBR - Max RX buffer size. 1179 * 1180 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1181 * but the datasheet says no such thing for imx6. On the imx6, setting 1182 * this to 2K without setting EN1588 resulted in a crazy runaway 1183 * receive loop in the hardware, where every rx descriptor in the ring 1184 * had its EMPTY flag cleared, no completion or error flags set, and a 1185 * length of zero. I think maybe you can only exceed it when EN1588 is 1186 * set, like maybe that's what enables jumbo frames, because in general 1187 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1188 * compatible" flag. 1189 */ 1190 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1191 1192 /* 1193 * FTRL - Frame truncation length. 1194 * 1195 * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1196 */ 1197 WR4(sc, FEC_FTRL_REG, maxfl); 1198 1199 /* 1200 * RDSR / TDSR descriptor ring pointers. 1201 * 1202 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1203 * internal current descriptor index values for both rings, so we zero 1204 * our index values as well. 1205 */ 1206 sc->rx_idx = 0; 1207 sc->tx_idx_head = sc->tx_idx_tail = 0; 1208 sc->txcount = 0; 1209 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1210 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1211 1212 /* 1213 * EIM - interrupt mask register. 1214 * 1215 * We always enable the same set of interrupts while running; unlike 1216 * some drivers there's no need to change the mask on the fly depending 1217 * on what operations are in progress. 1218 */ 1219 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1220 1221 /* 1222 * MIBC - MIB control (hardware stats); clear all statistics regs, then 1223 * enable collection of statistics. 1224 */ 1225 regval = RD4(sc, FEC_MIBC_REG); 1226 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1227 ffec_clear_stats(sc); 1228 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1229 1230 if (sc->fecflags & FECFLAG_RACC) { 1231 /* 1232 * RACC - Receive Accelerator Function Configuration. 1233 */ 1234 regval = RD4(sc, FEC_RACC_REG); 1235 WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16); 1236 } 1237 1238 /* 1239 * ECR - Ethernet control register. 1240 * 1241 * This must happen after all the other config registers are set. If 1242 * we're running on little-endian hardware, also set the flag for byte- 1243 * swapping descriptor ring entries. This flag doesn't exist on older 1244 * hardware, but it can be safely set -- the bit position it occupies 1245 * was unused. 1246 */ 1247 regval = RD4(sc, FEC_ECR_REG); 1248#if _BYTE_ORDER == _LITTLE_ENDIAN 1249 regval |= FEC_ECR_DBSWP; 1250#endif 1251 regval |= FEC_ECR_ETHEREN; 1252 WR4(sc, FEC_ECR_REG, regval); 1253 1254 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1255 1256 /* 1257 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1258 * set up the remaining config registers based on the current media. 1259 */ 1260 mii_mediachg(sc->mii_softc); 1261 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1262 1263 /* 1264 * Tell the hardware that receive buffers are available. They were made 1265 * available in ffec_attach() or ffec_stop(). 1266 */ 1267 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1268} 1269 1270static void 1271ffec_init(void *if_softc) 1272{ 1273 struct ffec_softc *sc = if_softc; 1274 1275 FFEC_LOCK(sc); 1276 ffec_init_locked(sc); 1277 FFEC_UNLOCK(sc); 1278} 1279 1280static void 1281ffec_intr(void *arg) 1282{ 1283 struct ffec_softc *sc; 1284 uint32_t ier; 1285 1286 sc = arg; 1287 1288 FFEC_LOCK(sc); 1289 1290 ier = RD4(sc, FEC_IER_REG); 1291 1292 if (ier & FEC_IER_TXF) { 1293 WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1294 ffec_txfinish_locked(sc); 1295 } 1296 1297 if (ier & FEC_IER_RXF) { 1298 WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1299 ffec_rxfinish_locked(sc); 1300 } 1301 1302 /* 1303 * We actually don't care about most errors, because the hardware copes 1304 * with them just fine, discarding the incoming bad frame, or forcing a 1305 * bad CRC onto an outgoing bad frame, and counting the errors in the 1306 * stats registers. The one that really matters is EBERR (DMA bus 1307 * error) because the hardware automatically clears ECR[ETHEREN] and we 1308 * have to restart it here. It should never happen. 1309 */ 1310 if (ier & FEC_IER_EBERR) { 1311 WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1312 device_printf(sc->dev, 1313 "Ethernet DMA error, restarting controller.\n"); 1314 ffec_stop_locked(sc); 1315 ffec_init_locked(sc); 1316 } 1317 1318 FFEC_UNLOCK(sc); 1319 1320} 1321 1322static int 1323ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1324{ 1325 struct ffec_softc *sc; 1326 struct mii_data *mii; 1327 struct ifreq *ifr; 1328 int mask, error; 1329 1330 sc = ifp->if_softc; 1331 ifr = (struct ifreq *)data; 1332 1333 error = 0; 1334 switch (cmd) { 1335 case SIOCSIFFLAGS: 1336 FFEC_LOCK(sc); 1337 if (ifp->if_flags & IFF_UP) { 1338 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1339 if ((ifp->if_flags ^ sc->if_flags) & 1340 (IFF_PROMISC | IFF_ALLMULTI)) 1341 ffec_setup_rxfilter(sc); 1342 } else { 1343 if (!sc->is_detaching) 1344 ffec_init_locked(sc); 1345 } 1346 } else { 1347 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1348 ffec_stop_locked(sc); 1349 } 1350 sc->if_flags = ifp->if_flags; 1351 FFEC_UNLOCK(sc); 1352 break; 1353 1354 case SIOCADDMULTI: 1355 case SIOCDELMULTI: 1356 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1357 FFEC_LOCK(sc); 1358 ffec_setup_rxfilter(sc); 1359 FFEC_UNLOCK(sc); 1360 } 1361 break; 1362 1363 case SIOCSIFMEDIA: 1364 case SIOCGIFMEDIA: 1365 mii = sc->mii_softc; 1366 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1367 break; 1368 1369 case SIOCSIFCAP: 1370 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1371 if (mask & IFCAP_VLAN_MTU) { 1372 /* No work to do except acknowledge the change took. */ 1373 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1374 } 1375 break; 1376 1377 default: 1378 error = ether_ioctl(ifp, cmd, data); 1379 break; 1380 } 1381 1382 return (error); 1383} 1384 1385static int 1386ffec_detach(device_t dev) 1387{ 1388 struct ffec_softc *sc; 1389 bus_dmamap_t map; 1390 int idx, irq; 1391 1392 /* 1393 * NB: This function can be called internally to unwind a failure to 1394 * attach. Make sure a resource got allocated/created before destroying. 1395 */ 1396 1397 sc = device_get_softc(dev); 1398 1399 if (sc->is_attached) { 1400 FFEC_LOCK(sc); 1401 sc->is_detaching = true; 1402 ffec_stop_locked(sc); 1403 FFEC_UNLOCK(sc); 1404 callout_drain(&sc->ffec_callout); 1405 ether_ifdetach(sc->ifp); 1406 } 1407 1408 /* XXX no miibus detach? */ 1409 1410 /* Clean up RX DMA resources and free mbufs. */ 1411 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1412 if ((map = sc->rxbuf_map[idx].map) != NULL) { 1413 bus_dmamap_unload(sc->rxbuf_tag, map); 1414 bus_dmamap_destroy(sc->rxbuf_tag, map); 1415 m_freem(sc->rxbuf_map[idx].mbuf); 1416 } 1417 } 1418 if (sc->rxbuf_tag != NULL) 1419 bus_dma_tag_destroy(sc->rxbuf_tag); 1420 if (sc->rxdesc_map != NULL) { 1421 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1422 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1423 } 1424 if (sc->rxdesc_tag != NULL) 1425 bus_dma_tag_destroy(sc->rxdesc_tag); 1426 1427 /* Clean up TX DMA resources. */ 1428 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1429 if ((map = sc->txbuf_map[idx].map) != NULL) { 1430 /* TX maps are already unloaded. */ 1431 bus_dmamap_destroy(sc->txbuf_tag, map); 1432 } 1433 } 1434 if (sc->txbuf_tag != NULL) 1435 bus_dma_tag_destroy(sc->txbuf_tag); 1436 if (sc->txdesc_map != NULL) { 1437 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1438 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1439 } 1440 if (sc->txdesc_tag != NULL) 1441 bus_dma_tag_destroy(sc->txdesc_tag); 1442 1443 /* Release bus resources. */ 1444 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1445 if (sc->intr_cookie[irq] != NULL) { 1446 bus_teardown_intr(dev, sc->irq_res[irq], 1447 sc->intr_cookie[irq]); 1448 } 1449 } 1450 bus_release_resources(dev, irq_res_spec, sc->irq_res); 1451 1452 if (sc->mem_res != NULL) 1453 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1454 1455 FFEC_LOCK_DESTROY(sc); 1456 return (0); 1457} 1458 1459static int 1460ffec_attach(device_t dev) 1461{ 1462 struct ffec_softc *sc; 1463 struct ifnet *ifp = NULL; 1464 struct mbuf *m; 1465 void *dummy; 1466 uintptr_t typeflags; 1467 phandle_t ofw_node; 1468 uint32_t idx, mscr; 1469 int error, phynum, rid, irq; 1470 uint8_t eaddr[ETHER_ADDR_LEN]; 1471 1472 sc = device_get_softc(dev); 1473 sc->dev = dev; 1474 1475 FFEC_LOCK_INIT(sc); 1476 1477 /* 1478 * There are differences in the implementation and features of the FEC 1479 * hardware on different SoCs, so figure out what type we are. 1480 */ 1481 typeflags = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1482 sc->fectype = (uint8_t)(typeflags & FECTYPE_MASK); 1483 sc->fecflags = (uint32_t)(typeflags & ~FECTYPE_MASK); 1484 1485 if (sc->fecflags & FECFLAG_AVB) { 1486 sc->rxbuf_align = 64; 1487 sc->txbuf_align = 1; 1488 } else { 1489 sc->rxbuf_align = 16; 1490 sc->txbuf_align = 16; 1491 } 1492 1493 /* 1494 * We have to be told what kind of electrical connection exists between 1495 * the MAC and PHY or we can't operate correctly. 1496 */ 1497 if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1498 device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1499 error = ENXIO; 1500 goto out; 1501 } 1502 sc->phy_conn_type = mii_fdt_get_contype(ofw_node); 1503 if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) { 1504 device_printf(sc->dev, "No valid 'phy-mode' " 1505 "property found in FDT data for device.\n"); 1506 error = ENOATTR; 1507 goto out; 1508 } 1509 1510 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1511 1512 /* Allocate bus resources for accessing the hardware. */ 1513 rid = 0; 1514 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1515 RF_ACTIVE); 1516 if (sc->mem_res == NULL) { 1517 device_printf(dev, "could not allocate memory resources.\n"); 1518 error = ENOMEM; 1519 goto out; 1520 } 1521 1522 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 1523 if (error != 0) { 1524 device_printf(dev, "could not allocate interrupt resources\n"); 1525 goto out; 1526 } 1527 1528 /* 1529 * Set up TX descriptor ring, descriptors, and dma maps. 1530 */ 1531 error = bus_dma_tag_create( 1532 bus_get_dma_tag(dev), /* Parent tag. */ 1533 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1534 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1535 BUS_SPACE_MAXADDR, /* highaddr */ 1536 NULL, NULL, /* filter, filterarg */ 1537 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1538 TX_DESC_SIZE, /* maxsegsize */ 1539 0, /* flags */ 1540 NULL, NULL, /* lockfunc, lockarg */ 1541 &sc->txdesc_tag); 1542 if (error != 0) { 1543 device_printf(sc->dev, 1544 "could not create TX ring DMA tag.\n"); 1545 goto out; 1546 } 1547 1548 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1549 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1550 if (error != 0) { 1551 device_printf(sc->dev, 1552 "could not allocate TX descriptor ring.\n"); 1553 goto out; 1554 } 1555 1556 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1557 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1558 if (error != 0) { 1559 device_printf(sc->dev, 1560 "could not load TX descriptor ring map.\n"); 1561 goto out; 1562 } 1563 1564 error = bus_dma_tag_create( 1565 bus_get_dma_tag(dev), /* Parent tag. */ 1566 sc->txbuf_align, 0, /* alignment, boundary */ 1567 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1568 BUS_SPACE_MAXADDR, /* highaddr */ 1569 NULL, NULL, /* filter, filterarg */ 1570 MCLBYTES, 1, /* maxsize, nsegments */ 1571 MCLBYTES, /* maxsegsize */ 1572 0, /* flags */ 1573 NULL, NULL, /* lockfunc, lockarg */ 1574 &sc->txbuf_tag); 1575 if (error != 0) { 1576 device_printf(sc->dev, 1577 "could not create TX ring DMA tag.\n"); 1578 goto out; 1579 } 1580 1581 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1582 error = bus_dmamap_create(sc->txbuf_tag, 0, 1583 &sc->txbuf_map[idx].map); 1584 if (error != 0) { 1585 device_printf(sc->dev, 1586 "could not create TX buffer DMA map.\n"); 1587 goto out; 1588 } 1589 ffec_setup_txdesc(sc, idx, 0, 0); 1590 } 1591 1592 /* 1593 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1594 */ 1595 error = bus_dma_tag_create( 1596 bus_get_dma_tag(dev), /* Parent tag. */ 1597 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1598 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1599 BUS_SPACE_MAXADDR, /* highaddr */ 1600 NULL, NULL, /* filter, filterarg */ 1601 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1602 RX_DESC_SIZE, /* maxsegsize */ 1603 0, /* flags */ 1604 NULL, NULL, /* lockfunc, lockarg */ 1605 &sc->rxdesc_tag); 1606 if (error != 0) { 1607 device_printf(sc->dev, 1608 "could not create RX ring DMA tag.\n"); 1609 goto out; 1610 } 1611 1612 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1613 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1614 if (error != 0) { 1615 device_printf(sc->dev, 1616 "could not allocate RX descriptor ring.\n"); 1617 goto out; 1618 } 1619 1620 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1621 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1622 if (error != 0) { 1623 device_printf(sc->dev, 1624 "could not load RX descriptor ring map.\n"); 1625 goto out; 1626 } 1627 1628 error = bus_dma_tag_create( 1629 bus_get_dma_tag(dev), /* Parent tag. */ 1630 1, 0, /* alignment, boundary */ 1631 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1632 BUS_SPACE_MAXADDR, /* highaddr */ 1633 NULL, NULL, /* filter, filterarg */ 1634 MCLBYTES, 1, /* maxsize, nsegments */ 1635 MCLBYTES, /* maxsegsize */ 1636 0, /* flags */ 1637 NULL, NULL, /* lockfunc, lockarg */ 1638 &sc->rxbuf_tag); 1639 if (error != 0) { 1640 device_printf(sc->dev, 1641 "could not create RX buf DMA tag.\n"); 1642 goto out; 1643 } 1644 1645 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1646 error = bus_dmamap_create(sc->rxbuf_tag, 0, 1647 &sc->rxbuf_map[idx].map); 1648 if (error != 0) { 1649 device_printf(sc->dev, 1650 "could not create RX buffer DMA map.\n"); 1651 goto out; 1652 } 1653 if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1654 device_printf(dev, "Could not alloc mbuf\n"); 1655 error = ENOMEM; 1656 goto out; 1657 } 1658 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1659 device_printf(sc->dev, 1660 "could not create new RX buffer.\n"); 1661 goto out; 1662 } 1663 } 1664 1665 /* Try to get the MAC address from the hardware before resetting it. */ 1666 ffec_get_hwaddr(sc, eaddr); 1667 1668 /* 1669 * Reset the hardware. Disables all interrupts. 1670 * 1671 * When the FEC is connected to the AXI bus (indicated by AVB flag), a 1672 * MAC reset while a bus transaction is pending can hang the bus. 1673 * Instead of resetting, turn off the ENABLE bit, which allows the 1674 * hardware to complete any in-progress transfers (appending a bad CRC 1675 * to any partial packet) and release the AXI bus. This could probably 1676 * be done unconditionally for all hardware variants, but that hasn't 1677 * been tested. 1678 */ 1679 if (sc->fecflags & FECFLAG_AVB) 1680 WR4(sc, FEC_ECR_REG, 0); 1681 else 1682 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1683 1684 /* Setup interrupt handler. */ 1685 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1686 if (sc->irq_res[irq] != NULL) { 1687 error = bus_setup_intr(dev, sc->irq_res[irq], 1688 INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc, 1689 &sc->intr_cookie[irq]); 1690 if (error != 0) { 1691 device_printf(dev, 1692 "could not setup interrupt handler.\n"); 1693 goto out; 1694 } 1695 } 1696 } 1697 1698 /* 1699 * Set up the PHY control register. 1700 * 1701 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1702 * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1703 * 1704 * XXX - Revisit this... 1705 * 1706 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1707 * code uses 10. Both values seem to work, but I suspect many modern 1708 * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1709 * 1710 * Different imx manuals use confusingly different terminology (things 1711 * like "system clock" and "internal module clock") with examples that 1712 * use frequencies that have nothing to do with ethernet, giving the 1713 * vague impression that maybe the clock in question is the periphclock 1714 * or something. In fact, on an imx53 development board (FEC), 1715 * measuring the mdio clock at the pin on the PHY and playing with 1716 * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1717 * aka periphclock) and 13 was the right divisor. 1718 * 1719 * All in all, it seems likely that 13 is a safe divisor for now, 1720 * because if we really do need to base it on the peripheral clock 1721 * speed, then we need a platform-independant get-clock-freq API. 1722 */ 1723 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1724 if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1725 mscr |= FEC_MSCR_DIS_PRE; 1726 if (bootverbose) 1727 device_printf(dev, "PHY preamble disabled\n"); 1728 } 1729 WR4(sc, FEC_MSCR_REG, mscr); 1730 1731 /* Set up the ethernet interface. */ 1732 sc->ifp = ifp = if_alloc(IFT_ETHER); 1733 1734 ifp->if_softc = sc; 1735 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1736 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1737 ifp->if_capabilities = IFCAP_VLAN_MTU; 1738 ifp->if_capenable = ifp->if_capabilities; 1739 ifp->if_start = ffec_txstart; 1740 ifp->if_ioctl = ffec_ioctl; 1741 ifp->if_init = ffec_init; 1742 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1743 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1744 IFQ_SET_READY(&ifp->if_snd); 1745 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1746 1747#if 0 /* XXX The hardware keeps stats we could use for these. */ 1748 ifp->if_linkmib = &sc->mibdata; 1749 ifp->if_linkmiblen = sizeof(sc->mibdata); 1750#endif 1751 1752 /* Set up the miigasket hardware (if any). */ 1753 ffec_miigasket_setup(sc); 1754 1755 /* Attach the mii driver. */ 1756 if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) { 1757 phynum = MII_PHY_ANY; 1758 } 1759 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1760 ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY, 1761 (sc->fecflags & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1762 if (error != 0) { 1763 device_printf(dev, "PHY attach failed\n"); 1764 goto out; 1765 } 1766 sc->mii_softc = device_get_softc(sc->miibus); 1767 1768 /* All ready to run, attach the ethernet interface. */ 1769 ether_ifattach(ifp, eaddr); 1770 sc->is_attached = true; 1771 1772 error = 0; 1773out: 1774 1775 if (error != 0) 1776 ffec_detach(dev); 1777 1778 return (error); 1779} 1780 1781static int 1782ffec_probe(device_t dev) 1783{ 1784 uintptr_t fectype; 1785 1786 if (!ofw_bus_status_okay(dev)) 1787 return (ENXIO); 1788 1789 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1790 if (fectype == FECTYPE_NONE) 1791 return (ENXIO); 1792 1793 device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1794 "Freescale Gigabit Ethernet Controller" : 1795 "Freescale Fast Ethernet Controller"); 1796 1797 return (BUS_PROBE_DEFAULT); 1798} 1799 1800 1801static device_method_t ffec_methods[] = { 1802 /* Device interface. */ 1803 DEVMETHOD(device_probe, ffec_probe), 1804 DEVMETHOD(device_attach, ffec_attach), 1805 DEVMETHOD(device_detach, ffec_detach), 1806 1807/* 1808 DEVMETHOD(device_shutdown, ffec_shutdown), 1809 DEVMETHOD(device_suspend, ffec_suspend), 1810 DEVMETHOD(device_resume, ffec_resume), 1811*/ 1812 1813 /* MII interface. */ 1814 DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1815 DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1816 DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1817 1818 DEVMETHOD_END 1819}; 1820 1821static driver_t ffec_driver = { 1822 "ffec", 1823 ffec_methods, 1824 sizeof(struct ffec_softc) 1825}; 1826 1827static devclass_t ffec_devclass; 1828 1829DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1830DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1831 1832MODULE_DEPEND(ffec, ether, 1, 1, 1); 1833MODULE_DEPEND(ffec, miibus, 1, 1, 1); 1834