xgehal-regs.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2007 Neterion, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/11/sys/dev/nxge/include/xgehal-regs.h 330897 2018-03-14 03:19:51Z eadler $ 29 */ 30 31#ifndef XGE_HAL_REGS_H 32#define XGE_HAL_REGS_H 33 34__EXTERN_BEGIN_DECLS 35 36typedef struct { 37 38/* General Control-Status Registers */ 39 u64 general_int_status; 40#define XGE_HAL_GEN_INTR_TXPIC BIT(0) 41#define XGE_HAL_GEN_INTR_TXDMA BIT(1) 42#define XGE_HAL_GEN_INTR_TXMAC BIT(2) 43#define XGE_HAL_GEN_INTR_TXXGXS BIT(3) 44#define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8) 45#define XGE_HAL_GEN_INTR_RXPIC BIT(32) 46#define XGE_HAL_GEN_INTR_RXDMA BIT(33) 47#define XGE_HAL_GEN_INTR_RXMAC BIT(34) 48#define XGE_HAL_GEN_INTR_MC BIT(35) 49#define XGE_HAL_GEN_INTR_RXXGXS BIT(36) 50#define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40) 51#define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \ 52 XGE_HAL_GEN_INTR_RXPIC | \ 53 XGE_HAL_GEN_INTR_TXDMA | \ 54 XGE_HAL_GEN_INTR_RXDMA | \ 55 XGE_HAL_GEN_INTR_TXMAC | \ 56 XGE_HAL_GEN_INTR_RXMAC | \ 57 XGE_HAL_GEN_INTR_TXXGXS | \ 58 XGE_HAL_GEN_INTR_RXXGXS | \ 59 XGE_HAL_GEN_INTR_MC) 60 61 u64 general_int_mask; 62 63 u8 unused0[0x100 - 0x10]; 64 65 u64 sw_reset; 66 67/* XGXS must be removed from reset only once. */ 68#define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8) 69#define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8) 70#define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8) 71#define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8) 72#define XGE_HAL_SW_RESET_ALL (XGE_HAL_SW_RESET_XENA | \ 73 XGE_HAL_SW_RESET_FLASH | \ 74 XGE_HAL_SW_RESET_EOI | \ 75 XGE_HAL_SW_RESET_XGXS) 76 77/* The SW_RESET register must read this value after a successful reset. */ 78#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN) 79#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL 80#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL 81#else 82#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL 83#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL 84#endif 85 86 87 u64 adapter_status; 88#define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0) 89#define XGE_HAL_ADAPTER_STATUS_RDMA_READY BIT(1) 90#define XGE_HAL_ADAPTER_STATUS_PFC_READY BIT(2) 91#define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3) 92#define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT BIT(5) 93#define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6) 94#define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7) 95#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) 96#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8) 97#define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 98 99#define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) 100#define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY BIT(24) 101#define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY BIT(25) 102#define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK BIT(30) 103#define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK BIT(31) 104 105 u64 adapter_control; 106#define XGE_HAL_ADAPTER_CNTL_EN BIT(7) 107#define XGE_HAL_ADAPTER_EOI_TX_ON BIT(15) 108#define XGE_HAL_ADAPTER_LED_ON BIT(23) 109#define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4) 110#define XGE_HAL_ADAPTER_WAIT_INT BIT(48) 111#define XGE_HAL_ADAPTER_ECC_EN BIT(55) 112 113 u64 serr_source; 114#define XGE_HAL_SERR_SOURCE_PIC BIT(0) 115#define XGE_HAL_SERR_SOURCE_TXDMA BIT(1) 116#define XGE_HAL_SERR_SOURCE_RXDMA BIT(2) 117#define XGE_HAL_SERR_SOURCE_MAC BIT(3) 118#define XGE_HAL_SERR_SOURCE_MC BIT(4) 119#define XGE_HAL_SERR_SOURCE_XGXS BIT(5) 120#define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \ 121 XGE_HAL_SERR_SOURCE_TXDMA | \ 122 XGE_HAL_SERR_SOURCE_RXDMA | \ 123 XGE_HAL_SERR_SOURCE_MAC | \ 124 XGE_HAL_SERR_SOURCE_MC | \ 125 XGE_HAL_SERR_SOURCE_XGXS) 126 127 u64 pci_info; 128#define XGE_HAL_PCI_INFO vBIT(0xF,0,4) 129#define XGE_HAL_PCI_32_BIT BIT(8) 130 131 u8 unused0_1[0x160 - 0x128]; 132 133 u64 ric_status; 134 135 u8 unused0_2[0x558 - 0x168]; 136 137 u64 mbist_status; 138 139 u8 unused0_3[0x800 - 0x560]; 140 141/* PCI-X Controller registers */ 142 u64 pic_int_status; 143 u64 pic_int_mask; 144#define XGE_HAL_PIC_INT_TX BIT(0) 145#define XGE_HAL_PIC_INT_FLSH BIT(1) 146#define XGE_HAL_PIC_INT_MDIO BIT(2) 147#define XGE_HAL_PIC_INT_IIC BIT(3) 148#define XGE_HAL_PIC_INT_MISC BIT(4) 149#define XGE_HAL_PIC_INT_RX BIT(32) 150 151 u64 txpic_int_reg; 152#define XGE_HAL_TXPIC_INT_SCHED_INTR BIT(42) 153 u64 txpic_int_mask; 154#define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0) 155#define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR BIT(1) 156#define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8) 157#define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9) 158#define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR BIT(10) 159#define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11) 160#define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR BIT(13) 161#define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR BIT(14) 162#define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR BIT(15) 163#define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21) 164#define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23) 165#define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR BIT(48) 166#define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR BIT(50) 167/* 168#define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52) 169#define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54) 170#define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58) 171*/ 172 u64 txpic_alarms; 173 u64 rxpic_int_reg; 174#define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0) 175#define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR BIT(44) 176#define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR BIT(55) 177 u64 rxpic_int_mask; 178 u64 rxpic_alarms; 179 180 u64 flsh_int_reg; 181 u64 flsh_int_mask; 182#define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63) 183#define XGE_HAL_PIC_FLSH_INT_REG_ERR BIT(62) 184 u64 flash_alarms; 185 186 u64 mdio_int_reg; 187 u64 mdio_int_mask; 188#define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0) 189#define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR BIT(8) 190#define XGE_HAL_MDIO_INT_REG_LASI BIT(39) 191 u64 mdio_alarms; 192 193 u64 iic_int_reg; 194 u64 iic_int_mask; 195#define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR BIT(4) 196#define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR BIT(5) 197#define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR BIT(6) 198#define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR BIT(7) 199#define XGE_HAL_IIC_INT_REG_ACK_ERR BIT(8) 200 u64 iic_alarms; 201 202 u64 msi_pending_reg; 203 204 u64 misc_int_reg; 205#define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0) 206#define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1) 207#define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2) 208 u64 misc_int_mask; 209 u64 misc_alarms; 210 211 u64 msi_triggered_reg; 212 213 u64 xfp_gpio_int_reg; 214 u64 xfp_gpio_int_mask; 215 u64 xfp_alarms; 216 217 u8 unused5[0x8E0 - 0x8C8]; 218 219 u64 tx_traffic_int; 220#define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n) 221 u64 tx_traffic_mask; 222 223 u64 rx_traffic_int; 224#define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n) 225 u64 rx_traffic_mask; 226 227/* PIC Control registers */ 228 u64 pic_control; 229#define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0) 230#define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT BIT(1) 231#define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4) 232 233 u64 swapper_ctrl; 234#define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0) 235#define XGE_HAL_SWAPPER_CTRL_PIF_R_SE BIT(1) 236#define XGE_HAL_SWAPPER_CTRL_PIF_W_FE BIT(8) 237#define XGE_HAL_SWAPPER_CTRL_PIF_W_SE BIT(9) 238#define XGE_HAL_SWAPPER_CTRL_RTH_FE BIT(10) 239#define XGE_HAL_SWAPPER_CTRL_RTH_SE BIT(11) 240#define XGE_HAL_SWAPPER_CTRL_TXP_FE BIT(16) 241#define XGE_HAL_SWAPPER_CTRL_TXP_SE BIT(17) 242#define XGE_HAL_SWAPPER_CTRL_TXD_R_FE BIT(18) 243#define XGE_HAL_SWAPPER_CTRL_TXD_R_SE BIT(19) 244#define XGE_HAL_SWAPPER_CTRL_TXD_W_FE BIT(20) 245#define XGE_HAL_SWAPPER_CTRL_TXD_W_SE BIT(21) 246#define XGE_HAL_SWAPPER_CTRL_TXF_R_FE BIT(22) 247#define XGE_HAL_SWAPPER_CTRL_TXF_R_SE BIT(23) 248#define XGE_HAL_SWAPPER_CTRL_RXD_R_FE BIT(32) 249#define XGE_HAL_SWAPPER_CTRL_RXD_R_SE BIT(33) 250#define XGE_HAL_SWAPPER_CTRL_RXD_W_FE BIT(34) 251#define XGE_HAL_SWAPPER_CTRL_RXD_W_SE BIT(35) 252#define XGE_HAL_SWAPPER_CTRL_RXF_W_FE BIT(36) 253#define XGE_HAL_SWAPPER_CTRL_RXF_W_SE BIT(37) 254#define XGE_HAL_SWAPPER_CTRL_XMSI_FE BIT(40) 255#define XGE_HAL_SWAPPER_CTRL_XMSI_SE BIT(41) 256#define XGE_HAL_SWAPPER_CTRL_STATS_FE BIT(48) 257#define XGE_HAL_SWAPPER_CTRL_STATS_SE BIT(49) 258 259 u64 pif_rd_swapper_fb; 260#define XGE_HAL_IF_RD_SWAPPER_FB 0x0123456789ABCDEFULL 261 262 u64 scheduled_int_ctrl; 263#define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0) 264#define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1) 265#define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) 266#define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32) 267#define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL 268 269 270 u64 txreqtimeout; 271#define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32) 272#define XGE_HAL_TXREQTO_EN BIT(63) 273 274 u64 statsreqtimeout; 275#define XGE_HAL_STATREQTO_VAL(n) TBD 276#define XGE_HAL_STATREQTO_EN BIT(63) 277 278 u64 read_retry_delay; 279 u64 read_retry_acceleration; 280 u64 write_retry_delay; 281 u64 write_retry_acceleration; 282 283 u64 xmsi_control; 284#define XGE_HAL_XMSI_EN BIT(0) 285#define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1) 286#define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3) 287 288 u64 xmsi_access; 289#define XGE_HAL_XMSI_WR_RDN BIT(7) 290#define XGE_HAL_XMSI_STROBE BIT(15) 291#define XGE_HAL_XMSI_NO(val) vBIT(val,26,6) 292 293 u64 xmsi_address; 294 u64 xmsi_data; 295 296 u64 rx_mat; 297#define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8) 298 299 u8 unused6[0x8]; 300 301 u64 tx_mat[8]; 302#define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8) 303 304 u64 xmsi_mask_reg; 305 306 /* Automated statistics collection */ 307 u64 stat_byte_cnt; 308 u64 stat_cfg; 309#define XGE_HAL_STAT_CFG_STAT_EN BIT(0) 310#define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1) 311#define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8) 312#define XGE_HAL_STAT_CFG_STAT_RO BIT(9) 313#define XGE_HAL_XENA_PER_SEC 0x208d5 314#define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32) 315 316 u64 stat_addr; 317 318 /* General Configuration */ 319 u64 mdio_control; 320#define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16) 321#define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5) 322#define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5) 323#define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16) 324#define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4) 325#define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2) 326#define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n) ((n>>16)&0xFFFF) 327#define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR 0x01 328#define XGE_HAL_MDIO_DOM_REG_ADDR 0xA100 329#define XGE_HAL_MDIO_ALARM_FLAGS_ADDR 0xA070 330#define XGE_HAL_MDIO_WARN_FLAGS_ADDR 0xA074 331#define XGE_HAL_MDIO_CTRL_START 0xE 332#define XGE_HAL_MDIO_OP_ADDRESS 0x0 333#define XGE_HAL_MDIO_OP_WRITE 0x1 334#define XGE_HAL_MDIO_OP_READ 0x3 335#define XGE_HAL_MDIO_OP_READ_POST_INCREMENT 0x2 336#define XGE_HAL_MDIO_ALARM_TEMPHIGH 0x0080 337#define XGE_HAL_MDIO_ALARM_TEMPLOW 0x0040 338#define XGE_HAL_MDIO_ALARM_BIASHIGH 0x0008 339#define XGE_HAL_MDIO_ALARM_BIASLOW 0x0004 340#define XGE_HAL_MDIO_ALARM_POUTPUTHIGH 0x0002 341#define XGE_HAL_MDIO_ALARM_POUTPUTLOW 0x0001 342#define XGE_HAL_MDIO_WARN_TEMPHIGH 0x0080 343#define XGE_HAL_MDIO_WARN_TEMPLOW 0x0040 344#define XGE_HAL_MDIO_WARN_BIASHIGH 0x0008 345#define XGE_HAL_MDIO_WARN_BIASLOW 0x0004 346#define XGE_HAL_MDIO_WARN_POUTPUTHIGH 0x0002 347#define XGE_HAL_MDIO_WARN_POUTPUTLOW 0x0001 348 349 u64 dtx_control; 350 351 u64 i2c_control; 352#define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) 353#define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) 354#define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) 355#define XGE_HAL_I2C_CONTROL_READ BIT(24) 356#define XGE_HAL_I2C_CONTROL_NACK BIT(25) 357#define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4) 358#define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) 359#define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) 360#define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) 361 362 u64 beacon_control; 363 u64 misc_control; 364#define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3) 365#define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1) 366#define XGE_HAL_MISC_CONTROL_LINK_FAULT BIT(0) 367 368 u64 xfb_control; 369 u64 gpio_control; 370#define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8) 371 372 u64 txfifo_dw_mask; 373 u64 split_table_line_no; 374 u64 sc_timeout; 375 u64 pic_control_2; 376#define XGE_HAL_TXD_WRITE_BC(n) vBIT(n, 13, 3) 377 u64 ini_dperr_ctrl; 378 u64 wreq_split_mask; 379 u64 qw_per_rxd; 380 u8 unused7[0x300 - 0x250]; 381 382 u64 pic_status; 383 u64 txp_status; 384 u64 txp_err_context; 385 u64 spdm_bir_offset; 386#define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \ 387 (u8)(spdm_bir_offset >> 61) 388#define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \ 389 (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF) 390 u64 spdm_overwrite; 391#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \ 392 (u8)((spdm_overwrite >> 48) & 0xff) 393#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \ 394 (u8)((spdm_overwrite >> 40) & 0x3) 395#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \ 396 (u8)((spdm_overwrite >> 32) & 0x7) 397 u64 cfg_addr_on_dperr; 398 u64 pif_addr_on_dperr; 399 u64 tags_in_use; 400 u64 rd_req_types; 401 u64 split_table_line; 402 u64 unxp_split_add_ph; 403 u64 unexp_split_attr_ph; 404 u64 split_message; 405 u64 spdm_structure; 406#define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure) (u16)(spdm_structure >> 48) 407#define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \ 408 (u8)((spdm_structure >> 40) & 0xff) 409#define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \ 410 (u8)((spdm_structure >> 32) & 0xff) 411 412 u64 txdw_ptr_cnt_0; 413 u64 txdw_ptr_cnt_1; 414 u64 txdw_ptr_cnt_2; 415 u64 txdw_ptr_cnt_3; 416 u64 txdw_ptr_cnt_4; 417 u64 txdw_ptr_cnt_5; 418 u64 txdw_ptr_cnt_6; 419 u64 txdw_ptr_cnt_7; 420 u64 rxdw_cnt_ring_0; 421 u64 rxdw_cnt_ring_1; 422 u64 rxdw_cnt_ring_2; 423 u64 rxdw_cnt_ring_3; 424 u64 rxdw_cnt_ring_4; 425 u64 rxdw_cnt_ring_5; 426 u64 rxdw_cnt_ring_6; 427 u64 rxdw_cnt_ring_7; 428 429 u8 unused8[0x410]; 430 431/* TxDMA registers */ 432 u64 txdma_int_status; 433 u64 txdma_int_mask; 434#define XGE_HAL_TXDMA_PFC_INT BIT(0) 435#define XGE_HAL_TXDMA_TDA_INT BIT(1) 436#define XGE_HAL_TXDMA_PCC_INT BIT(2) 437#define XGE_HAL_TXDMA_TTI_INT BIT(3) 438#define XGE_HAL_TXDMA_LSO_INT BIT(4) 439#define XGE_HAL_TXDMA_TPA_INT BIT(5) 440#define XGE_HAL_TXDMA_SM_INT BIT(6) 441 u64 pfc_err_reg; 442#define XGE_HAL_PFC_ECC_SG_ERR BIT(7) 443#define XGE_HAL_PFC_ECC_DB_ERR BIT(15) 444#define XGE_HAL_PFC_SM_ERR_ALARM BIT(23) 445#define XGE_HAL_PFC_MISC_0_ERR BIT(31) 446#define XGE_HAL_PFC_MISC_1_ERR BIT(32) 447#define XGE_HAL_PFC_PCIX_ERR BIT(39) 448 u64 pfc_err_mask; 449 u64 pfc_err_alarm; 450 451 u64 tda_err_reg; 452#define XGE_HAL_TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) 453#define XGE_HAL_TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) 454#define XGE_HAL_TDA_SM0_ERR_ALARM BIT(22) 455#define XGE_HAL_TDA_SM1_ERR_ALARM BIT(23) 456#define XGE_HAL_TDA_PCIX_ERR BIT(39) 457 u64 tda_err_mask; 458 u64 tda_err_alarm; 459 460 u64 pcc_err_reg; 461#define XGE_HAL_PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8) 462#define XGE_HAL_PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8) 463#define XGE_HAL_PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8) 464#define XGE_HAL_PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8) 465#define XGE_HAL_PCC_SM_ERR_ALARM vBIT(0xff,32,8) 466#define XGE_HAL_PCC_WR_ERR_ALARM vBIT(0xff,40,8) 467#define XGE_HAL_PCC_N_SERR vBIT(0xff,48,8) 468#define XGE_HAL_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 469#define XGE_HAL_PCC_6_COF_OV_ERR BIT(56) 470#define XGE_HAL_PCC_7_COF_OV_ERR BIT(57) 471#define XGE_HAL_PCC_6_LSO_OV_ERR BIT(58) 472#define XGE_HAL_PCC_7_LSO_OV_ERR BIT(59) 473 u64 pcc_err_mask; 474 u64 pcc_err_alarm; 475 476 u64 tti_err_reg; 477#define XGE_HAL_TTI_ECC_SG_ERR BIT(7) 478#define XGE_HAL_TTI_ECC_DB_ERR BIT(15) 479#define XGE_HAL_TTI_SM_ERR_ALARM BIT(23) 480 u64 tti_err_mask; 481 u64 tti_err_alarm; 482 483 u64 lso_err_reg; 484#define XGE_HAL_LSO6_SEND_OFLOW BIT(12) 485#define XGE_HAL_LSO7_SEND_OFLOW BIT(13) 486#define XGE_HAL_LSO6_ABORT BIT(14) 487#define XGE_HAL_LSO7_ABORT BIT(15) 488#define XGE_HAL_LSO6_SM_ERR_ALARM BIT(22) 489#define XGE_HAL_LSO7_SM_ERR_ALARM BIT(23) 490 u64 lso_err_mask; 491 u64 lso_err_alarm; 492 493 u64 tpa_err_reg; 494#define XGE_HAL_TPA_TX_FRM_DROP BIT(7) 495#define XGE_HAL_TPA_SM_ERR_ALARM BIT(23) 496 u64 tpa_err_mask; 497 u64 tpa_err_alarm; 498 499 u64 sm_err_reg; 500#define XGE_HAL_SM_SM_ERR_ALARM BIT(15) 501 u64 sm_err_mask; 502 u64 sm_err_alarm; 503 504 u8 unused9[0x100 - 0xB8]; 505 506/* TxDMA arbiter */ 507 u64 tx_dma_wrap_stat; 508 509/* Tx FIFO controller */ 510#define XGE_HAL_X_MAX_FIFOS 8 511#define XGE_HAL_X_FIFO_MAX_LEN 0x1FFF /*8191 */ 512 u64 tx_fifo_partition_0; 513#define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0) 514#define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) 515#define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) 516#define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) 517#define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) 518 519 u64 tx_fifo_partition_1; 520#define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) 521#define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) 522#define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) 523#define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) 524 525 u64 tx_fifo_partition_2; 526#define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) 527#define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) 528#define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) 529#define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) 530 531 u64 tx_fifo_partition_3; 532#define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) 533#define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) 534#define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) 535#define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) 536 537#define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */ 538#define XGE_HAL_TX_FIFO_PARTITION_PRI_1 1 539#define XGE_HAL_TX_FIFO_PARTITION_PRI_2 2 540#define XGE_HAL_TX_FIFO_PARTITION_PRI_3 3 541#define XGE_HAL_TX_FIFO_PARTITION_PRI_4 4 542#define XGE_HAL_TX_FIFO_PARTITION_PRI_5 5 543#define XGE_HAL_TX_FIFO_PARTITION_PRI_6 6 544#define XGE_HAL_TX_FIFO_PARTITION_PRI_7 7 /* lowest */ 545 546 u64 tx_w_round_robin_0; 547 u64 tx_w_round_robin_1; 548 u64 tx_w_round_robin_2; 549 u64 tx_w_round_robin_3; 550 u64 tx_w_round_robin_4; 551 552 u64 tti_command_mem; 553#define XGE_HAL_TTI_CMD_MEM_WE BIT(7) 554#define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 555#define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15) 556#define XGE_HAL_TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) 557 558 u64 tti_data1_mem; 559#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) 560#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) 561#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38) 562#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39) 563#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) 564#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) 565#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) 566 567 u64 tti_data2_mem; 568#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) 569#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) 570#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) 571#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) 572 573/* Tx Protocol assist */ 574 u64 tx_pa_cfg; 575#define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1) 576#define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 577#define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 578#define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6) 579 580/* Recent add, used only debug purposes. */ 581 u64 pcc_enable; 582 583 u64 pfc_monitor_0; 584 u64 pfc_monitor_1; 585 u64 pfc_monitor_2; 586 u64 pfc_monitor_3; 587 u64 txd_ownership_ctrl; 588 u64 pfc_read_cntrl; 589 u64 pfc_read_data; 590 591 u8 unused10[0x1700 - 0x11B0]; 592 593 u64 txdma_debug_ctrl; 594 595 u8 unused11[0x1800 - 0x1708]; 596 597/* RxDMA Registers */ 598 u64 rxdma_int_status; 599#define XGE_HAL_RXDMA_RC_INT BIT(0) 600#define XGE_HAL_RXDMA_RPA_INT BIT(1) 601#define XGE_HAL_RXDMA_RDA_INT BIT(2) 602#define XGE_HAL_RXDMA_RTI_INT BIT(3) 603 604 u64 rxdma_int_mask; 605#define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0) 606#define XGE_HAL_RXDMA_INT_RPA_INT_M BIT(1) 607#define XGE_HAL_RXDMA_INT_RDA_INT_M BIT(2) 608#define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3) 609 610 u64 rda_err_reg; 611#define XGE_HAL_RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) 612#define XGE_HAL_RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) 613#define XGE_HAL_RDA_FRM_ECC_SG_ERR BIT(23) 614#define XGE_HAL_RDA_FRM_ECC_DB_N_AERR BIT(31) 615#define XGE_HAL_RDA_SM1_ERR_ALARM BIT(38) 616#define XGE_HAL_RDA_SM0_ERR_ALARM BIT(39) 617#define XGE_HAL_RDA_MISC_ERR BIT(47) 618#define XGE_HAL_RDA_PCIX_ERR BIT(55) 619#define XGE_HAL_RDA_RXD_ECC_DB_SERR BIT(63) 620 u64 rda_err_mask; 621 u64 rda_err_alarm; 622 623 u64 rc_err_reg; 624#define XGE_HAL_RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) 625#define XGE_HAL_RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) 626#define XGE_HAL_RC_FTC_ECC_SG_ERR BIT(23) 627#define XGE_HAL_RC_FTC_ECC_DB_ERR BIT(31) 628#define XGE_HAL_RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) 629#define XGE_HAL_RC_FTC_SM_ERR_ALARM BIT(47) 630#define XGE_HAL_RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) 631 u64 rc_err_mask; 632 u64 rc_err_alarm; 633 634 u64 prc_pcix_err_reg; 635#define XGE_HAL_PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8) 636#define XGE_HAL_PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8) 637#define XGE_HAL_PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8) 638#define XGE_HAL_PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8) 639#define XGE_HAL_PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8) 640#define XGE_HAL_PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8) 641 u64 prc_pcix_err_mask; 642 u64 prc_pcix_err_alarm; 643 644 u64 rpa_err_reg; 645#define XGE_HAL_RPA_ECC_SG_ERR BIT(7) 646#define XGE_HAL_RPA_ECC_DB_ERR BIT(15) 647#define XGE_HAL_RPA_FLUSH_REQUEST BIT(22) 648#define XGE_HAL_RPA_SM_ERR_ALARM BIT(23) 649#define XGE_HAL_RPA_CREDIT_ERR BIT(31) 650 u64 rpa_err_mask; 651 u64 rpa_err_alarm; 652 653 u64 rti_err_reg; 654#define XGE_HAL_RTI_ECC_SG_ERR BIT(7) 655#define XGE_HAL_RTI_ECC_DB_ERR BIT(15) 656#define XGE_HAL_RTI_SM_ERR_ALARM BIT(23) 657 u64 rti_err_mask; 658 u64 rti_err_alarm; 659 660 u8 unused12[0x100 - 0x88]; 661 662/* DMA arbiter */ 663 u64 rx_queue_priority; 664#define XGE_HAL_RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) 665#define XGE_HAL_RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) 666#define XGE_HAL_RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) 667#define XGE_HAL_RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) 668#define XGE_HAL_RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) 669#define XGE_HAL_RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) 670#define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) 671#define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) 672 673#define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */ 674#define XGE_HAL_RX_QUEUE_PRI_1 1 675#define XGE_HAL_RX_QUEUE_PRI_2 2 676#define XGE_HAL_RX_QUEUE_PRI_3 3 677#define XGE_HAL_RX_QUEUE_PRI_4 4 678#define XGE_HAL_RX_QUEUE_PRI_5 5 679#define XGE_HAL_RX_QUEUE_PRI_6 6 680#define XGE_HAL_RX_QUEUE_PRI_7 7 /* lowest */ 681 682 u64 rx_w_round_robin_0; 683 u64 rx_w_round_robin_1; 684 u64 rx_w_round_robin_2; 685 u64 rx_w_round_robin_3; 686 u64 rx_w_round_robin_4; 687 688 /* Per-ring controller regs */ 689#define XGE_HAL_RX_MAX_RINGS 8 690 u64 prc_rxd0_n[XGE_HAL_RX_MAX_RINGS]; 691 u64 prc_ctrl_n[XGE_HAL_RX_MAX_RINGS]; 692#define XGE_HAL_PRC_CTRL_RC_ENABLED BIT(7) 693#define XGE_HAL_PRC_CTRL_RING_MODE (BIT(14)|BIT(15)) 694#define XGE_HAL_PRC_CTRL_RING_MODE_1 vBIT(0,14,2) 695#define XGE_HAL_PRC_CTRL_RING_MODE_3 vBIT(1,14,2) 696#define XGE_HAL_PRC_CTRL_RING_MODE_5 vBIT(2,14,2) 697#define XGE_HAL_PRC_CTRL_RING_MODE_x vBIT(3,14,2) 698#define XGE_HAL_PRC_CTRL_NO_SNOOP(n) vBIT(n,22,2) 699#define XGE_HAL_PRC_CTRL_RTH_DISABLE BIT(31) 700#define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT BIT(37) 701#define XGE_HAL_PRC_CTRL_GROUP_READS BIT(38) 702#define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) 703 704 u64 prc_alarm_action; 705#define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP BIT(3) 706#define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP BIT(7) 707#define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP BIT(11) 708#define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP BIT(15) 709#define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP BIT(19) 710#define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP BIT(23) 711#define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP BIT(27) 712#define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP BIT(31) 713#define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP BIT(35) 714#define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP BIT(39) 715#define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP BIT(43) 716#define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP BIT(47) 717#define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP BIT(51) 718#define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP BIT(55) 719#define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP BIT(59) 720#define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP BIT(63) 721 722/* Receive traffic interrupts */ 723 u64 rti_command_mem; 724#define XGE_HAL_RTI_CMD_MEM_WE BIT(7) 725#define XGE_HAL_RTI_CMD_MEM_STROBE BIT(15) 726#define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 727#define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15) 728#define XGE_HAL_RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) 729 730 u64 rti_data1_mem; 731#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) 732#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38) 733#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39) 734#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) 735#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) 736#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) 737 738 u64 rti_data2_mem; 739#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) 740#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) 741#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) 742#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) 743 744 u64 rx_pa_cfg; 745#define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR BIT(1) 746#define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 747#define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 748#define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n) vBIT(n,6,1) 749#define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1) 750 751 u8 unused13_0[0x8]; 752 753 u64 ring_bump_counter1; 754 u64 ring_bump_counter2; 755#define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4)))) 756 757 u8 unused13[0x700 - 0x1f0]; 758 759 u64 rxdma_debug_ctrl; 760 761 u8 unused14[0x2000 - 0x1f08]; 762 763/* Media Access Controller Register */ 764 u64 mac_int_status; 765 u64 mac_int_mask; 766#define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0) 767#define XGE_HAL_MAC_INT_STATUS_RMAC_INT BIT(1) 768 769 u64 mac_tmac_err_reg; 770#define XGE_HAL_TMAC_ECC_DB_ERR BIT(15) 771#define XGE_HAL_TMAC_TX_BUF_OVRN BIT(23) 772#define XGE_HAL_TMAC_TX_CRI_ERR BIT(31) 773#define XGE_HAL_TMAC_TX_SM_ERR BIT(39) 774 u64 mac_tmac_err_mask; 775 u64 mac_tmac_err_alarm; 776 777 u64 mac_rmac_err_reg; 778#define XGE_HAL_RMAC_RX_BUFF_OVRN BIT(0) 779#define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR BIT(0) 780#define XGE_HAL_RMAC_RTS_ECC_DB_ERR BIT(0) 781#define XGE_HAL_RMAC_ECC_DB_ERR BIT(0) 782#define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR BIT(0) 783#define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(0) 784#define XGE_HAL_RMAC_RX_SM_ERR BIT(39) 785 u64 mac_rmac_err_mask; 786 u64 mac_rmac_err_alarm; 787 788 u8 unused15[0x100 - 0x40]; 789 790 u64 mac_cfg; 791#define XGE_HAL_MAC_CFG_TMAC_ENABLE BIT(0) 792#define XGE_HAL_MAC_CFG_RMAC_ENABLE BIT(1) 793#define XGE_HAL_MAC_CFG_LAN_NOT_WAN BIT(2) 794#define XGE_HAL_MAC_CFG_TMAC_LOOPBACK BIT(3) 795#define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD BIT(4) 796#define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS BIT(5) 797#define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD BIT(6) 798#define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE BIT(7) 799#define XGE_HAL_MAC_RMAC_DISCARD_PFRM BIT(8) 800#define XGE_HAL_MAC_RMAC_BCAST_ENABLE BIT(9) 801#define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE BIT(10) 802#define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) 803 804 u64 tmac_avg_ipg; 805#define XGE_HAL_TMAC_AVG_IPG(val) vBIT(val,0,8) 806 807 u64 rmac_max_pyld_len; 808#define XGE_HAL_RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) 809 810 u64 rmac_err_cfg; 811#define XGE_HAL_RMAC_ERR_FCS BIT(0) 812#define XGE_HAL_RMAC_ERR_FCS_ACCEPT BIT(1) 813#define XGE_HAL_RMAC_ERR_TOO_LONG BIT(1) 814#define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT BIT(1) 815#define XGE_HAL_RMAC_ERR_RUNT BIT(2) 816#define XGE_HAL_RMAC_ERR_RUNT_ACCEPT BIT(2) 817#define XGE_HAL_RMAC_ERR_LEN_MISMATCH BIT(3) 818#define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3) 819 820 u64 rmac_cfg_key; 821#define XGE_HAL_RMAC_CFG_KEY(val) vBIT(val,0,16) 822 823#define XGE_HAL_MAX_MAC_ADDRESSES 64 824#define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET 63 825#define XGE_HAL_MAX_MAC_ADDRESSES_HERC 256 826#define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET_HERC 255 827 828 u64 rmac_addr_cmd_mem; 829#define XGE_HAL_RMAC_ADDR_CMD_MEM_WE BIT(7) 830#define XGE_HAL_RMAC_ADDR_CMD_MEM_RD 0 831#define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15) 832#define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15) 833#define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) 834 835 u64 rmac_addr_data0_mem; 836#define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) 837#define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER BIT(48) 838 839 u64 rmac_addr_data1_mem; 840#define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) 841 842 u8 unused16[0x8]; 843 844/* 845 u64 rmac_addr_cfg; 846#define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) 847#define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) 848#define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48 849#define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 850*/ 851 u64 tmac_ipg_cfg; 852 853 u64 rmac_pause_cfg; 854#define XGE_HAL_RMAC_PAUSE_GEN_EN BIT(0) 855#define XGE_HAL_RMAC_PAUSE_RCV_EN BIT(1) 856#define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) 857#define XGE_HAL_RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) 858 859 u64 rmac_red_cfg; 860 861 u64 rmac_red_rate_q0q3; 862 u64 rmac_red_rate_q4q7; 863 864 u64 mac_link_util; 865#define XGE_HAL_MAC_TX_LINK_UTIL vBIT(0xFE,1,7) 866#define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) 867#define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) 868#define XGE_HAL_MAC_RX_LINK_UTIL vBIT(0xFE,33,7) 869#define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) 870#define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) 871 872#define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \ 873 XGE_HAL_MAC_RX_LINK_UTIL_DISABLE) 874 875 u64 rmac_invalid_ipg; 876 877/* rx traffic steering */ 878#define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) 879 u64 rts_frm_len_n[8]; 880 881 u64 rts_qos_steering; 882 883#define XGE_HAL_MAX_DIX_MAP 4 884 u64 rts_dix_map_n[XGE_HAL_MAX_DIX_MAP]; 885#define XGE_HAL_RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) 886#define XGE_HAL_RTS_DIX_MAP_SCW(val) BIT(val,21) 887 888 u64 rts_q_alternates; 889 u64 rts_default_q; 890#define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3) 891 892 u64 rts_ctrl; 893#define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI BIT(2) 894#define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL BIT(3) 895#define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7) 896 897 u64 rts_pn_cam_ctrl; 898#define XGE_HAL_RTS_PN_CAM_CTRL_WE BIT(7) 899#define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15) 900#define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15) 901#define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) 902 u64 rts_pn_cam_data; 903#define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT BIT(7) 904#define XGE_HAL_RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) 905#define XGE_HAL_RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) 906 907 u64 rts_ds_mem_ctrl; 908#define XGE_HAL_RTS_DS_MEM_CTRL_WE BIT(7) 909#define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15) 910#define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15) 911#define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) 912 u64 rts_ds_mem_data; 913#define XGE_HAL_RTS_DS_MEM_DATA(n) vBIT(n,0,8) 914 915 u8 unused16_1[0x308 - 0x220]; 916 917 u64 rts_vid_mem_ctrl; 918 u64 rts_vid_mem_data; 919 u64 rts_p0_p3_map; 920 u64 rts_p4_p7_map; 921 u64 rts_p8_p11_map; 922 u64 rts_p12_p15_map; 923 924 u64 rts_mac_cfg; 925#define XGE_HAL_RTS_MAC_SECT0_EN BIT(0) 926#define XGE_HAL_RTS_MAC_SECT1_EN BIT(1) 927#define XGE_HAL_RTS_MAC_SECT2_EN BIT(2) 928#define XGE_HAL_RTS_MAC_SECT3_EN BIT(3) 929#define XGE_HAL_RTS_MAC_SECT4_EN BIT(4) 930#define XGE_HAL_RTS_MAC_SECT5_EN BIT(5) 931#define XGE_HAL_RTS_MAC_SECT6_EN BIT(6) 932#define XGE_HAL_RTS_MAC_SECT7_EN BIT(7) 933 934 u8 unused16_2[0x380 - 0x340]; 935 936 u64 rts_rth_cfg; 937#define XGE_HAL_RTS_RTH_EN BIT(3) 938#define XGE_HAL_RTS_RTH_BUCKET_SIZE(n) vBIT(n,4,4) 939#define XGE_HAL_RTS_RTH_ALG_SEL_MS BIT(11) 940#define XGE_HAL_RTS_RTH_TCP_IPV4_EN BIT(15) 941#define XGE_HAL_RTS_RTH_UDP_IPV4_EN BIT(19) 942#define XGE_HAL_RTS_RTH_IPV4_EN BIT(23) 943#define XGE_HAL_RTS_RTH_TCP_IPV6_EN BIT(27) 944#define XGE_HAL_RTS_RTH_UDP_IPV6_EN BIT(31) 945#define XGE_HAL_RTS_RTH_IPV6_EN BIT(35) 946#define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN BIT(39) 947#define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN BIT(43) 948#define XGE_HAL_RTS_RTH_IPV6_EX_EN BIT(47) 949 950 u64 rts_rth_map_mem_ctrl; 951#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE BIT(7) 952#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE BIT(15) 953#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 954 955 u64 rts_rth_map_mem_data; 956#define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN BIT(3) 957#define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n) vBIT(n,5,3) 958 959 u64 rts_rth_spdm_mem_ctrl; 960#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE BIT(15) 961#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n,21,3) 962#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 963 964 u64 rts_rth_spdm_mem_data; 965 966 u64 rts_rth_jhash_cfg; 967#define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n) vBIT(n,0,32) 968#define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n) vBIT(n,32,32) 969 970 u64 rts_rth_hash_mask[5]; /* rth mask's 0...4 */ 971 u64 rts_rth_hash_mask_5; 972#define XGE_HAL_RTH_HASH_MASK_5(n) vBIT(n,0,32) 973 974 u64 rts_rth_status; 975#define XGE_HAL_RTH_STATUS_SPDM_USE_L4 BIT(3) 976 977 u8 unused17[0x400 - 0x3E8]; 978 979 u64 rmac_red_fine_q0q3; 980 u64 rmac_red_fine_q4q7; 981 u64 rmac_pthresh_cross; 982 u64 rmac_rthresh_cross; 983 u64 rmac_pnum_range[32]; 984 985 u64 rmac_mp_crc_0; 986 u64 rmac_mp_mask_a_0; 987 u64 rmac_mp_mask_b_0; 988 989 u64 rmac_mp_crc_1; 990 u64 rmac_mp_mask_a_1; 991 u64 rmac_mp_mask_b_1; 992 993 u64 rmac_mp_crc_2; 994 u64 rmac_mp_mask_a_2; 995 u64 rmac_mp_mask_b_2; 996 997 u64 rmac_mp_crc_3; 998 u64 rmac_mp_mask_a_3; 999 u64 rmac_mp_mask_b_3; 1000 1001 u64 rmac_mp_crc_4; 1002 u64 rmac_mp_mask_a_4; 1003 u64 rmac_mp_mask_b_4; 1004 1005 u64 rmac_mp_crc_5; 1006 u64 rmac_mp_mask_a_5; 1007 u64 rmac_mp_mask_b_5; 1008 1009 u64 rmac_mp_crc_6; 1010 u64 rmac_mp_mask_a_6; 1011 u64 rmac_mp_mask_b_6; 1012 1013 u64 rmac_mp_crc_7; 1014 u64 rmac_mp_mask_a_7; 1015 u64 rmac_mp_mask_b_7; 1016 1017 u64 mac_ctrl; 1018 u64 activity_control; 1019 1020 u8 unused17_2[0x700 - 0x5F0]; 1021 1022 u64 mac_debug_ctrl; 1023#define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL 1024 1025 u8 unused18[0x2800 - 0x2708]; 1026 1027/* memory controller registers */ 1028 u64 mc_int_status; 1029#define XGE_HAL_MC_INT_STATUS_MC_INT BIT(0) 1030 u64 mc_int_mask; 1031#define XGE_HAL_MC_INT_MASK_MC_INT BIT(0) 1032 1033 u64 mc_err_reg; 1034#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L BIT(2) /* non-Xena */ 1035#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U BIT(3) /* non-Xena */ 1036#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L BIT(4) /* non-Xena */ 1037#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U BIT(5) /* non-Xena */ 1038#define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L BIT(6) 1039#define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U BIT(7) 1040#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L BIT(10) /* non-Xena */ 1041#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U BIT(11) /* non-Xena */ 1042#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L BIT(12) /* non-Xena */ 1043#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U BIT(13) /* non-Xena */ 1044#define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L BIT(14) 1045#define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U BIT(15) 1046#define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 BIT(17) 1047#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) /* Xena: reset */ 1048#define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 BIT(19) 1049#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) /* Xena: reset */ 1050#define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22) 1051#define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23) 1052#define XGE_HAL_MC_ERR_REG_SM_ERR BIT(31) 1053#define XGE_HAL_MC_ERR_REG_PL_LOCK_N BIT(39) 1054 1055 u64 mc_err_mask; 1056 u64 mc_err_alarm; 1057 1058 u8 unused19[0x100 - 0x28]; 1059 1060/* MC configuration */ 1061 u64 rx_queue_cfg; 1062#define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) 1063#define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) 1064#define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) 1065#define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) 1066#define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) 1067#define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) 1068#define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) 1069#define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) 1070 1071 u64 mc_rldram_mrs; 1072#define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) 1073#define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47) 1074 1075 u64 mc_rldram_interleave; 1076 1077 u64 mc_pause_thresh_q0q3; 1078 u64 mc_pause_thresh_q4q7; 1079 1080 u64 mc_red_thresh_q[8]; 1081 1082 u8 unused20[0x200 - 0x168]; 1083 u64 mc_rldram_ref_per; 1084 u8 unused21[0x220 - 0x208]; 1085 u64 mc_rldram_test_ctrl; 1086#define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47) 1087#define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7) 1088#define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15) 1089#define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23) 1090#define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31) 1091 1092 u8 unused22[0x240 - 0x228]; 1093 u64 mc_rldram_test_add; 1094 u8 unused23[0x260 - 0x248]; 1095 u64 mc_rldram_test_d0; 1096 u8 unused24[0x280 - 0x268]; 1097 u64 mc_rldram_test_d1; 1098 u8 unused25[0x300 - 0x288]; 1099 u64 mc_rldram_test_d2; 1100 u8 unused26_1[0x2C00 - 0x2B08]; 1101 u64 mc_rldram_test_read_d0; 1102 u8 unused26_2[0x20 - 0x8]; 1103 u64 mc_rldram_test_read_d1; 1104 u8 unused26_3[0x40 - 0x28]; 1105 u64 mc_rldram_test_read_d2; 1106 u8 unused26_4[0x60 - 0x48]; 1107 u64 mc_rldram_test_add_bkg; 1108 u8 unused26_5[0x80 - 0x68]; 1109 u64 mc_rldram_test_d0_bkg; 1110 u8 unused26_6[0xD00 - 0xC88]; 1111 u64 mc_rldram_test_d1_bkg; 1112 u8 unused26_7[0x20 - 0x8]; 1113 u64 mc_rldram_test_d2_bkg; 1114 u8 unused26_8[0x40 - 0x28]; 1115 u64 mc_rldram_test_read_d0_bkg; 1116 u8 unused26_9[0x60 - 0x48]; 1117 u64 mc_rldram_test_read_d1_bkg; 1118 u8 unused26_10[0x80 - 0x68]; 1119 u64 mc_rldram_test_read_d2_bkg; 1120 u8 unused26_11[0xE00 - 0xD88]; 1121 u64 mc_rldram_generation; 1122 u8 unused26_12[0x20 - 0x8]; 1123 u64 mc_driver; 1124 u8 unused26_13[0x40 - 0x28]; 1125 u64 mc_rldram_ref_per_herc; 1126#define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n) vBIT(n, 0, 16) 1127 u8 unused26_14[0x660 - 0x648]; 1128 u64 mc_rldram_mrs_herc; 1129#define XGE_HAL_MC_RLDRAM_MRS(n) vBIT(n, 14, 17) 1130 u8 unused26_15[0x700 - 0x668]; 1131 u64 mc_debug_ctrl; 1132 1133 u8 unused27[0x3000 - 0x2f08]; 1134 1135/* XGXG */ 1136 /* XGXS control registers */ 1137 1138 u64 xgxs_int_status; 1139#define XGE_HAL_XGXS_INT_STATUS_TXGXS BIT(0) 1140#define XGE_HAL_XGXS_INT_STATUS_RXGXS BIT(1) 1141 u64 xgxs_int_mask; 1142#define XGE_HAL_XGXS_INT_MASK_TXGXS BIT(0) 1143#define XGE_HAL_XGXS_INT_MASK_RXGXS BIT(1) 1144 1145 u64 xgxs_txgxs_err_reg; 1146#define XGE_HAL_TXGXS_ECC_SG_ERR BIT(7) 1147#define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15) 1148#define XGE_HAL_TXGXS_ESTORE_UFLOW BIT(31) 1149#define XGE_HAL_TXGXS_TX_SM_ERR BIT(39) 1150 u64 xgxs_txgxs_err_mask; 1151 u64 xgxs_txgxs_err_alarm; 1152 1153 u64 xgxs_rxgxs_err_reg; 1154#define XGE_HAL_RXGXS_ESTORE_OFLOW BIT(7) 1155#define XGE_HAL_RXGXS_RX_SM_ERR BIT(39) 1156 u64 xgxs_rxgxs_err_mask; 1157 u64 xgxs_rxgxs_err_alarm; 1158 1159 u64 spi_err_reg; 1160 u64 spi_err_mask; 1161 u64 spi_err_alarm; 1162 1163 u8 unused28[0x100 - 0x58]; 1164 1165 u64 xgxs_cfg; 1166 u64 xgxs_status; 1167 1168 u64 xgxs_cfg_key; 1169 u64 xgxs_efifo_cfg; /* CHANGED */ 1170 u64 rxgxs_ber_0; /* CHANGED */ 1171 u64 rxgxs_ber_1; /* CHANGED */ 1172 1173 u64 spi_control; 1174 u64 spi_data; 1175 u64 spi_write_protect; 1176 1177 u8 unused29[0x80 - 0x48]; 1178 1179 u64 xgxs_cfg_1; 1180} xge_hal_pci_bar0_t; 1181 1182/* Using this strcture to calculate offsets */ 1183typedef struct xge_hal_pci_config_le_t { 1184 u16 vendor_id; // 0x00 1185 u16 device_id; // 0x02 1186 1187 u16 command; // 0x04 1188 u16 status; // 0x06 1189 1190 u8 revision; // 0x08 1191 u8 pciClass[3]; // 0x09 1192 1193 u8 cache_line_size; // 0x0c 1194 u8 latency_timer; // 0x0d 1195 u8 header_type; // 0x0e 1196 u8 bist; // 0x0f 1197 1198 u32 base_addr0_lo; // 0x10 1199 u32 base_addr0_hi; // 0x14 1200 1201 u32 base_addr1_lo; // 0x18 1202 u32 base_addr1_hi; // 0x1C 1203 1204 u32 not_Implemented1; // 0x20 1205 u32 not_Implemented2; // 0x24 1206 1207 u32 cardbus_cis_pointer; // 0x28 1208 1209 u16 subsystem_vendor_id; // 0x2c 1210 u16 subsystem_id; // 0x2e 1211 1212 u32 rom_base; // 0x30 1213 u8 capabilities_pointer; // 0x34 1214 u8 rsvd_35[3]; // 0x35 1215 u32 rsvd_38; // 0x38 1216 1217 u8 interrupt_line; // 0x3c 1218 u8 interrupt_pin; // 0x3d 1219 u8 min_grant; // 0x3e 1220 u8 max_latency; // 0x3f 1221 1222 u8 msi_cap_id; // 0x40 1223 u8 msi_next_ptr; // 0x41 1224 u16 msi_control; // 0x42 1225 u32 msi_lower_address; // 0x44 1226 u32 msi_higher_address; // 0x48 1227 u16 msi_data; // 0x4c 1228 u16 msi_unused; // 0x4e 1229 1230 u8 vpd_cap_id; // 0x50 1231 u8 vpd_next_cap; // 0x51 1232 u16 vpd_addr; // 0x52 1233 u32 vpd_data; // 0x54 1234 1235 u8 rsvd_b0[8]; // 0x58 1236 1237 u8 pcix_cap; // 0x60 1238 u8 pcix_next_cap; // 0x61 1239 u16 pcix_command; // 0x62 1240 1241 u32 pcix_status; // 0x64 1242 1243 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1244} xge_hal_pci_config_le_t; // 0x100 1245 1246typedef struct xge_hal_pci_config_t { 1247#ifdef XGE_OS_HOST_BIG_ENDIAN 1248 u16 device_id; // 0x02 1249 u16 vendor_id; // 0x00 1250 1251 u16 status; // 0x06 1252 u16 command; // 0x04 1253 1254 u8 pciClass[3]; // 0x09 1255 u8 revision; // 0x08 1256 1257 u8 bist; // 0x0f 1258 u8 header_type; // 0x0e 1259 u8 latency_timer; // 0x0d 1260 u8 cache_line_size; // 0x0c 1261 1262 u32 base_addr0_lo; // 0x10 1263 u32 base_addr0_hi; // 0x14 1264 1265 u32 base_addr1_lo; // 0x18 1266 u32 base_addr1_hi; // 0x1C 1267 1268 u32 not_Implemented1; // 0x20 1269 u32 not_Implemented2; // 0x24 1270 1271 u32 cardbus_cis_pointer; // 0x28 1272 1273 u16 subsystem_id; // 0x2e 1274 u16 subsystem_vendor_id; // 0x2c 1275 1276 u32 rom_base; // 0x30 1277 u8 rsvd_35[3]; // 0x35 1278 u8 capabilities_pointer; // 0x34 1279 u32 rsvd_38; // 0x38 1280 1281 u8 max_latency; // 0x3f 1282 u8 min_grant; // 0x3e 1283 u8 interrupt_pin; // 0x3d 1284 u8 interrupt_line; // 0x3c 1285 1286 u16 msi_control; // 0x42 1287 u8 msi_next_ptr; // 0x41 1288 u8 msi_cap_id; // 0x40 1289 u32 msi_lower_address; // 0x44 1290 u32 msi_higher_address; // 0x48 1291 u16 msi_unused; // 0x4e 1292 u16 msi_data; // 0x4c 1293 1294 u16 vpd_addr; // 0x52 1295 u8 vpd_next_cap; // 0x51 1296 u8 vpd_cap_id; // 0x50 1297 u32 vpd_data; // 0x54 1298 1299 u8 rsvd_b0[8]; // 0x58 1300 1301 u16 pcix_command; // 0x62 1302 u8 pcix_next_cap; // 0x61 1303 u8 pcix_cap; // 0x60 1304 1305 u32 pcix_status; // 0x64 1306#else 1307 u16 vendor_id; // 0x00 1308 u16 device_id; // 0x02 1309 1310 u16 command; // 0x04 1311 u16 status; // 0x06 1312 1313 u8 revision; // 0x08 1314 u8 pciClass[3]; // 0x09 1315 1316 u8 cache_line_size; // 0x0c 1317 u8 latency_timer; // 0x0d 1318 u8 header_type; // 0x0e 1319 u8 bist; // 0x0f 1320 1321 u32 base_addr0_lo; // 0x10 1322 u32 base_addr0_hi; // 0x14 1323 1324 u32 base_addr1_lo; // 0x18 1325 u32 base_addr1_hi; // 0x1C 1326 1327 u32 not_Implemented1; // 0x20 1328 u32 not_Implemented2; // 0x24 1329 1330 u32 cardbus_cis_pointer; // 0x28 1331 1332 u16 subsystem_vendor_id; // 0x2c 1333 u16 subsystem_id; // 0x2e 1334 1335 u32 rom_base; // 0x30 1336 u8 capabilities_pointer; // 0x34 1337 u8 rsvd_35[3]; // 0x35 1338 u32 rsvd_38; // 0x38 1339 1340 u8 interrupt_line; // 0x3c 1341 u8 interrupt_pin; // 0x3d 1342 u8 min_grant; // 0x3e 1343 u8 max_latency; // 0x3f 1344 1345 u8 msi_cap_id; // 0x40 1346 u8 msi_next_ptr; // 0x41 1347 u16 msi_control; // 0x42 1348 u32 msi_lower_address; // 0x44 1349 u32 msi_higher_address; // 0x48 1350 u16 msi_data; // 0x4c 1351 u16 msi_unused; // 0x4e 1352 1353 u8 vpd_cap_id; // 0x50 1354 u8 vpd_next_cap; // 0x51 1355 u16 vpd_addr; // 0x52 1356 u32 vpd_data; // 0x54 1357 1358 u8 rsvd_b0[8]; // 0x58 1359 1360 u8 pcix_cap; // 0x60 1361 u8 pcix_next_cap; // 0x61 1362 u16 pcix_command; // 0x62 1363 1364 u32 pcix_status; // 0x64 1365 1366#endif 1367 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1368} xge_hal_pci_config_t; // 0x100 1369 1370#define XGE_HAL_REG_SPACE sizeof(xge_hal_pci_bar0_t) 1371#define XGE_HAL_EEPROM_SIZE (0x01 << 11) 1372 1373__EXTERN_END_DECLS 1374 1375#endif /* XGE_HAL_REGS_H */ 1376