pmc.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2008, Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: stable/11/sys/sys/pmc.h 330897 2018-03-14 03:19:51Z eadler $ 33 */ 34 35#ifndef _SYS_PMC_H_ 36#define _SYS_PMC_H_ 37 38#include <dev/hwpmc/pmc_events.h> 39 40#include <machine/pmc_mdep.h> 41#include <machine/profile.h> 42 43#define PMC_MODULE_NAME "hwpmc" 44#define PMC_NAME_MAX 64 /* HW counter name size */ 45#define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 46 47/* 48 * Kernel<->userland API version number [MMmmpppp] 49 * 50 * Major numbers are to be incremented when an incompatible change to 51 * the ABI occurs that older clients will not be able to handle. 52 * 53 * Minor numbers are incremented when a backwards compatible change 54 * occurs that allows older correct programs to run unchanged. For 55 * example, when support for a new PMC type is added. 56 * 57 * The patch version is incremented for every bug fix. 58 */ 59#define PMC_VERSION_MAJOR 0x03 60#define PMC_VERSION_MINOR 0x01 61#define PMC_VERSION_PATCH 0x0000 62 63#define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 64 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 65 66/* 67 * Kinds of CPUs known. 68 * 69 * We keep track of CPU variants that need to be distinguished in 70 * some way for PMC operations. CPU names are grouped by manufacturer 71 * and numbered sparsely in order to minimize changes to the ABI involved 72 * when new CPUs are added. 73 */ 74 75#define __PMC_CPUS() \ 76 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ 77 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 78 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \ 79 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \ 80 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \ 81 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \ 82 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \ 83 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \ 84 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \ 85 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 86 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 87 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 88 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 89 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 90 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 91 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 92 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 93 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 94 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 95 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 96 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 97 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 98 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 99 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ 100 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ 101 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ 102 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ 103 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ 104 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ 105 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ 106 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ 107 __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ 108 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 109 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ 110 __PMC_CPU(PPC_MPC85XX, 0x340, "Freescale PowerPC MPC85XX") \ 111 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 112 __PMC_CPU(GENERIC, 0x400, "Generic") \ 113 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ 114 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ 115 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ 116 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ 117 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ 118 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ 119 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ 120 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") 121 122enum pmc_cputype { 123#undef __PMC_CPU 124#define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 125 __PMC_CPUS() 126}; 127 128#define PMC_CPU_FIRST PMC_CPU_AMD_K7 129#define PMC_CPU_LAST PMC_CPU_GENERIC 130 131/* 132 * Classes of PMCs 133 */ 134 135#define __PMC_CLASSES() \ 136 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ 137 __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ 138 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ 139 __PMC_CLASS(P5, 0x03, "Intel Pentium counters") \ 140 __PMC_CLASS(P6, 0x04, "Intel Pentium Pro counters") \ 141 __PMC_CLASS(P4, 0x05, "Intel Pentium-IV counters") \ 142 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ 143 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ 144 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ 145 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ 146 __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ 147 __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \ 148 __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \ 149 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ 150 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ 151 __PMC_CLASS(SOFT, 0x0F, "Software events") \ 152 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ 153 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ 154 __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \ 155 __PMC_CLASS(E500, 0x13, "Freescale e500 class") 156 157enum pmc_class { 158#undef __PMC_CLASS 159#define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V, 160 __PMC_CLASSES() 161}; 162 163#define PMC_CLASS_FIRST PMC_CLASS_TSC 164#define PMC_CLASS_LAST PMC_CLASS_E500 165 166/* 167 * A PMC can be in the following states: 168 * 169 * Hardware states: 170 * DISABLED -- administratively prohibited from being used. 171 * FREE -- HW available for use 172 * Software states: 173 * ALLOCATED -- allocated 174 * STOPPED -- allocated, but not counting events 175 * RUNNING -- allocated, and in operation; 'pm_runcount' 176 * holds the number of CPUs using this PMC at 177 * a given instant 178 * DELETED -- being destroyed 179 */ 180 181#define __PMC_HWSTATES() \ 182 __PMC_STATE(DISABLED) \ 183 __PMC_STATE(FREE) 184 185#define __PMC_SWSTATES() \ 186 __PMC_STATE(ALLOCATED) \ 187 __PMC_STATE(STOPPED) \ 188 __PMC_STATE(RUNNING) \ 189 __PMC_STATE(DELETED) 190 191#define __PMC_STATES() \ 192 __PMC_HWSTATES() \ 193 __PMC_SWSTATES() 194 195enum pmc_state { 196#undef __PMC_STATE 197#define __PMC_STATE(S) PMC_STATE_##S, 198 __PMC_STATES() 199 __PMC_STATE(MAX) 200}; 201 202#define PMC_STATE_FIRST PMC_STATE_DISABLED 203#define PMC_STATE_LAST PMC_STATE_DELETED 204 205/* 206 * An allocated PMC may used as a 'global' counter or as a 207 * 'thread-private' one. Each such mode of use can be in either 208 * statistical sampling mode or in counting mode. Thus a PMC in use 209 * 210 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 211 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 212 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 213 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 214 * 215 * Statistical profiling modes rely on the PMC periodically delivering 216 * a interrupt to the CPU (when the configured number of events have 217 * been measured), so the PMC must have the ability to generate 218 * interrupts. 219 * 220 * In counting modes, the PMC counts its configured events, with the 221 * value of the PMC being read whenever needed by its owner process. 222 * 223 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 224 * to be thread private and count events only when the profiled thread 225 * actually executes on the CPU. 226 * 227 * The system-wide "global" modes keep the PMCs running all the time 228 * and are used to measure the behaviour of the whole system. 229 */ 230 231#define __PMC_MODES() \ 232 __PMC_MODE(SS, 0) \ 233 __PMC_MODE(SC, 1) \ 234 __PMC_MODE(TS, 2) \ 235 __PMC_MODE(TC, 3) 236 237enum pmc_mode { 238#undef __PMC_MODE 239#define __PMC_MODE(M,N) PMC_MODE_##M = N, 240 __PMC_MODES() 241}; 242 243#define PMC_MODE_FIRST PMC_MODE_SS 244#define PMC_MODE_LAST PMC_MODE_TC 245 246#define PMC_IS_COUNTING_MODE(mode) \ 247 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 248#define PMC_IS_SYSTEM_MODE(mode) \ 249 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 250#define PMC_IS_SAMPLING_MODE(mode) \ 251 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 252#define PMC_IS_VIRTUAL_MODE(mode) \ 253 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 254 255/* 256 * PMC row disposition 257 */ 258 259#define __PMC_DISPOSITIONS(N) \ 260 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 261 __PMC_DISP(FREE) /* free/available */ \ 262 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 263 __PMC_DISP(UNKNOWN) /* sentinel */ 264 265enum pmc_disp { 266#undef __PMC_DISP 267#define __PMC_DISP(D) PMC_DISP_##D , 268 __PMC_DISPOSITIONS() 269}; 270 271#define PMC_DISP_FIRST PMC_DISP_STANDALONE 272#define PMC_DISP_LAST PMC_DISP_THREAD 273 274/* 275 * Counter capabilities 276 * 277 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 278 */ 279 280#define __PMC_CAPS() \ 281 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 282 __PMC_CAP(USER, 1, "count user-mode events") \ 283 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 284 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 285 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 286 __PMC_CAP(READ, 5, "read PMC counter") \ 287 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 288 __PMC_CAP(INVERT, 7, "invert comparison sense") \ 289 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 290 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 291 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 292 __PMC_CAP(CASCADE, 11, "cascade counters") 293 294enum pmc_caps 295{ 296#undef __PMC_CAP 297#define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 298 __PMC_CAPS() 299}; 300 301#define PMC_CAP_FIRST PMC_CAP_INTERRUPT 302#define PMC_CAP_LAST PMC_CAP_CASCADE 303 304/* 305 * PMC Event Numbers 306 * 307 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 308 */ 309 310enum pmc_event { 311#undef __PMC_EV 312#undef __PMC_EV_BLOCK 313#define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 314#define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 315 __PMC_EVENTS() 316}; 317 318/* 319 * PMC SYSCALL INTERFACE 320 */ 321 322/* 323 * "PMC_OPS" -- these are the commands recognized by the kernel 324 * module, and are used when performing a system call from userland. 325 */ 326#define __PMC_OPS() \ 327 __PMC_OP(CONFIGURELOG, "Set log file") \ 328 __PMC_OP(FLUSHLOG, "Flush log file") \ 329 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 330 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 331 __PMC_OP(GETMODULEVERSION, "Get module version") \ 332 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 333 __PMC_OP(PMCADMIN, "Set PMC state") \ 334 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 335 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 336 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 337 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 338 __PMC_OP(PMCRELEASE, "Release a PMC") \ 339 __PMC_OP(PMCRW, "Read/Set a PMC") \ 340 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 341 __PMC_OP(PMCSTART, "Start a PMC") \ 342 __PMC_OP(PMCSTOP, "Stop a PMC") \ 343 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 344 __PMC_OP(CLOSELOG, "Close log file") \ 345 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") 346 347 348enum pmc_ops { 349#undef __PMC_OP 350#define __PMC_OP(N, D) PMC_OP_##N, 351 __PMC_OPS() 352}; 353 354 355/* 356 * Flags used in operations on PMCs. 357 */ 358 359#define PMC_F_FORCE 0x00000001 /*OP ADMIN force operation */ 360#define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 361#define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 362#define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 363#define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 364#define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 365#define PMC_F_KGMON 0x00000040 /*OP ALLOCATE kgmon(8) profiling */ 366/* V2 API */ 367#define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 368 369/* internal flags */ 370#define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 371#define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 372#define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 373 374#define PMC_CALLCHAIN_DEPTH_MAX 128 375 376#define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 377 378/* 379 * Cookies used to denote allocated PMCs, and the values of PMCs. 380 */ 381 382typedef uint32_t pmc_id_t; 383typedef uint64_t pmc_value_t; 384 385#define PMC_ID_INVALID (~ (pmc_id_t) 0) 386 387/* 388 * PMC IDs have the following format: 389 * 390 * +--------+----------+-----------+-----------+ 391 * | CPU | PMC MODE | PMC CLASS | ROW INDEX | 392 * +--------+----------+-----------+-----------+ 393 * 394 * where each field is 8 bits wide. Field 'CPU' is set to the 395 * requested CPU for system-wide PMCs or PMC_CPU_ANY for process-mode 396 * PMCs. Field 'PMC MODE' is the allocated PMC mode. Field 'PMC 397 * CLASS' is the class of the PMC. Field 'ROW INDEX' is the row index 398 * for the PMC. 399 * 400 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 401 * number of hardware PMCs on this cpu. 402 */ 403 404 405#define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 406#define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8) 407#define PMC_ID_TO_MODE(ID) (((ID) & 0xFF0000) >> 16) 408#define PMC_ID_TO_CPU(ID) (((ID) & 0xFF000000) >> 24) 409#define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 410 ((((CPU) & 0xFF) << 24) | (((MODE) & 0xFF) << 16) | \ 411 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF)) 412 413/* 414 * Data structures for system calls supported by the pmc driver. 415 */ 416 417/* 418 * OP PMCALLOCATE 419 * 420 * Allocate a PMC on the named CPU. 421 */ 422 423#define PMC_CPU_ANY ~0 424 425struct pmc_op_pmcallocate { 426 uint32_t pm_caps; /* PMC_CAP_* */ 427 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 428 enum pmc_class pm_class; /* class of PMC desired */ 429 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 430 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 431 enum pmc_mode pm_mode; /* desired mode */ 432 pmc_id_t pm_pmcid; /* [return] process pmc id */ 433 434 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 435}; 436 437/* 438 * OP PMCADMIN 439 * 440 * Set the administrative state (i.e., whether enabled or disabled) of 441 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 442 * absolute PMC number and need not have been first allocated by the 443 * calling process. 444 */ 445 446struct pmc_op_pmcadmin { 447 int pm_cpu; /* CPU# */ 448 uint32_t pm_flags; /* flags */ 449 int pm_pmc; /* PMC# */ 450 enum pmc_state pm_state; /* desired state */ 451}; 452 453/* 454 * OP PMCATTACH / OP PMCDETACH 455 * 456 * Attach/detach a PMC and a process. 457 */ 458 459struct pmc_op_pmcattach { 460 pmc_id_t pm_pmc; /* PMC to attach to */ 461 pid_t pm_pid; /* target process */ 462}; 463 464/* 465 * OP PMCSETCOUNT 466 * 467 * Set the sampling rate (i.e., the reload count) for statistical counters. 468 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 469 */ 470 471struct pmc_op_pmcsetcount { 472 pmc_value_t pm_count; /* initial/sample count */ 473 pmc_id_t pm_pmcid; /* PMC id to set */ 474}; 475 476 477/* 478 * OP PMCRW 479 * 480 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 481 * to have been previously allocated using PMCALLOCATE. 482 */ 483 484 485struct pmc_op_pmcrw { 486 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 487 pmc_id_t pm_pmcid; /* pmc id */ 488 pmc_value_t pm_value; /* new&returned value */ 489}; 490 491 492/* 493 * OP GETPMCINFO 494 * 495 * retrieve PMC state for a named CPU. The caller is expected to 496 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 497 * values. 498 */ 499 500struct pmc_info { 501 char pm_name[PMC_NAME_MAX]; /* pmc name */ 502 enum pmc_class pm_class; /* enum pmc_class */ 503 int pm_enabled; /* whether enabled */ 504 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 505 pid_t pm_ownerpid; /* owner, or -1 */ 506 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 507 enum pmc_event pm_event; /* current event */ 508 uint32_t pm_flags; /* current flags */ 509 pmc_value_t pm_reloadcount; /* sampling counters only */ 510}; 511 512struct pmc_op_getpmcinfo { 513 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 514 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 515}; 516 517 518/* 519 * OP GETCPUINFO 520 * 521 * Retrieve system CPU information. 522 */ 523 524 525struct pmc_classinfo { 526 enum pmc_class pm_class; /* class id */ 527 uint32_t pm_caps; /* counter capabilities */ 528 uint32_t pm_width; /* width of the PMC */ 529 uint32_t pm_num; /* number of PMCs in class */ 530}; 531 532struct pmc_op_getcpuinfo { 533 enum pmc_cputype pm_cputype; /* what kind of CPU */ 534 uint32_t pm_ncpu; /* max CPU number */ 535 uint32_t pm_npmc; /* #PMCs per CPU */ 536 uint32_t pm_nclass; /* #classes of PMCs */ 537 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 538}; 539 540/* 541 * OP CONFIGURELOG 542 * 543 * Configure a log file for writing system-wide statistics to. 544 */ 545 546struct pmc_op_configurelog { 547 int pm_flags; 548 int pm_logfd; /* logfile fd (or -1) */ 549}; 550 551/* 552 * OP GETDRIVERSTATS 553 * 554 * Retrieve pmc(4) driver-wide statistics. 555 */ 556 557struct pmc_op_getdriverstats { 558 unsigned int pm_intr_ignored; /* #interrupts ignored */ 559 unsigned int pm_intr_processed; /* #interrupts processed */ 560 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 561 unsigned int pm_syscalls; /* #syscalls */ 562 unsigned int pm_syscall_errors; /* #syscalls with errors */ 563 unsigned int pm_buffer_requests; /* #buffer requests */ 564 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ 565 unsigned int pm_log_sweeps; /* #sample buffer processing 566 passes */ 567}; 568 569/* 570 * OP RELEASE / OP START / OP STOP 571 * 572 * Simple operations on a PMC id. 573 */ 574 575struct pmc_op_simple { 576 pmc_id_t pm_pmcid; 577}; 578 579/* 580 * OP WRITELOG 581 * 582 * Flush the current log buffer and write 4 bytes of user data to it. 583 */ 584 585struct pmc_op_writelog { 586 uint32_t pm_userdata; 587}; 588 589/* 590 * OP GETMSR 591 * 592 * Retrieve the machine specific address associated with the allocated 593 * PMC. This number can be used subsequently with a read-performance-counter 594 * instruction. 595 */ 596 597struct pmc_op_getmsr { 598 uint32_t pm_msr; /* machine specific address */ 599 pmc_id_t pm_pmcid; /* allocated pmc id */ 600}; 601 602/* 603 * OP GETDYNEVENTINFO 604 * 605 * Retrieve a PMC dynamic class events list. 606 */ 607 608struct pmc_dyn_event_descr { 609 char pm_ev_name[PMC_NAME_MAX]; 610 enum pmc_event pm_ev_code; 611}; 612 613struct pmc_op_getdyneventinfo { 614 enum pmc_class pm_class; 615 unsigned int pm_nevent; 616 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 617}; 618 619#ifdef _KERNEL 620 621#include <sys/malloc.h> 622#include <sys/sysctl.h> 623#include <sys/_cpuset.h> 624 625#include <machine/frame.h> 626 627#define PMC_HASH_SIZE 1024 628#define PMC_MTXPOOL_SIZE 2048 629#define PMC_LOG_BUFFER_SIZE 4 630#define PMC_NLOGBUFFERS 1024 631#define PMC_NSAMPLES 1024 632#define PMC_CALLCHAIN_DEPTH 32 633 634#define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 635 636/* 637 * Locking keys 638 * 639 * (b) - pmc_bufferlist_mtx (spin lock) 640 * (k) - pmc_kthread_mtx (sleep lock) 641 * (o) - po->po_mtx (spin lock) 642 */ 643 644/* 645 * PMC commands 646 */ 647 648struct pmc_syscall_args { 649 register_t pmop_code; /* one of PMC_OP_* */ 650 void *pmop_data; /* syscall parameter */ 651}; 652 653/* 654 * Interface to processor specific s1tuff 655 */ 656 657/* 658 * struct pmc_descr 659 * 660 * Machine independent (i.e., the common parts) of a human readable 661 * PMC description. 662 */ 663 664struct pmc_descr { 665 char pd_name[PMC_NAME_MAX]; /* name */ 666 uint32_t pd_caps; /* capabilities */ 667 enum pmc_class pd_class; /* class of the PMC */ 668 uint32_t pd_width; /* width in bits */ 669}; 670 671/* 672 * struct pmc_target 673 * 674 * This structure records all the target processes associated with a 675 * PMC. 676 */ 677 678struct pmc_target { 679 LIST_ENTRY(pmc_target) pt_next; 680 struct pmc_process *pt_process; /* target descriptor */ 681}; 682 683/* 684 * struct pmc 685 * 686 * Describes each allocated PMC. 687 * 688 * Each PMC has precisely one owner, namely the process that allocated 689 * the PMC. 690 * 691 * A PMC may be attached to multiple target processes. The 692 * 'pm_targets' field links all the target processes being monitored 693 * by this PMC. 694 * 695 * The 'pm_savedvalue' field is protected by a mutex. 696 * 697 * On a multi-cpu machine, multiple target threads associated with a 698 * process-virtual PMC could be concurrently executing on different 699 * CPUs. The 'pm_runcount' field is atomically incremented every time 700 * the PMC gets scheduled on a CPU and atomically decremented when it 701 * get descheduled. Deletion of a PMC is only permitted when this 702 * field is '0'. 703 * 704 */ 705 706struct pmc { 707 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 708 LIST_ENTRY(pmc) pm_next; /* owner's list */ 709 710 /* 711 * System-wide PMCs are allocated on a CPU and are not moved 712 * around. For system-wide PMCs we record the CPU the PMC was 713 * allocated on in the 'CPU' field of the pmc ID. 714 * 715 * Virtual PMCs run on whichever CPU is currently executing 716 * their targets' threads. For these PMCs we need to save 717 * their current PMC counter values when they are taken off 718 * CPU. 719 */ 720 721 union { 722 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 723 } pm_gv; 724 725 /* 726 * For sampling mode PMCs, we keep track of the PMC's "reload 727 * count", which is the counter value to be loaded in when 728 * arming the PMC for the next counting session. For counting 729 * modes on PMCs that are read-only (e.g., the x86 TSC), we 730 * keep track of the initial value at the start of 731 * counting-mode operation. 732 */ 733 734 union { 735 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 736 pmc_value_t pm_initial; /* counting PMC modes */ 737 } pm_sc; 738 739 volatile cpuset_t pm_stalled; /* marks stalled sampling PMCs */ 740 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ 741 uint32_t pm_caps; /* PMC capabilities */ 742 enum pmc_event pm_event; /* event being measured */ 743 uint32_t pm_flags; /* additional flags PMC_F_... */ 744 struct pmc_owner *pm_owner; /* owner thread state */ 745 int pm_runcount; /* #cpus currently on */ 746 enum pmc_state pm_state; /* current PMC state */ 747 748 /* 749 * The PMC ID field encodes the row-index for the PMC, its 750 * mode, class and the CPU# associated with the PMC. 751 */ 752 753 pmc_id_t pm_id; /* allocated PMC id */ 754 755 /* md extensions */ 756 union pmc_md_pmc pm_md; 757}; 758 759/* 760 * Accessor macros for 'struct pmc' 761 */ 762 763#define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 764#define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 765#define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 766#define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 767 768 769/* 770 * struct pmc_process 771 * 772 * Record a 'target' process being profiled. 773 * 774 * The target process being profiled could be different from the owner 775 * process which allocated the PMCs. Each target process descriptor 776 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 777 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 778 * array. The size of this structure is thus PMC architecture 779 * dependent. 780 * 781 */ 782 783struct pmc_targetstate { 784 struct pmc *pp_pmc; /* target PMC */ 785 pmc_value_t pp_pmcval; /* per-process value */ 786}; 787 788struct pmc_process { 789 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 790 int pp_refcnt; /* reference count */ 791 uint32_t pp_flags; /* flags PMC_PP_* */ 792 struct proc *pp_proc; /* target thread */ 793 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 794}; 795 796#define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 797 798/* 799 * struct pmc_owner 800 * 801 * We associate a PMC with an 'owner' process. 802 * 803 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 804 * lifetime, where NCPUS is the numbers of CPUS in the system and 805 * NHWPMC is the number of hardware PMCs per CPU. These are 806 * maintained in the list headed by the 'po_pmcs' to save on space. 807 * 808 */ 809 810struct pmc_owner { 811 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 812 LIST_ENTRY(pmc_owner) po_ssnext; /* list of SS PMC owners */ 813 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 814 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 815 struct mtx po_mtx; /* spin lock for (o) */ 816 struct proc *po_owner; /* owner proc */ 817 uint32_t po_flags; /* (k) flags PMC_PO_* */ 818 struct proc *po_kthread; /* (k) helper kthread */ 819 struct pmclog_buffer *po_curbuf; /* current log buffer */ 820 struct file *po_file; /* file reference */ 821 int po_error; /* recorded error */ 822 short po_sscount; /* # SS PMCs owned */ 823 short po_logprocmaps; /* global mappings done */ 824}; 825 826#define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 827#define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 828#define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 829 830/* 831 * struct pmc_hw -- describe the state of the PMC hardware 832 * 833 * When in use, a HW PMC is associated with one allocated 'struct pmc' 834 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 835 * 836 * On an SMP box, one or more HW PMC's in process virtual mode with 837 * the same 'phw_pmc' could be executing on different CPUs. In order 838 * to handle this case correctly, we need to ensure that only 839 * incremental counts get added to the saved value in the associated 840 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 841 * value at the time the hardware is started during this context 842 * switch (i.e., the difference between the new (hardware) count and 843 * the saved count is atomically added to the count field in 'struct 844 * pmc' at context switch time). 845 * 846 */ 847 848struct pmc_hw { 849 uint32_t phw_state; /* see PHW_* macros below */ 850 struct pmc *phw_pmc; /* current thread PMC */ 851}; 852 853#define PMC_PHW_RI_MASK 0x000000FF 854#define PMC_PHW_CPU_SHIFT 8 855#define PMC_PHW_CPU_MASK 0x0000FF00 856#define PMC_PHW_FLAGS_SHIFT 16 857#define PMC_PHW_FLAGS_MASK 0xFFFF0000 858 859#define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 860#define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 861#define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 862 PMC_PHW_CPU_MASK) 863#define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 864 PMC_PHW_CPU_SHIFT) 865#define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 866 PMC_PHW_FLAGS_MASK) 867#define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 868 PMC_PHW_FLAGS_SHIFT) 869#define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 870#define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 871 872/* 873 * struct pmc_sample 874 * 875 * Space for N (tunable) PC samples and associated control data. 876 */ 877 878struct pmc_sample { 879 uint16_t ps_nsamples; /* callchain depth */ 880 uint8_t ps_cpu; /* cpu number */ 881 uint8_t ps_flags; /* other flags */ 882 pid_t ps_pid; /* process PID or -1 */ 883 struct thread *ps_td; /* which thread */ 884 struct pmc *ps_pmc; /* interrupting PMC */ 885 uintptr_t *ps_pc; /* (const) callchain start */ 886}; 887 888#define PMC_SAMPLE_FREE ((uint16_t) 0) 889#define PMC_SAMPLE_INUSE ((uint16_t) 0xFFFF) 890 891struct pmc_samplebuffer { 892 struct pmc_sample * volatile ps_read; /* read pointer */ 893 struct pmc_sample * volatile ps_write; /* write pointer */ 894 uintptr_t *ps_callchains; /* all saved call chains */ 895 struct pmc_sample *ps_fence; /* one beyond ps_samples[] */ 896 struct pmc_sample ps_samples[]; /* array of sample entries */ 897}; 898 899 900/* 901 * struct pmc_cpustate 902 * 903 * A CPU is modelled as a collection of HW PMCs with space for additional 904 * flags. 905 */ 906 907struct pmc_cpu { 908 uint32_t pc_state; /* physical cpu number + flags */ 909 struct pmc_samplebuffer *pc_sb[2]; /* space for samples */ 910 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 911}; 912 913#define PMC_PCPU_CPU_MASK 0x000000FF 914#define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 915#define PMC_PCPU_FLAGS_SHIFT 8 916#define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 917#define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 918#define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 919#define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 920#define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 921 922/* 923 * struct pmc_binding 924 * 925 * CPU binding information. 926 */ 927 928struct pmc_binding { 929 int pb_bound; /* is bound? */ 930 int pb_cpu; /* if so, to which CPU */ 931}; 932 933 934struct pmc_mdep; 935 936/* 937 * struct pmc_classdep 938 * 939 * PMC class-dependent operations. 940 */ 941struct pmc_classdep { 942 uint32_t pcd_caps; /* class capabilities */ 943 enum pmc_class pcd_class; /* class id */ 944 int pcd_num; /* number of PMCs */ 945 int pcd_ri; /* row index of the first PMC in class */ 946 int pcd_width; /* width of the PMC */ 947 948 /* configuring/reading/writing the hardware PMCs */ 949 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 950 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 951 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value); 952 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value); 953 954 /* pmc allocation/release */ 955 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 956 const struct pmc_op_pmcallocate *_a); 957 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 958 959 /* starting and stopping PMCs */ 960 int (*pcd_start_pmc)(int _cpu, int _ri); 961 int (*pcd_stop_pmc)(int _cpu, int _ri); 962 963 /* description */ 964 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 965 struct pmc **_ppmc); 966 967 /* class-dependent initialization & finalization */ 968 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 969 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 970 971 /* machine-specific interface */ 972 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 973}; 974 975/* 976 * struct pmc_mdep 977 * 978 * Machine dependent bits needed per CPU type. 979 */ 980 981struct pmc_mdep { 982 uint32_t pmd_cputype; /* from enum pmc_cputype */ 983 uint32_t pmd_npmc; /* number of PMCs per CPU */ 984 uint32_t pmd_nclass; /* number of PMC classes present */ 985 986 /* 987 * Machine dependent methods. 988 */ 989 990 /* per-cpu initialization and finalization */ 991 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 992 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 993 994 /* thread context switch in/out */ 995 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 996 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 997 998 /* handle a PMC interrupt */ 999 int (*pmd_intr)(int _cpu, struct trapframe *_tf); 1000 1001 /* 1002 * PMC class dependent information. 1003 */ 1004 struct pmc_classdep pmd_classdep[]; 1005}; 1006 1007/* 1008 * Per-CPU state. This is an array of 'mp_ncpu' pointers 1009 * to struct pmc_cpu descriptors. 1010 */ 1011 1012extern struct pmc_cpu **pmc_pcpu; 1013 1014/* driver statistics */ 1015extern struct pmc_op_getdriverstats pmc_stats; 1016 1017#if defined(HWPMC_DEBUG) 1018#include <sys/ktr.h> 1019 1020/* debug flags, major flag groups */ 1021struct pmc_debugflags { 1022 int pdb_CPU; 1023 int pdb_CSW; 1024 int pdb_LOG; 1025 int pdb_MDP; 1026 int pdb_MOD; 1027 int pdb_OWN; 1028 int pdb_PMC; 1029 int pdb_PRC; 1030 int pdb_SAM; 1031}; 1032 1033extern struct pmc_debugflags pmc_debugflags; 1034 1035#define KTR_PMC KTR_SUBSYS 1036 1037#define PMC_DEBUG_STRSIZE 128 1038#define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1039 1040#define PMCDBG0(M, N, L, F) do { \ 1041 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1042 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \ 1043} while (0) 1044#define PMCDBG1(M, N, L, F, p1) do { \ 1045 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1046 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \ 1047} while (0) 1048#define PMCDBG2(M, N, L, F, p1, p2) do { \ 1049 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1050 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \ 1051} while (0) 1052#define PMCDBG3(M, N, L, F, p1, p2, p3) do { \ 1053 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1054 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \ 1055} while (0) 1056#define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \ 1057 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1058 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\ 1059} while (0) 1060#define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \ 1061 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1062 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1063 p5); \ 1064} while (0) 1065#define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \ 1066 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1067 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1068 p5, p6); \ 1069} while (0) 1070 1071/* Major numbers */ 1072#define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1073#define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1074#define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1075#define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1076#define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1077#define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1078#define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1079#define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1080#define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1081 1082/* Minor numbers */ 1083 1084/* Common (8 bits) */ 1085#define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1086#define PMC_DEBUG_MIN_REL 1 /* release */ 1087#define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1088#define PMC_DEBUG_MIN_INI 3 /* init */ 1089#define PMC_DEBUG_MIN_FND 4 /* find */ 1090 1091/* MODULE */ 1092#define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1093#define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1094 1095/* OWN */ 1096#define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1097#define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1098 1099/* PROCESSES */ 1100#define PMC_DEBUG_MIN_TLK 8 /* link target */ 1101#define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1102#define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1103#define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1104#define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1105#define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1106#define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1107 1108/* CONTEXT SWITCHES */ 1109#define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1110#define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1111 1112/* PMC */ 1113#define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1114#define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1115 1116/* MACHINE DEPENDENT LAYER */ 1117#define PMC_DEBUG_MIN_REA 8 /* read */ 1118#define PMC_DEBUG_MIN_WRI 9 /* write */ 1119#define PMC_DEBUG_MIN_CFG 10 /* config */ 1120#define PMC_DEBUG_MIN_STA 11 /* start */ 1121#define PMC_DEBUG_MIN_STO 12 /* stop */ 1122#define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1123 1124/* CPU */ 1125#define PMC_DEBUG_MIN_BND 8 /* bind */ 1126#define PMC_DEBUG_MIN_SEL 9 /* select */ 1127 1128/* LOG */ 1129#define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1130#define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1131#define PMC_DEBUG_MIN_FLS 10 /* flush */ 1132#define PMC_DEBUG_MIN_SAM 11 /* sample */ 1133#define PMC_DEBUG_MIN_CLO 12 /* close */ 1134 1135#else 1136#define PMCDBG0(M, N, L, F) /* nothing */ 1137#define PMCDBG1(M, N, L, F, p1) 1138#define PMCDBG2(M, N, L, F, p1, p2) 1139#define PMCDBG3(M, N, L, F, p1, p2, p3) 1140#define PMCDBG4(M, N, L, F, p1, p2, p3, p4) 1141#define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) 1142#define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) 1143#endif 1144 1145/* declare a dedicated memory pool */ 1146MALLOC_DECLARE(M_PMC); 1147 1148/* 1149 * Functions 1150 */ 1151 1152struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1153void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1154int pmc_getrowdisp(int _ri); 1155int pmc_process_interrupt(int _cpu, int _soft, struct pmc *_pm, 1156 struct trapframe *_tf, int _inuserspace); 1157int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1158 struct trapframe *_tf); 1159int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1160 struct trapframe *_tf); 1161struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1162void pmc_mdep_free(struct pmc_mdep *md); 1163#endif /* _KERNEL */ 1164#endif /* _SYS_PMC_H_ */ 1165