cache.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Harvard University. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by Aaron Brown and 29 * Harvard University. 30 * 4. Neither the name of the University nor the names of its contributors 31 * may be used to endorse or promote products derived from this software 32 * without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 44 * SUCH DAMAGE. 45 */ 46/*- 47 * Copyright (c) 2001 by Thomas Moestl <tmm@FreeBSD.org>. 48 * Copyright (c) 2008, 2010 Marius Strobl <marius@FreeBSD.org> 49 * All rights reserved. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 61 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 62 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 63 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 64 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 65 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 69 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 70 * 71 * from: @(#)cache.c 8.2 (Berkeley) 10/30/93 72 * from: NetBSD: cache.c,v 1.5 2000/12/06 01:47:50 mrg Exp 73 */ 74 75#include <sys/cdefs.h> 76__FBSDID("$FreeBSD: stable/11/sys/sparc64/sparc64/cache.c 330897 2018-03-14 03:19:51Z eadler $"); 77 78#include <sys/param.h> 79#include <sys/systm.h> 80#include <sys/pcpu.h> 81 82#include <dev/ofw/openfirm.h> 83 84#include <machine/cache.h> 85#include <machine/tlb.h> 86#include <machine/ver.h> 87 88cache_enable_t *cache_enable; 89cache_flush_t *cache_flush; 90dcache_page_inval_t *dcache_page_inval; 91icache_page_inval_t *icache_page_inval; 92 93u_int dcache_color_ignore; 94 95#define OF_GET(h, n, v) OF_getprop((h), (n), &(v), sizeof(v)) 96 97static u_int cache_new_prop(u_int cpu_impl); 98 99static u_int 100cache_new_prop(u_int cpu_impl) 101{ 102 103 switch (cpu_impl) { 104 case CPU_IMPL_ULTRASPARCIV: 105 case CPU_IMPL_ULTRASPARCIVp: 106 return (1); 107 default: 108 return (0); 109 } 110} 111 112/* 113 * Fill in the cache parameters using the CPU node. 114 */ 115void 116cache_init(struct pcpu *pcpu) 117{ 118 u_long set; 119 u_int use_new_prop; 120 121 /* 122 * For CPUs which ignore TD_CV and support hardware unaliasing don't 123 * bother doing page coloring. This is equal across all CPUs. 124 */ 125 if (pcpu->pc_cpuid == 0 && pcpu->pc_impl == CPU_IMPL_SPARC64V) 126 dcache_color_ignore = 1; 127 128 use_new_prop = cache_new_prop(pcpu->pc_impl); 129 if (OF_GET(pcpu->pc_node, !use_new_prop ? "icache-size" : 130 "l1-icache-size", pcpu->pc_cache.ic_size) == -1 || 131 OF_GET(pcpu->pc_node, !use_new_prop ? "icache-line-size" : 132 "l1-icache-line-size", pcpu->pc_cache.ic_linesize) == -1 || 133 OF_GET(pcpu->pc_node, !use_new_prop ? "icache-associativity" : 134 "l1-icache-associativity", pcpu->pc_cache.ic_assoc) == -1 || 135 OF_GET(pcpu->pc_node, !use_new_prop ? "dcache-size" : 136 "l1-dcache-size", pcpu->pc_cache.dc_size) == -1 || 137 OF_GET(pcpu->pc_node, !use_new_prop ? "dcache-line-size" : 138 "l1-dcache-line-size", pcpu->pc_cache.dc_linesize) == -1 || 139 OF_GET(pcpu->pc_node, !use_new_prop ? "dcache-associativity" : 140 "l1-dcache-associativity", pcpu->pc_cache.dc_assoc) == -1 || 141 OF_GET(pcpu->pc_node, !use_new_prop ? "ecache-size" : 142 "l2-cache-size", pcpu->pc_cache.ec_size) == -1 || 143 OF_GET(pcpu->pc_node, !use_new_prop ? "ecache-line-size" : 144 "l2-cache-line-size", pcpu->pc_cache.ec_linesize) == -1 || 145 OF_GET(pcpu->pc_node, !use_new_prop ? "ecache-associativity" : 146 "l2-cache-associativity", pcpu->pc_cache.ec_assoc) == -1) 147 OF_panic("%s: could not retrieve cache parameters", __func__); 148 149 set = pcpu->pc_cache.ic_size / pcpu->pc_cache.ic_assoc; 150 if ((set & ~(1UL << (ffs(set) - 1))) != 0) 151 OF_panic("%s: I$ set size not a power of 2", __func__); 152 if ((pcpu->pc_cache.dc_size & 153 ~(1UL << (ffs(pcpu->pc_cache.dc_size) - 1))) != 0) 154 OF_panic("%s: D$ size not a power of 2", __func__); 155 /* 156 * For CPUs which don't support unaliasing in hardware ensure that 157 * the data cache doesn't have too many virtual colors. 158 */ 159 if (dcache_color_ignore == 0 && ((pcpu->pc_cache.dc_size / 160 pcpu->pc_cache.dc_assoc) / PAGE_SIZE) != DCACHE_COLORS) 161 OF_panic("%s: too many D$ colors", __func__); 162 set = pcpu->pc_cache.ec_size / pcpu->pc_cache.ec_assoc; 163 if ((set & ~(1UL << (ffs(set) - 1))) != 0) 164 OF_panic("%s: E$ set size not a power of 2", __func__); 165 166 if (pcpu->pc_impl >= CPU_IMPL_ULTRASPARCIII) { 167 cache_enable = cheetah_cache_enable; 168 cache_flush = cheetah_cache_flush; 169 dcache_page_inval = cheetah_dcache_page_inval; 170 icache_page_inval = cheetah_icache_page_inval; 171 tlb_flush_nonlocked = cheetah_tlb_flush_nonlocked; 172 tlb_flush_user = cheetah_tlb_flush_user; 173 } else if (pcpu->pc_impl == CPU_IMPL_SPARC64V) { 174 cache_enable = zeus_cache_enable; 175 cache_flush = zeus_cache_flush; 176 dcache_page_inval = zeus_dcache_page_inval; 177 icache_page_inval = zeus_icache_page_inval; 178 tlb_flush_nonlocked = zeus_tlb_flush_nonlocked; 179 tlb_flush_user = zeus_tlb_flush_user; 180 } else if (pcpu->pc_impl >= CPU_IMPL_ULTRASPARCI && 181 pcpu->pc_impl < CPU_IMPL_ULTRASPARCIII) { 182 cache_enable = spitfire_cache_enable; 183 cache_flush = spitfire_cache_flush; 184 dcache_page_inval = spitfire_dcache_page_inval; 185 icache_page_inval = spitfire_icache_page_inval; 186 tlb_flush_nonlocked = spitfire_tlb_flush_nonlocked; 187 tlb_flush_user = spitfire_tlb_flush_user; 188 } else 189 OF_panic("%s: unknown CPU", __func__); 190} 191