vxgehal-common-reg.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright(c) 2002-2011 Exar Corp.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification are permitted provided the following conditions are met:
9 *
10 *    1. Redistributions of source code must retain the above copyright notice,
11 *       this list of conditions and the following disclaimer.
12 *
13 *    2. Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in the
15 *       documentation and/or other materials provided with the distribution.
16 *
17 *    3. Neither the name of the Exar Corporation nor the names of its
18 *       contributors may be used to endorse or promote products derived from
19 *       this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33/*$FreeBSD: stable/11/sys/dev/vxge/vxgehal/vxgehal-common-reg.h 330897 2018-03-14 03:19:51Z eadler $*/
34
35#ifndef	VXGE_HAL_COMMON_REGS_H
36#define	VXGE_HAL_COMMON_REGS_H
37
38__EXTERN_BEGIN_DECLS
39
40typedef struct vxge_hal_common_reg_t {
41
42	u8	unused00a00[0x00a00];
43
44/* 0x00a00 */	u64	prc_status1;
45#define	VXGE_HAL_PRC_STATUS1_PRC_VP_QUIESCENT(n)	mBIT(n)
46/* 0x00a08 */	u64	rxdcm_reset_in_progress;
47#define	VXGE_HAL_RXDCM_RESET_IN_PROGRESS_PRC_VP(n)	mBIT(n)
48/* 0x00a10 */	u64	replicq_flush_in_progress;
49#define	VXGE_HAL_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n)	mBIT(n)
50/* 0x00a18 */	u64	rxpe_cmds_reset_in_progress;
51#define	VXGE_HAL_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n)	mBIT(n)
52/* 0x00a20 */	u64	mxp_cmds_reset_in_progress;
53#define	VXGE_HAL_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n)	mBIT(n)
54/* 0x00a28 */	u64	noffload_reset_in_progress;
55#define	VXGE_HAL_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n)	mBIT(n)
56/* 0x00a30 */	u64	rd_req_in_progress;
57#define	VXGE_HAL_RD_REQ_IN_PROGRESS_VP(n)	mBIT(n)
58/* 0x00a38 */	u64	rd_req_outstanding;
59#define	VXGE_HAL_RD_REQ_OUTSTANDING_VP(n)	mBIT(n)
60/* 0x00a40 */	u64	kdfc_reset_in_progress;
61#define	VXGE_HAL_KDFC_RESET_IN_PROGRESS_NOA_VP(n)	mBIT(n)
62	u8	unused00b00[0x00b00 - 0x00a48];
63
64/* 0x00b00 */	u64	one_cfg_vp;
65#define	VXGE_HAL_ONE_CFG_VP_RDY(n)	mBIT(n)
66/* 0x00b08 */	u64	one_common;
67#define	VXGE_HAL_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS(n)	mBIT(n)
68	u8	unused00b80[0x00b80 - 0x00b10];
69
70/* 0x00b80 */	u64	tim_int_en;
71#define	VXGE_HAL_TIM_INT_EN_TIM_VP(n)	mBIT(n)
72/* 0x00b88 */	u64	tim_set_int_en;
73#define	VXGE_HAL_TIM_SET_INT_EN_VP(n)	mBIT(n)
74/* 0x00b90 */	u64	tim_clr_int_en;
75#define	VXGE_HAL_TIM_CLR_INT_EN_VP(n)	mBIT(n)
76/* 0x00b98 */	u64	tim_mask_int_during_reset;
77#define	VXGE_HAL_TIM_MASK_INT_DURING_RESET_VPATH(n)	mBIT(n)
78/* 0x00ba0 */	u64	tim_reset_in_progress;
79#define	VXGE_HAL_TIM_RESET_IN_PROGRESS_TIM_VPATH(n)	mBIT(n)
80/* 0x00ba8 */	u64	tim_outstanding_bmap;
81#define	VXGE_HAL_TIM_OUTSTANDING_BMAP_TIM_VPATH(n)	mBIT(n)
82	u8	unused00c00[0x00c00 - 0x00bb0];
83
84/* 0x00c00 */	u64	msg_reset_in_progress;
85#define	VXGE_HAL_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val)	vBIT(val, 0, 17)
86/* 0x00c08 */	u64	msg_mxp_mr_ready;
87#define	VXGE_HAL_MSG_MXP_MR_READY_MP_BOOTED(n)	mBIT(n)
88/* 0x00c10 */	u64	msg_uxp_mr_ready;
89#define	VXGE_HAL_MSG_UXP_MR_READY_UP_BOOTED(n)	mBIT(n)
90/* 0x00c18 */	u64	msg_dmq_noni_rtl_prefetch;
91#define	VXGE_HAL_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE(n)	mBIT(n)
92/* 0x00c20 */	u64	msg_umq_rtl_bwr;
93#define	VXGE_HAL_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE(n)	mBIT(n)
94	u8	unused00d00[0x00d00 - 0x00c28];
95
96/* 0x00d00 */	u64	cmn_rsthdlr_cfg0;
97#define	VXGE_HAL_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val)	vBIT(val, 0, 17)
98/* 0x00d08 */	u64	cmn_rsthdlr_cfg1;
99#define	VXGE_HAL_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val)	vBIT(val, 0, 17)
100/* 0x00d10 */	u64	cmn_rsthdlr_cfg2;
101#define	VXGE_HAL_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val)	vBIT(val, 0, 17)
102/* 0x00d18 */	u64	cmn_rsthdlr_cfg3;
103#define	VXGE_HAL_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val)	vBIT(val, 0, 17)
104/* 0x00d20 */	u64	cmn_rsthdlr_cfg4;
105#define	VXGE_HAL_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val)	vBIT(val, 0, 17)
106	u8	unused00d40[0x00d40 - 0x00d28];
107
108/* 0x00d40 */	u64	cmn_rsthdlr_cfg8;
109#define	VXGE_HAL_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val)	vBIT(val, 0, 17)
110/* 0x00d48 */	u64	stats_cfg0;
111#define	VXGE_HAL_STATS_CFG0_STATS_ENABLE(val)	vBIT(val, 0, 17)
112	u8	unused00da8[0x00da8 - 0x00d50];
113
114/* 0x00da8 */	u64	clear_msix_mask_vect[4];
115#define	VXGE_HAL_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val)	vBIT(val, 0, 17)
116/* 0x00dc8 */	u64	set_msix_mask_vect[4];
117#define	VXGE_HAL_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val)	vBIT(val, 0, 17)
118/* 0x00de8 */	u64	clear_msix_mask_all_vect;
119#define	VXGE_HAL_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val)\
120								vBIT(val, 0, 17)
121/* 0x00df0 */	u64	set_msix_mask_all_vect;
122#define	VXGE_HAL_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val)\
123								vBIT(val, 0, 17)
124/* 0x00df8 */	u64	mask_vector[4];
125#define	VXGE_HAL_MASK_VECTOR_MASK_VECTOR(val)	vBIT(val, 0, 17)
126/* 0x00e18 */	u64	msix_pending_vector[4];
127#define	VXGE_HAL_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val)	vBIT(val, 0, 17)
128/* 0x00e38 */	u64	clr_msix_one_shot_vec[4];
129#define	VXGE_HAL_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val)\
130								vBIT(val, 0, 17)
131/* 0x00e58 */	u64	titan_asic_id;
132#define	VXGE_HAL_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val)		vBIT(val, 0, 16)
133#define	VXGE_HAL_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val)	vBIT(val, 48, 8)
134#define	VXGE_HAL_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val)	vBIT(val, 56, 8)
135/* 0x00e60 */	u64	titan_general_int_status;
136#define	VXGE_HAL_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT	mBIT(0)
137#define	VXGE_HAL_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT	mBIT(1)
138#define	VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT	mBIT(2)
139#define	VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val)\
140								vBIT(val, 3, 17)
141	u8	unused00e70[0x00e70 - 0x00e68];
142
143/* 0x00e70 */	u64	titan_mask_all_int;
144#define	VXGE_HAL_TITAN_MASK_ALL_INT_ALARM	mBIT(7)
145#define	VXGE_HAL_TITAN_MASK_ALL_INT_TRAFFIC	mBIT(15)
146	u8	unused00e80[0x00e80 - 0x00e78];
147
148/* 0x00e80 */	u64	tim_int_status0;
149#define	VXGE_HAL_TIM_INT_STATUS0_TIM_INT_STATUS0(val)	vBIT(val, 0, 64)
150/* 0x00e88 */	u64	tim_int_mask0;
151#define	VXGE_HAL_TIM_INT_MASK0_TIM_INT_MASK0(val)	vBIT(val, 0, 64)
152/* 0x00e90 */	u64	tim_int_status1;
153#define	VXGE_HAL_TIM_INT_STATUS1_TIM_INT_STATUS1(val)	vBIT(val, 0, 4)
154/* 0x00e98 */	u64	tim_int_mask1;
155#define	VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(val)	vBIT(val, 0, 4)
156/* 0x00ea0 */	u64	rti_int_status;
157#define	VXGE_HAL_RTI_INT_STATUS_RTI_INT_STATUS(val)	vBIT(val, 0, 17)
158/* 0x00ea8 */	u64	rti_int_mask;
159#define	VXGE_HAL_RTI_INT_MASK_RTI_INT_MASK(val)	vBIT(val, 0, 17)
160/* 0x00eb0 */	u64	adapter_status;
161#define	VXGE_HAL_ADAPTER_STATUS_RTDMA_RTDMA_READY	mBIT(0)
162#define	VXGE_HAL_ADAPTER_STATUS_WRDMA_WRDMA_READY	mBIT(1)
163#define	VXGE_HAL_ADAPTER_STATUS_KDFC_KDFC_READY	mBIT(2)
164#define	VXGE_HAL_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY	mBIT(3)
165#define	VXGE_HAL_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT	mBIT(4)
166#define	VXGE_HAL_ADAPTER_STATUS_XGMAC_NETWORK_FAULT	mBIT(5)
167#define	VXGE_HAL_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT	mBIT(6)
168#define	VXGE_HAL_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY	mBIT(7)
169#define	VXGE_HAL_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY	mBIT(8)
170#define	VXGE_HAL_ADAPTER_STATUS_RIC_RIC_RUNNING	mBIT(9)
171#define	VXGE_HAL_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK	mBIT(10)
172#define	VXGE_HAL_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK	mBIT(11)
173#define	VXGE_HAL_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK	mBIT(12)
174#define	VXGE_HAL_ADAPTER_STATUS_PCC_PCC_IDLE(val)	vBIT(val, 24, 8)
175#define	VXGE_HAL_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val)	vBIT(val, 44, 8)
176/* 0x00eb8 */	u64	gen_ctrl;
177#define	VXGE_HAL_GEN_CTRL_SPI_MRPCIM_WR_DIS	mBIT(0)
178#define	VXGE_HAL_GEN_CTRL_SPI_MRPCIM_RD_DIS	mBIT(1)
179#define	VXGE_HAL_GEN_CTRL_SPI_SRPCIM_WR_DIS	mBIT(2)
180#define	VXGE_HAL_GEN_CTRL_SPI_SRPCIM_RD_DIS	mBIT(3)
181#define	VXGE_HAL_GEN_CTRL_SPI_DEBUG_DIS	mBIT(4)
182#define	VXGE_HAL_GEN_CTRL_SPI_APP_LTSSM_TIMER_DIS	mBIT(5)
183#define	VXGE_HAL_GEN_CTRL_SPI_NOT_USED(val)	vBIT(val, 6, 4)
184	u8	unused00ed0[0x00ed0 - 0x00ec0];
185
186/* 0x00ed0 */	u64	adapter_ready;
187#define	VXGE_HAL_ADAPTER_READY_ADAPTER_READY	mBIT(63)
188/* 0x00ed8 */	u64	outstanding_read;
189#define	VXGE_HAL_OUTSTANDING_READ_OUTSTANDING_READ(val)	vBIT(val, 0, 17)
190/* 0x00ee0 */	u64	vpath_rst_in_prog;
191#define	VXGE_HAL_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val)	vBIT(val, 0, 17)
192/* 0x00ee8 */	u64	vpath_reg_modified;
193#define	VXGE_HAL_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val)	vBIT(val, 0, 17)
194	u8	unused00f40[0x00f40 - 0x00ef0];
195
196/* 0x00f40 */	u64	qcc_reset_in_progress;
197#define	VXGE_HAL_QCC_RESET_IN_PROGRESS_QCC_VPATH(n)	mBIT(n)
198	u8	unused00fc0[0x00fc0 - 0x00f48];
199
200/* 0x00fc0 */	u64	cp_reset_in_progress;
201#define	VXGE_HAL_CP_RESET_IN_PROGRESS_CP_VPATH(n)	mBIT(n)
202	u8	unused01000[0x01000 - 0x00fc8];
203
204/* 0x01000 */	u64	h2l_reset_in_progress;
205#define	VXGE_HAL_H2L_RESET_IN_PROGRESS_H2L_VPATH(n)	mBIT(n)
206	u8	unused01080[0x01080 - 0x01008];
207
208/* 0x01080 */	u64	xgmac_ready;
209#define	VXGE_HAL_XGMAC_READY_XMACJ_READY(val)	vBIT(val, 0, 17)
210	u8	unused010c0[0x010c0 - 0x01088];
211
212/* 0x010c0 */	u64	fbif_ready;
213#define	VXGE_HAL_FBIF_READY_FAU_READY(val)	vBIT(val, 0, 17)
214	u8	unused01100[0x01100 - 0x010c8];
215
216/* 0x01100 */	u64	vplane_assignments;
217#define	VXGE_HAL_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val)	vBIT(val, 3, 5)
218/* 0x01108 */	u64	vpath_assignments;
219#define	VXGE_HAL_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val)	vBIT(val, 0, 17)
220/* 0x01110 */	u64	resource_assignments;
221#define	VXGE_HAL_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val)	vBIT(val, 0, 17)
222/* 0x01118 */	u64	host_type_assignments;
223#define	VXGE_HAL_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val)\
224								vBIT(val, 5, 3)
225/* 0x01120 */	u64	debug_assignments;
226#define	VXGE_HAL_DEBUG_ASSIGNMENTS_VHLABEL(val)			vBIT(val, 3, 5)
227#define	VXGE_HAL_DEBUG_ASSIGNMENTS_VPLANE(val)			vBIT(val, 11, 5)
228#define	VXGE_HAL_DEBUG_ASSIGNMENTS_FUNC(val)			vBIT(val, 19, 5)
229
230/* 0x01128 */	u64	max_resource_assignments;
231#define	VXGE_HAL_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val)	vBIT(val, 3, 5)
232#define	VXGE_HAL_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val)	vBIT(val, 11, 5)
233/* 0x01130 */	u64	pf_vpath_assignments;
234#define	VXGE_HAL_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val)	vBIT(val, 0, 17)
235	u8	unused01200[0x01200 - 0x01138];
236
237/* 0x01200 */	u64	rts_access_icmp;
238#define	VXGE_HAL_RTS_ACCESS_ICMP_EN(val)	vBIT(val, 0, 17)
239/* 0x01208 */	u64	rts_access_tcpsyn;
240#define	VXGE_HAL_RTS_ACCESS_TCPSYN_EN(val)	vBIT(val, 0, 17)
241/* 0x01210 */	u64	rts_access_zl4pyld;
242#define	VXGE_HAL_RTS_ACCESS_ZL4PYLD_EN(val)	vBIT(val, 0, 17)
243/* 0x01218 */	u64	rts_access_l4prtcl_tcp;
244#define	VXGE_HAL_RTS_ACCESS_L4PRTCL_TCP_EN(val)	vBIT(val, 0, 17)
245/* 0x01220 */	u64	rts_access_l4prtcl_udp;
246#define	VXGE_HAL_RTS_ACCESS_L4PRTCL_UDP_EN(val)	vBIT(val, 0, 17)
247/* 0x01228 */	u64	rts_access_l4prtcl_flex;
248#define	VXGE_HAL_RTS_ACCESS_L4PRTCL_FLEX_EN(val)	vBIT(val, 0, 17)
249/* 0x01230 */	u64	rts_access_ipfrag;
250#define	VXGE_HAL_RTS_ACCESS_IPFRAG_EN(val)	vBIT(val, 0, 17)
251
252	u8	unused01238[0x01248 - 0x01238];
253
254} vxge_hal_common_reg_t;
255
256__EXTERN_END_DECLS
257
258#endif	/* VXGE_HAL_COMMON_REGS_H */
259