vxgehal-srpcim-reg.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright(c) 2002-2011 Exar Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification are permitted provided the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Exar Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33/*$FreeBSD: stable/11/sys/dev/vxge/vxgehal/vxgehal-srpcim-reg.h 330897 2018-03-14 03:19:51Z eadler $*/ 34 35#ifndef VXGE_HAL_SRPCIM_REGS_H 36#define VXGE_HAL_SRPCIM_REGS_H 37 38__EXTERN_BEGIN_DECLS 39 40typedef struct vxge_hal_srpcim_reg_t { 41 42/* 0x00000 */ u64 tim_mr2sr_resource_assignment_vh; 43#define VXGE_HAL_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val)\ 44 vBIT(val, 0, 32) 45 u8 unused00100[0x00100 - 0x00008]; 46 47/* 0x00100 */ u64 srpcim_pcipif_int_status; 48#define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_INT mBIT(3) 49#define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT mBIT(7) 50#define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_SRPCIM_SPARE_R1_SRPCIM_SPARE_R1_INT\ 51 mBIT(11) 52/* 0x00108 */ u64 srpcim_pcipif_int_mask; 53/* 0x00110 */ u64 mrpcim_msg_reg; 54#define VXGE_HAL_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT mBIT(3) 55/* 0x00118 */ u64 mrpcim_msg_mask; 56/* 0x00120 */ u64 mrpcim_msg_alarm; 57/* 0x00128 */ u64 vpath_msg_reg; 58#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT mBIT(0) 59#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT mBIT(1) 60#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT mBIT(2) 61#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT mBIT(3) 62#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT mBIT(4) 63#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT mBIT(5) 64#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT mBIT(6) 65#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT mBIT(7) 66#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT mBIT(8) 67#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT mBIT(9) 68#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT mBIT(10) 69#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT mBIT(11) 70#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT mBIT(12) 71#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT mBIT(13) 72#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT mBIT(14) 73#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT mBIT(15) 74#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT mBIT(16) 75/* 0x00130 */ u64 vpath_msg_mask; 76/* 0x00138 */ u64 vpath_msg_alarm; 77 u8 unused00158[0x00158 - 0x00140]; 78 79/* 0x00158 */ u64 vf_bargrp_no; 80#define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR0(val) vBIT(val, 11, 5) 81#define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR1(val) vBIT(val, 19, 5) 82#define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR2(val) vBIT(val, 26, 6) 83#define VXGE_HAL_VF_BARGRP_NO_FIRST_VF_OFFSET(val) vBIT(val, 32, 4) 84#define VXGE_HAL_VF_BARGRP_NO_MASK(val) vBIT(val, 36, 4) 85/* 0x00160 */ u64 srpcim_to_mrpcim_wmsg; 86#define VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val)\ 87 vBIT(val, 0, 64) 88/* 0x00168 */ u64 srpcim_to_mrpcim_wmsg_trig; 89#define VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG mBIT(0) 90/* 0x00170 */ u64 mrpcim_to_srpcim_rmsg; 91#define VXGE_HAL_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val)\ 92 vBIT(val, 0, 64) 93/* 0x00178 */ u64 vpath_to_srpcim_rmsg_sel; 94#define VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SEL_SEL(val) vBIT(val, 0, 5) 95/* 0x00180 */ u64 vpath_to_srpcim_rmsg; 96#define VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val)\ 97 vBIT(val, 0, 64) 98 u8 unused00200[0x00200 - 0x00188]; 99 100/* 0x00200 */ u64 srpcim_general_int_status; 101#define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT mBIT(0) 102#define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PCI_INT mBIT(3) 103#define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT mBIT(7) 104 u8 unused00210[0x00210 - 0x00208]; 105 106/* 0x00210 */ u64 srpcim_general_int_mask; 107#define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PIC_INT mBIT(0) 108#define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PCI_INT mBIT(3) 109#define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_XMAC_INT mBIT(7) 110 u8 unused00220[0x00220 - 0x00218]; 111 112/* 0x00220 */ u64 srpcim_ppif_int_status; 113#define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_SRPCIM_GEN_ERRORS_INT\ 114 mBIT(3) 115#define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_MRPCIM_TO_SRPCIM_ALARM mBIT(7) 116#define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_VPATH_TO_SRPCIM_ALARM_INT mBIT(11) 117/* 0x00228 */ u64 srpcim_ppif_int_mask; 118/* 0x00230 */ u64 srpcim_gen_errors_reg; 119#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR mBIT(3) 120#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR mBIT(7) 121#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR mBIT(11) 122#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT mBIT(15) 123#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET mBIT(19) 124#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS mBIT(23) 125/* 0x00238 */ u64 srpcim_gen_errors_mask; 126/* 0x00240 */ u64 srpcim_gen_errors_alarm; 127/* 0x00248 */ u64 mrpcim_to_srpcim_alarm_reg; 128#define VXGE_HAL_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM mBIT(3) 129/* 0x00250 */ u64 mrpcim_to_srpcim_alarm_mask; 130/* 0x00258 */ u64 mrpcim_to_srpcim_alarm_alarm; 131/* 0x00260 */ u64 vpath_to_srpcim_alarm_reg; 132#define VXGE_HAL_VPATH_TO_SRPCIM_ALARM_REG_PPIF_VPATH_TO_SRPCIM_ALARM(val)\ 133 vBIT(val, 0, 17) 134/* 0x00268 */ u64 vpath_to_srpcim_alarm_mask; 135/* 0x00270 */ u64 vpath_to_srpcim_alarm_alarm; 136 u8 unused00280[0x00280 - 0x00278]; 137 138/* 0x00280 */ u64 pf_sw_reset; 139#define VXGE_HAL_PF_SW_RESET_PF_SW_RESET(val) vBIT(val, 0, 8) 140/* 0x00288 */ u64 srpcim_general_cfg1; 141#define VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN mBIT(19) 142#define VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN mBIT(23) 143#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN mBIT(27) 144#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN mBIT(31) 145#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN mBIT(35) 146#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN mBIT(39) 147/* 0x00290 */ u64 srpcim_interrupt_cfg1; 148#define VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vBIT(val, 1, 7) 149#define VXGE_HAL_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val) vBIT(val, 9, 3) 150/* 0x00298 */ u64 srpcim_interrupt_cfg2; 151#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_MSIX_FOR_SCHED_INT(val)\ 152 vBIT(val, 1, 7) 153#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_ONE_SHOT mBIT(11) 154#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_TIMER_EN mBIT(15) 155#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_INT_PERIOD(val) vBIT(val, 32, 32) 156 u8 unused002a8[0x002a8 - 0x002a0]; 157 158/* 0x002a8 */ u64 srpcim_clear_msix_mask; 159#define VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK mBIT(0) 160/* 0x002b0 */ u64 srpcim_set_msix_mask; 161#define VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK mBIT(0) 162/* 0x002b8 */ u64 srpcim_clr_msix_one_shot; 163#define VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT mBIT(0) 164/* 0x002c0 */ u64 srpcim_rst_in_prog; 165#define VXGE_HAL_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG mBIT(7) 166/* 0x002c8 */ u64 srpcim_reg_modified; 167#define VXGE_HAL_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED mBIT(7) 168/* 0x002d0 */ u64 tgt_pf_illegal_access; 169#define VXGE_HAL_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vBIT(val, 1, 7) 170/* 0x002d8 */ u64 srpcim_msix_status; 171#define VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK mBIT(3) 172#define VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR mBIT(7) 173 u8 unused00318[0x00318 - 0x002e0]; 174 175/* 0x00318 */ u64 usdc_vpl; 176#define VXGE_HAL_USDC_VPL_SGRP_OWN(val) vBIT(val, 0, 32) 177 u8 unused00600[0x00600 - 0x00320]; 178 179/* 0x00600 */ u64 one_cfg_sr_copy; 180#define VXGE_HAL_ONE_CFG_SR_COPY_ONE_CFG_RDY mBIT(7) 181/* 0x00608 */ u64 sgrp_allocated; 182#define VXGE_HAL_SGRP_ALLOCATED_SGRP_ALLOC(val) vBIT(val, 0, 64) 183/* 0x00610 */ u64 sgrp_iwarp_lro_allocated; 184#define VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_ENABLE_IWARP mBIT(7) 185#define VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_LAST_IWARP_SGRP(val) vBIT(val, 11, 5) 186 u8 unused00880[0x00880 - 0x00618]; 187 188/* 0x00880 */ u64 xgmac_sr_int_status; 189#define VXGE_HAL_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_INT mBIT(3) 190/* 0x00888 */ u64 xgmac_sr_int_mask; 191/* 0x00890 */ u64 asic_ntwk_sr_err_reg; 192#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT mBIT(3) 193#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK mBIT(7) 194#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT_OCCURRED\ 195 mBIT(11) 196#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED mBIT(15) 197/* 0x00898 */ u64 asic_ntwk_sr_err_mask; 198/* 0x008a0 */ u64 asic_ntwk_sr_err_alarm; 199 u8 unused008c0[0x008c0 - 0x008a8]; 200 201/* 0x008c0 */ u64 xmac_vsport_choices_sr_clone; 202#define VXGE_HAL_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val)\ 203 vBIT(val, 0, 17) 204 u8 unused00900[0x00900 - 0x008c8]; 205 206/* 0x00900 */ u64 mr_rqa_top_prty_for_vh; 207#define VXGE_HAL_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val)\ 208 vBIT(val, 59, 5) 209/* 0x00908 */ u64 umq_vh_data_list_empty; 210#define VXGE_HAL_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY mBIT(0) 211/* 0x00910 */ u64 wde_cfg; 212#define VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_START mBIT(0) 213#define VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_END mBIT(1) 214#define VXGE_HAL_WDE_CFG_NS0_FORCE_QB_START mBIT(2) 215#define VXGE_HAL_WDE_CFG_NS0_FORCE_QB_END mBIT(3) 216#define VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_START mBIT(4) 217#define VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_END mBIT(5) 218#define VXGE_HAL_WDE_CFG_NS0_MWB_OPT_EN mBIT(6) 219#define VXGE_HAL_WDE_CFG_NS0_QB_OPT_EN mBIT(7) 220#define VXGE_HAL_WDE_CFG_NS0_MPSB_OPT_EN mBIT(8) 221#define VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_START mBIT(9) 222#define VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_END mBIT(10) 223#define VXGE_HAL_WDE_CFG_NS1_FORCE_QB_START mBIT(11) 224#define VXGE_HAL_WDE_CFG_NS1_FORCE_QB_END mBIT(12) 225#define VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_START mBIT(13) 226#define VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_END mBIT(14) 227#define VXGE_HAL_WDE_CFG_NS1_MWB_OPT_EN mBIT(15) 228#define VXGE_HAL_WDE_CFG_NS1_QB_OPT_EN mBIT(16) 229#define VXGE_HAL_WDE_CFG_NS1_MPSB_OPT_EN mBIT(17) 230#define VXGE_HAL_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR mBIT(19) 231#define VXGE_HAL_WDE_CFG_ALIGNMENT_PREFERENCE(val) vBIT(val, 30, 2) 232#define VXGE_HAL_WDE_CFG_MEM_WORD_SIZE(val) vBIT(val, 46, 2) 233 234} vxge_hal_srpcim_reg_t; 235 236__EXTERN_END_DECLS 237 238#endif /* VXGE_HAL_SRPCIM_REGS_H */ 239