am335x_lcd.c revision 331722
1/*- 2 * Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/ti/am335x/am335x_lcd.c 331722 2018-03-29 02:50:57Z eadler $"); 29 30#include "opt_syscons.h" 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/clock.h> 36#include <sys/time.h> 37#include <sys/bus.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/resource.h> 41#include <sys/rman.h> 42#include <sys/sysctl.h> 43#include <vm/vm.h> 44#include <vm/pmap.h> 45#include <sys/fbio.h> 46#include <sys/consio.h> 47 48#include <machine/bus.h> 49 50#include <dev/fdt/fdt_common.h> 51#include <dev/ofw/openfirm.h> 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_bus_subr.h> 54 55#include <dev/videomode/videomode.h> 56#include <dev/videomode/edidvar.h> 57 58#include <dev/fb/fbreg.h> 59#ifdef DEV_SC 60#include <dev/syscons/syscons.h> 61#else /* VT */ 62#include <dev/vt/vt.h> 63#endif 64 65#include <arm/ti/ti_prcm.h> 66#include <arm/ti/ti_scm.h> 67 68#include "am335x_lcd.h" 69#include "am335x_pwm.h" 70 71#include "fb_if.h" 72#include "hdmi_if.h" 73 74#define LCD_PID 0x00 75#define LCD_CTRL 0x04 76#define CTRL_DIV_MASK 0xff 77#define CTRL_DIV_SHIFT 8 78#define CTRL_AUTO_UFLOW_RESTART (1 << 1) 79#define CTRL_RASTER_MODE 1 80#define CTRL_LIDD_MODE 0 81#define LCD_LIDD_CTRL 0x0C 82#define LCD_LIDD_CS0_CONF 0x10 83#define LCD_LIDD_CS0_ADDR 0x14 84#define LCD_LIDD_CS0_DATA 0x18 85#define LCD_LIDD_CS1_CONF 0x1C 86#define LCD_LIDD_CS1_ADDR 0x20 87#define LCD_LIDD_CS1_DATA 0x24 88#define LCD_RASTER_CTRL 0x28 89#define RASTER_CTRL_TFT24_UNPACKED (1 << 26) 90#define RASTER_CTRL_TFT24 (1 << 25) 91#define RASTER_CTRL_STN565 (1 << 24) 92#define RASTER_CTRL_TFTPMAP (1 << 23) 93#define RASTER_CTRL_NIBMODE (1 << 22) 94#define RASTER_CTRL_PALMODE_SHIFT 20 95#define PALETTE_PALETTE_AND_DATA 0x00 96#define PALETTE_PALETTE_ONLY 0x01 97#define PALETTE_DATA_ONLY 0x02 98#define RASTER_CTRL_REQDLY_SHIFT 12 99#define RASTER_CTRL_MONO8B (1 << 9) 100#define RASTER_CTRL_RBORDER (1 << 8) 101#define RASTER_CTRL_LCDTFT (1 << 7) 102#define RASTER_CTRL_LCDBW (1 << 1) 103#define RASTER_CTRL_LCDEN (1 << 0) 104#define LCD_RASTER_TIMING_0 0x2C 105#define RASTER_TIMING_0_HBP_SHIFT 24 106#define RASTER_TIMING_0_HFP_SHIFT 16 107#define RASTER_TIMING_0_HSW_SHIFT 10 108#define RASTER_TIMING_0_PPLLSB_SHIFT 4 109#define RASTER_TIMING_0_PPLMSB_SHIFT 3 110#define LCD_RASTER_TIMING_1 0x30 111#define RASTER_TIMING_1_VBP_SHIFT 24 112#define RASTER_TIMING_1_VFP_SHIFT 16 113#define RASTER_TIMING_1_VSW_SHIFT 10 114#define RASTER_TIMING_1_LPP_SHIFT 0 115#define LCD_RASTER_TIMING_2 0x34 116#define RASTER_TIMING_2_HSWHI_SHIFT 27 117#define RASTER_TIMING_2_LPP_B10_SHIFT 26 118#define RASTER_TIMING_2_PHSVS (1 << 25) 119#define RASTER_TIMING_2_PHSVS_RISE (1 << 24) 120#define RASTER_TIMING_2_PHSVS_FALL (0 << 24) 121#define RASTER_TIMING_2_IOE (1 << 23) 122#define RASTER_TIMING_2_IPC (1 << 22) 123#define RASTER_TIMING_2_IHS (1 << 21) 124#define RASTER_TIMING_2_IVS (1 << 20) 125#define RASTER_TIMING_2_ACBI_SHIFT 16 126#define RASTER_TIMING_2_ACB_SHIFT 8 127#define RASTER_TIMING_2_HBPHI_SHIFT 4 128#define RASTER_TIMING_2_HFPHI_SHIFT 0 129#define LCD_RASTER_SUBPANEL 0x38 130#define LCD_RASTER_SUBPANEL2 0x3C 131#define LCD_LCDDMA_CTRL 0x40 132#define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 133#define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 134#define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 135#define LCDDMA_CTRL_BYTES_SWAP (1 << 3) 136#define LCDDMA_CTRL_BE (1 << 1) 137#define LCDDMA_CTRL_FB0_ONLY 0 138#define LCDDMA_CTRL_FB0_FB1 (1 << 0) 139#define LCD_LCDDMA_FB0_BASE 0x44 140#define LCD_LCDDMA_FB0_CEILING 0x48 141#define LCD_LCDDMA_FB1_BASE 0x4C 142#define LCD_LCDDMA_FB1_CEILING 0x50 143#define LCD_SYSCONFIG 0x54 144#define SYSCONFIG_STANDBY_FORCE (0 << 4) 145#define SYSCONFIG_STANDBY_NONE (1 << 4) 146#define SYSCONFIG_STANDBY_SMART (2 << 4) 147#define SYSCONFIG_IDLE_FORCE (0 << 2) 148#define SYSCONFIG_IDLE_NONE (1 << 2) 149#define SYSCONFIG_IDLE_SMART (2 << 2) 150#define LCD_IRQSTATUS_RAW 0x58 151#define LCD_IRQSTATUS 0x5C 152#define LCD_IRQENABLE_SET 0x60 153#define LCD_IRQENABLE_CLEAR 0x64 154#define IRQ_EOF1 (1 << 9) 155#define IRQ_EOF0 (1 << 8) 156#define IRQ_PL (1 << 6) 157#define IRQ_FUF (1 << 5) 158#define IRQ_ACB (1 << 3) 159#define IRQ_SYNC_LOST (1 << 2) 160#define IRQ_RASTER_DONE (1 << 1) 161#define IRQ_FRAME_DONE (1 << 0) 162#define LCD_END_OF_INT_IND 0x68 163#define LCD_CLKC_ENABLE 0x6C 164#define CLKC_ENABLE_DMA (1 << 2) 165#define CLKC_ENABLE_LDID (1 << 1) 166#define CLKC_ENABLE_CORE (1 << 0) 167#define LCD_CLKC_RESET 0x70 168#define CLKC_RESET_MAIN (1 << 3) 169#define CLKC_RESET_DMA (1 << 2) 170#define CLKC_RESET_LDID (1 << 1) 171#define CLKC_RESET_CORE (1 << 0) 172 173#define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 174#define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 175#define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 176 device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) 177#define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); 178 179#define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); 180#define LCD_WRITE4(_sc, reg, value) \ 181 bus_write_4((_sc)->sc_mem_res, reg, value); 182 183/* Backlight is controlled by eCAS interface on PWM unit 0 */ 184#define PWM_UNIT 0 185#define PWM_PERIOD 100 186 187#define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end) 188#define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay) 189#define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start) 190#define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end) 191#define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay) 192#define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start) 193 194#define MAX_PIXEL_CLOCK 126000 195#define MAX_BANDWIDTH (1280*1024*60) 196 197struct am335x_lcd_softc { 198 device_t sc_dev; 199 struct fb_info sc_fb_info; 200 struct resource *sc_mem_res; 201 struct resource *sc_irq_res; 202 void *sc_intr_hl; 203 struct mtx sc_mtx; 204 int sc_backlight; 205 struct sysctl_oid *sc_oid; 206 207 struct panel_info sc_panel; 208 209 /* Framebuffer */ 210 bus_dma_tag_t sc_dma_tag; 211 bus_dmamap_t sc_dma_map; 212 size_t sc_fb_size; 213 bus_addr_t sc_fb_phys; 214 uint8_t *sc_fb_base; 215 216 /* HDMI framer */ 217 phandle_t sc_hdmi_framer; 218 eventhandler_tag sc_hdmi_evh; 219}; 220 221static void 222am335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 223{ 224 bus_addr_t *addr; 225 226 if (err) 227 return; 228 229 addr = (bus_addr_t*)arg; 230 *addr = segs[0].ds_addr; 231} 232 233static uint32_t 234am335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) 235{ 236 uint32_t div, i; 237 uint32_t delta, min_delta; 238 239 min_delta = freq; 240 div = 255; 241 242 /* Raster mode case: divisors are in range from 2 to 255 */ 243 for (i = 2; i < 255; i++) { 244 delta = abs(reference/i - freq); 245 if (delta < min_delta) { 246 div = i; 247 min_delta = delta; 248 } 249 } 250 251 return (div); 252} 253 254static int 255am335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) 256{ 257 struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; 258 int error; 259 int backlight; 260 261 backlight = sc->sc_backlight; 262 error = sysctl_handle_int(oidp, &backlight, 0, req); 263 264 if (error != 0 || req->newptr == NULL) 265 return (error); 266 267 if (backlight < 0) 268 backlight = 0; 269 if (backlight > 100) 270 backlight = 100; 271 272 LCD_LOCK(sc); 273 error = am335x_pwm_config_ecap(PWM_UNIT, PWM_PERIOD, 274 backlight*PWM_PERIOD/100); 275 if (error == 0) 276 sc->sc_backlight = backlight; 277 LCD_UNLOCK(sc); 278 279 return (error); 280} 281 282static uint32_t 283am335x_mode_vrefresh(const struct videomode *mode) 284{ 285 uint32_t refresh; 286 287 /* Calculate vertical refresh rate */ 288 refresh = (mode->dot_clock * 1000 / mode->htotal); 289 refresh = (refresh + mode->vtotal / 2) / mode->vtotal; 290 291 if (mode->flags & VID_INTERLACE) 292 refresh *= 2; 293 if (mode->flags & VID_DBLSCAN) 294 refresh /= 2; 295 296 return refresh; 297} 298 299static int 300am335x_mode_is_valid(const struct videomode *mode) 301{ 302 uint32_t hbp, hfp, hsw; 303 uint32_t vbp, vfp, vsw; 304 305 if (mode->dot_clock > MAX_PIXEL_CLOCK) 306 return (0); 307 308 if (mode->hdisplay & 0xf) 309 return (0); 310 311 if (mode->vdisplay > 2048) 312 return (0); 313 314 /* Check ranges for timing parameters */ 315 hbp = MODE_HBP(mode) - 1; 316 hfp = MODE_HFP(mode) - 1; 317 hsw = MODE_HSW(mode) - 1; 318 vbp = MODE_VBP(mode); 319 vfp = MODE_VFP(mode); 320 vsw = MODE_VSW(mode) - 1; 321 322 if (hbp > 0x3ff) 323 return (0); 324 if (hfp > 0x3ff) 325 return (0); 326 if (hsw > 0x3ff) 327 return (0); 328 329 if (vbp > 0xff) 330 return (0); 331 if (vfp > 0xff) 332 return (0); 333 if (vsw > 0x3f) 334 return (0); 335 if (mode->vdisplay*mode->hdisplay*am335x_mode_vrefresh(mode) 336 > MAX_BANDWIDTH) 337 return (0); 338 339 return (1); 340} 341 342static void 343am335x_read_hdmi_property(device_t dev) 344{ 345 phandle_t node; 346 phandle_t hdmi_xref; 347 struct am335x_lcd_softc *sc; 348 349 sc = device_get_softc(dev); 350 node = ofw_bus_get_node(dev); 351 if (OF_getencprop(node, "hdmi", &hdmi_xref, sizeof(hdmi_xref)) == -1) 352 sc->sc_hdmi_framer = 0; 353 else 354 sc->sc_hdmi_framer = hdmi_xref; 355} 356 357static int 358am335x_read_property(device_t dev, phandle_t node, const char *name, uint32_t *val) 359{ 360 pcell_t cell; 361 362 if ((OF_getencprop(node, name, &cell, sizeof(cell))) <= 0) { 363 device_printf(dev, "missing '%s' attribute in LCD panel info\n", 364 name); 365 return (ENXIO); 366 } 367 368 *val = cell; 369 370 return (0); 371} 372 373static int 374am335x_read_timing(device_t dev, phandle_t node, struct panel_info *panel) 375{ 376 int error; 377 phandle_t timings_node, timing_node, native; 378 379 timings_node = ofw_bus_find_child(node, "display-timings"); 380 if (timings_node == 0) { 381 device_printf(dev, "no \"display-timings\" node\n"); 382 return (-1); 383 } 384 385 if (OF_searchencprop(timings_node, "native-mode", &native, 386 sizeof(native)) == -1) { 387 device_printf(dev, "no \"native-mode\" reference in \"timings\" node\n"); 388 return (-1); 389 } 390 391 timing_node = OF_node_from_xref(native); 392 393 error = 0; 394 if ((error = am335x_read_property(dev, timing_node, 395 "hactive", &panel->panel_width))) 396 goto out; 397 398 if ((error = am335x_read_property(dev, timing_node, 399 "vactive", &panel->panel_height))) 400 goto out; 401 402 if ((error = am335x_read_property(dev, timing_node, 403 "hfront-porch", &panel->panel_hfp))) 404 goto out; 405 406 if ((error = am335x_read_property(dev, timing_node, 407 "hback-porch", &panel->panel_hbp))) 408 goto out; 409 410 if ((error = am335x_read_property(dev, timing_node, 411 "hsync-len", &panel->panel_hsw))) 412 goto out; 413 414 if ((error = am335x_read_property(dev, timing_node, 415 "vfront-porch", &panel->panel_vfp))) 416 goto out; 417 418 if ((error = am335x_read_property(dev, timing_node, 419 "vback-porch", &panel->panel_vbp))) 420 goto out; 421 422 if ((error = am335x_read_property(dev, timing_node, 423 "vsync-len", &panel->panel_vsw))) 424 goto out; 425 426 if ((error = am335x_read_property(dev, timing_node, 427 "clock-frequency", &panel->panel_pxl_clk))) 428 goto out; 429 430 if ((error = am335x_read_property(dev, timing_node, 431 "pixelclk-active", &panel->pixelclk_active))) 432 goto out; 433 434 if ((error = am335x_read_property(dev, timing_node, 435 "hsync-active", &panel->hsync_active))) 436 goto out; 437 438 if ((error = am335x_read_property(dev, timing_node, 439 "vsync-active", &panel->vsync_active))) 440 goto out; 441 442out: 443 return (error); 444} 445 446static int 447am335x_read_panel_info(device_t dev, phandle_t node, struct panel_info *panel) 448{ 449 phandle_t panel_info_node; 450 451 panel_info_node = ofw_bus_find_child(node, "panel-info"); 452 if (panel_info_node == 0) 453 return (-1); 454 455 am335x_read_property(dev, panel_info_node, 456 "ac-bias", &panel->ac_bias); 457 458 am335x_read_property(dev, panel_info_node, 459 "ac-bias-intrpt", &panel->ac_bias_intrpt); 460 461 am335x_read_property(dev, panel_info_node, 462 "dma-burst-sz", &panel->dma_burst_sz); 463 464 am335x_read_property(dev, panel_info_node, 465 "bpp", &panel->bpp); 466 467 am335x_read_property(dev, panel_info_node, 468 "fdd", &panel->fdd); 469 470 am335x_read_property(dev, panel_info_node, 471 "sync-edge", &panel->sync_edge); 472 473 am335x_read_property(dev, panel_info_node, 474 "sync-ctrl", &panel->sync_ctrl); 475 476 return (0); 477} 478 479static void 480am335x_lcd_intr(void *arg) 481{ 482 struct am335x_lcd_softc *sc = arg; 483 uint32_t reg; 484 485 reg = LCD_READ4(sc, LCD_IRQSTATUS); 486 LCD_WRITE4(sc, LCD_IRQSTATUS, reg); 487 /* Read value back to make sure it reached the hardware */ 488 reg = LCD_READ4(sc, LCD_IRQSTATUS); 489 490 if (reg & IRQ_SYNC_LOST) { 491 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 492 reg &= ~RASTER_CTRL_LCDEN; 493 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 494 495 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 496 reg |= RASTER_CTRL_LCDEN; 497 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 498 goto done; 499 } 500 501 if (reg & IRQ_PL) { 502 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 503 reg &= ~RASTER_CTRL_LCDEN; 504 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 505 506 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 507 reg |= RASTER_CTRL_LCDEN; 508 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 509 goto done; 510 } 511 512 if (reg & IRQ_EOF0) { 513 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 514 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 515 reg &= ~IRQ_EOF0; 516 } 517 518 if (reg & IRQ_EOF1) { 519 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 520 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 521 reg &= ~IRQ_EOF1; 522 } 523 524 if (reg & IRQ_FUF) { 525 /* TODO: Handle FUF */ 526 } 527 528 if (reg & IRQ_ACB) { 529 /* TODO: Handle ACB */ 530 } 531 532done: 533 LCD_WRITE4(sc, LCD_END_OF_INT_IND, 0); 534 /* Read value back to make sure it reached the hardware */ 535 reg = LCD_READ4(sc, LCD_END_OF_INT_IND); 536} 537 538static const struct videomode * 539am335x_lcd_pick_mode(struct edid_info *ei) 540{ 541 const struct videomode *videomode; 542 const struct videomode *m; 543 int n; 544 545 /* Get standard VGA as default */ 546 videomode = NULL; 547 548 /* 549 * Pick a mode. 550 */ 551 if (ei->edid_preferred_mode != NULL) { 552 if (am335x_mode_is_valid(ei->edid_preferred_mode)) 553 videomode = ei->edid_preferred_mode; 554 } 555 556 if (videomode == NULL) { 557 m = ei->edid_modes; 558 559 sort_modes(ei->edid_modes, 560 &ei->edid_preferred_mode, 561 ei->edid_nmodes); 562 for (n = 0; n < ei->edid_nmodes; n++) 563 if (am335x_mode_is_valid(&m[n])) { 564 videomode = &m[n]; 565 break; 566 } 567 } 568 569 return videomode; 570} 571 572static int 573am335x_lcd_configure(struct am335x_lcd_softc *sc) 574{ 575 int div; 576 uint32_t reg, timing0, timing1, timing2; 577 uint32_t burst_log; 578 size_t dma_size; 579 uint32_t hbp, hfp, hsw; 580 uint32_t vbp, vfp, vsw; 581 uint32_t width, height; 582 unsigned int ref_freq; 583 int err; 584 585 /* 586 * try to adjust clock to get double of requested frequency 587 * HDMI/DVI displays are very sensitive to error in frequncy value 588 */ 589 if (ti_prcm_clk_set_source_freq(LCDC_CLK, sc->sc_panel.panel_pxl_clk*2)) { 590 device_printf(sc->sc_dev, "can't set source frequency\n"); 591 return (ENXIO); 592 } 593 594 if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) { 595 device_printf(sc->sc_dev, "can't get reference frequency\n"); 596 return (ENXIO); 597 } 598 599 /* Panle initialization */ 600 dma_size = round_page(sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8); 601 602 /* 603 * Now allocate framebuffer memory 604 */ 605 err = bus_dma_tag_create( 606 bus_get_dma_tag(sc->sc_dev), 607 4, 0, /* alignment, boundary */ 608 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 609 BUS_SPACE_MAXADDR, /* highaddr */ 610 NULL, NULL, /* filter, filterarg */ 611 dma_size, 1, /* maxsize, nsegments */ 612 dma_size, 0, /* maxsegsize, flags */ 613 NULL, NULL, /* lockfunc, lockarg */ 614 &sc->sc_dma_tag); 615 if (err) 616 goto done; 617 618 err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 619 BUS_DMA_COHERENT, &sc->sc_dma_map); 620 621 if (err) { 622 device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); 623 goto done; 624 } 625 626 err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 627 dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 628 629 if (err) { 630 device_printf(sc->sc_dev, "cannot load DMA map\n"); 631 goto done; 632 } 633 634 /* Make sure it's blank */ 635 memset(sc->sc_fb_base, 0x0, dma_size); 636 637 /* Calculate actual FB Size */ 638 sc->sc_fb_size = sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8; 639 640 /* Only raster mode is supported */ 641 reg = CTRL_RASTER_MODE; 642 div = am335x_lcd_calc_divisor(ref_freq, sc->sc_panel.panel_pxl_clk); 643 reg |= (div << CTRL_DIV_SHIFT); 644 LCD_WRITE4(sc, LCD_CTRL, reg); 645 646 /* Set timing */ 647 timing0 = timing1 = timing2 = 0; 648 649 hbp = sc->sc_panel.panel_hbp - 1; 650 hfp = sc->sc_panel.panel_hfp - 1; 651 hsw = sc->sc_panel.panel_hsw - 1; 652 653 vbp = sc->sc_panel.panel_vbp; 654 vfp = sc->sc_panel.panel_vfp; 655 vsw = sc->sc_panel.panel_vsw - 1; 656 657 height = sc->sc_panel.panel_height - 1; 658 width = sc->sc_panel.panel_width - 1; 659 660 /* Horizontal back porch */ 661 timing0 |= (hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; 662 timing2 |= ((hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; 663 /* Horizontal front porch */ 664 timing0 |= (hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; 665 timing2 |= ((hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; 666 /* Horizontal sync width */ 667 timing0 |= (hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; 668 timing2 |= ((hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; 669 670 /* Vertical back porch, front porch, sync width */ 671 timing1 |= (vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; 672 timing1 |= (vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; 673 timing1 |= (vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; 674 675 /* Pixels per line */ 676 timing0 |= ((width >> 10) & 1) 677 << RASTER_TIMING_0_PPLMSB_SHIFT; 678 timing0 |= ((width >> 4) & 0x3f) 679 << RASTER_TIMING_0_PPLLSB_SHIFT; 680 681 /* Lines per panel */ 682 timing1 |= (height & 0x3ff) 683 << RASTER_TIMING_1_LPP_SHIFT; 684 timing2 |= ((height >> 10 ) & 1) 685 << RASTER_TIMING_2_LPP_B10_SHIFT; 686 687 /* clock signal settings */ 688 if (sc->sc_panel.sync_ctrl) 689 timing2 |= RASTER_TIMING_2_PHSVS; 690 if (sc->sc_panel.sync_edge) 691 timing2 |= RASTER_TIMING_2_PHSVS_RISE; 692 else 693 timing2 |= RASTER_TIMING_2_PHSVS_FALL; 694 if (sc->sc_panel.hsync_active == 0) 695 timing2 |= RASTER_TIMING_2_IHS; 696 if (sc->sc_panel.vsync_active == 0) 697 timing2 |= RASTER_TIMING_2_IVS; 698 if (sc->sc_panel.pixelclk_active == 0) 699 timing2 |= RASTER_TIMING_2_IPC; 700 701 /* AC bias */ 702 timing2 |= (sc->sc_panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); 703 timing2 |= (sc->sc_panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); 704 705 LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); 706 LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); 707 LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); 708 709 /* DMA settings */ 710 reg = LCDDMA_CTRL_FB0_FB1; 711 /* Find power of 2 for current burst size */ 712 switch (sc->sc_panel.dma_burst_sz) { 713 case 1: 714 burst_log = 0; 715 break; 716 case 2: 717 burst_log = 1; 718 break; 719 case 4: 720 burst_log = 2; 721 break; 722 case 8: 723 burst_log = 3; 724 break; 725 case 16: 726 default: 727 burst_log = 4; 728 break; 729 } 730 reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); 731 /* XXX: FIFO TH */ 732 reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); 733 LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); 734 735 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 736 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 737 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 738 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 739 740 /* Enable LCD */ 741 reg = RASTER_CTRL_LCDTFT; 742 reg |= (sc->sc_panel.fdd << RASTER_CTRL_REQDLY_SHIFT); 743 reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); 744 if (sc->sc_panel.bpp >= 24) 745 reg |= RASTER_CTRL_TFT24; 746 if (sc->sc_panel.bpp == 32) 747 reg |= RASTER_CTRL_TFT24_UNPACKED; 748 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 749 750 LCD_WRITE4(sc, LCD_CLKC_ENABLE, 751 CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); 752 753 LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); 754 DELAY(100); 755 LCD_WRITE4(sc, LCD_CLKC_RESET, 0); 756 757 reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | 758 IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | 759 IRQ_FRAME_DONE; 760 LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); 761 762 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 763 reg |= RASTER_CTRL_LCDEN; 764 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 765 766 LCD_WRITE4(sc, LCD_SYSCONFIG, 767 SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); 768 769 sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); 770 sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; 771 sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; 772 sc->sc_fb_info.fb_size = sc->sc_fb_size; 773 sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = sc->sc_panel.bpp; 774 sc->sc_fb_info.fb_stride = sc->sc_panel.panel_width*sc->sc_panel.bpp / 8; 775 sc->sc_fb_info.fb_width = sc->sc_panel.panel_width; 776 sc->sc_fb_info.fb_height = sc->sc_panel.panel_height; 777 778#ifdef DEV_SC 779 err = (sc_attach_unit(device_get_unit(sc->sc_dev), 780 device_get_flags(sc->sc_dev) | SC_AUTODETECT_KBD)); 781 782 if (err) { 783 device_printf(sc->sc_dev, "failed to attach syscons\n"); 784 goto fail; 785 } 786 787 am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); 788#else /* VT */ 789 device_t fbd = device_add_child(sc->sc_dev, "fbd", 790 device_get_unit(sc->sc_dev)); 791 if (fbd != NULL) { 792 if (device_probe_and_attach(fbd) != 0) 793 device_printf(sc->sc_dev, "failed to attach fbd device\n"); 794 } else 795 device_printf(sc->sc_dev, "failed to add fbd child\n"); 796#endif 797 798done: 799 return (err); 800} 801 802static void 803am335x_lcd_hdmi_event(void *arg, device_t hdmi, int event) 804{ 805 struct am335x_lcd_softc *sc; 806 const struct videomode *videomode; 807 struct videomode hdmi_mode; 808 device_t hdmi_dev; 809 uint8_t *edid; 810 uint32_t edid_len; 811 struct edid_info ei; 812 813 sc = arg; 814 815 /* Nothing to work with */ 816 if (!sc->sc_hdmi_framer) { 817 device_printf(sc->sc_dev, "HDMI event without HDMI framer set\n"); 818 return; 819 } 820 821 hdmi_dev = OF_device_from_xref(sc->sc_hdmi_framer); 822 if (!hdmi_dev) { 823 device_printf(sc->sc_dev, "no actual device for \"hdmi\" property\n"); 824 return; 825 } 826 827 edid = NULL; 828 edid_len = 0; 829 if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { 830 device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); 831 return; 832 } 833 834 videomode = NULL; 835 836 if (edid_parse(edid, &ei) == 0) { 837 edid_print(&ei); 838 videomode = am335x_lcd_pick_mode(&ei); 839 } else 840 device_printf(sc->sc_dev, "failed to parse EDID\n"); 841 842 /* Use standard VGA as fallback */ 843 if (videomode == NULL) 844 videomode = pick_mode_by_ref(640, 480, 60); 845 846 if (videomode == NULL) { 847 device_printf(sc->sc_dev, "failed to find usable videomode"); 848 return; 849 } 850 851 device_printf(sc->sc_dev, "detected videomode: %dx%d @ %dKHz\n", videomode->hdisplay, 852 videomode->vdisplay, am335x_mode_vrefresh(videomode)); 853 854 sc->sc_panel.panel_width = videomode->hdisplay; 855 sc->sc_panel.panel_height = videomode->vdisplay; 856 sc->sc_panel.panel_hfp = videomode->hsync_start - videomode->hdisplay; 857 sc->sc_panel.panel_hbp = videomode->htotal - videomode->hsync_end; 858 sc->sc_panel.panel_hsw = videomode->hsync_end - videomode->hsync_start; 859 sc->sc_panel.panel_vfp = videomode->vsync_start - videomode->vdisplay; 860 sc->sc_panel.panel_vbp = videomode->vtotal - videomode->vsync_end; 861 sc->sc_panel.panel_vsw = videomode->vsync_end - videomode->vsync_start; 862 sc->sc_panel.pixelclk_active = 1; 863 864 /* logic for HSYNC should be reversed */ 865 if (videomode->flags & VID_NHSYNC) 866 sc->sc_panel.hsync_active = 1; 867 else 868 sc->sc_panel.hsync_active = 0; 869 870 if (videomode->flags & VID_NVSYNC) 871 sc->sc_panel.vsync_active = 0; 872 else 873 sc->sc_panel.vsync_active = 1; 874 875 sc->sc_panel.panel_pxl_clk = videomode->dot_clock * 1000; 876 877 am335x_lcd_configure(sc); 878 879 memcpy(&hdmi_mode, videomode, sizeof(hdmi_mode)); 880 hdmi_mode.hskew = videomode->hsync_end - videomode->hsync_start; 881 hdmi_mode.flags |= VID_HSKEW; 882 883 HDMI_SET_VIDEOMODE(hdmi_dev, &hdmi_mode); 884} 885 886static int 887am335x_lcd_probe(device_t dev) 888{ 889#ifdef DEV_SC 890 int err; 891#endif 892 893 if (!ofw_bus_status_okay(dev)) 894 return (ENXIO); 895 896 if (!ofw_bus_is_compatible(dev, "ti,am33xx-tilcdc")) 897 return (ENXIO); 898 899 device_set_desc(dev, "AM335x LCD controller"); 900 901#ifdef DEV_SC 902 err = sc_probe_unit(device_get_unit(dev), 903 device_get_flags(dev) | SC_AUTODETECT_KBD); 904 if (err != 0) 905 return (err); 906#endif 907 908 return (BUS_PROBE_DEFAULT); 909} 910 911static int 912am335x_lcd_attach(device_t dev) 913{ 914 struct am335x_lcd_softc *sc; 915 916 int err; 917 int rid; 918 struct sysctl_ctx_list *ctx; 919 struct sysctl_oid *tree; 920 phandle_t root, panel_node; 921 922 err = 0; 923 sc = device_get_softc(dev); 924 sc->sc_dev = dev; 925 926 am335x_read_hdmi_property(dev); 927 928 root = OF_finddevice("/"); 929 if (root == 0) { 930 device_printf(dev, "failed to get FDT root node\n"); 931 return (ENXIO); 932 } 933 934 sc->sc_panel.ac_bias = 255; 935 sc->sc_panel.ac_bias_intrpt = 0; 936 sc->sc_panel.dma_burst_sz = 16; 937 sc->sc_panel.bpp = 16; 938 sc->sc_panel.fdd = 128; 939 sc->sc_panel.sync_edge = 0; 940 sc->sc_panel.sync_ctrl = 1; 941 942 panel_node = fdt_find_compatible(root, "ti,tilcdc,panel", 1); 943 if (panel_node != 0) { 944 device_printf(dev, "using static panel info\n"); 945 if (am335x_read_panel_info(dev, panel_node, &sc->sc_panel)) { 946 device_printf(dev, "failed to read panel info\n"); 947 return (ENXIO); 948 } 949 950 if (am335x_read_timing(dev, panel_node, &sc->sc_panel)) { 951 device_printf(dev, "failed to read timings\n"); 952 return (ENXIO); 953 } 954 } 955 956 ti_prcm_clk_enable(LCDC_CLK); 957 958 rid = 0; 959 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 960 RF_ACTIVE); 961 if (!sc->sc_mem_res) { 962 device_printf(dev, "cannot allocate memory window\n"); 963 return (ENXIO); 964 } 965 966 rid = 0; 967 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 968 RF_ACTIVE); 969 if (!sc->sc_irq_res) { 970 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 971 device_printf(dev, "cannot allocate interrupt\n"); 972 return (ENXIO); 973 } 974 975 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 976 NULL, am335x_lcd_intr, sc, 977 &sc->sc_intr_hl) != 0) { 978 bus_release_resource(dev, SYS_RES_IRQ, rid, 979 sc->sc_irq_res); 980 bus_release_resource(dev, SYS_RES_MEMORY, rid, 981 sc->sc_mem_res); 982 device_printf(dev, "Unable to setup the irq handler.\n"); 983 return (ENXIO); 984 } 985 986 LCD_LOCK_INIT(sc); 987 988 /* Init backlight interface */ 989 ctx = device_get_sysctl_ctx(sc->sc_dev); 990 tree = device_get_sysctl_tree(sc->sc_dev); 991 sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 992 "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 993 am335x_lcd_sysctl_backlight, "I", "LCD backlight"); 994 sc->sc_backlight = 0; 995 /* Check if eCAS interface is available at this point */ 996 if (am335x_pwm_config_ecap(PWM_UNIT, 997 PWM_PERIOD, PWM_PERIOD) == 0) 998 sc->sc_backlight = 100; 999 1000 if (panel_node != 0) 1001 am335x_lcd_configure(sc); 1002 else 1003 sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, 1004 am335x_lcd_hdmi_event, sc, EVENTHANDLER_PRI_ANY); 1005 1006 return (0); 1007} 1008 1009static int 1010am335x_lcd_detach(device_t dev) 1011{ 1012 /* Do not let unload driver */ 1013 return (EBUSY); 1014} 1015 1016static struct fb_info * 1017am335x_lcd_fb_getinfo(device_t dev) 1018{ 1019 struct am335x_lcd_softc *sc; 1020 1021 sc = device_get_softc(dev); 1022 1023 return (&sc->sc_fb_info); 1024} 1025 1026static device_method_t am335x_lcd_methods[] = { 1027 DEVMETHOD(device_probe, am335x_lcd_probe), 1028 DEVMETHOD(device_attach, am335x_lcd_attach), 1029 DEVMETHOD(device_detach, am335x_lcd_detach), 1030 1031 /* Framebuffer service methods */ 1032 DEVMETHOD(fb_getinfo, am335x_lcd_fb_getinfo), 1033 1034 DEVMETHOD_END 1035}; 1036 1037static driver_t am335x_lcd_driver = { 1038 "fb", 1039 am335x_lcd_methods, 1040 sizeof(struct am335x_lcd_softc), 1041}; 1042 1043static devclass_t am335x_lcd_devclass; 1044 1045DRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0); 1046MODULE_VERSION(am335x_lcd, 1); 1047MODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); 1048