if_ixgb.h revision 330897
1139743Simp/******************************************************************************* 2123474SwpaulSPDX-License-Identifier: BSD-3-Clause 3123474Swpaul 4123474SwpaulCopyright (c) 2001-2004, Intel Corporation 5123474SwpaulAll rights reserved. 6123474Swpaul 7123474SwpaulRedistribution and use in source and binary forms, with or without 8123474Swpaulmodification, are permitted provided that the following conditions are met: 9123474Swpaul 10123474Swpaul 1. Redistributions of source code must retain the above copyright notice, 11123474Swpaul this list of conditions and the following disclaimer. 12123474Swpaul 13123474Swpaul 2. Redistributions in binary form must reproduce the above copyright 14123474Swpaul notice, this list of conditions and the following disclaimer in the 15123474Swpaul documentation and/or other materials provided with the distribution. 16123474Swpaul 17123474Swpaul 3. Neither the name of the Intel Corporation nor the names of its 18123474Swpaul contributors may be used to endorse or promote products derived from 19123474Swpaul this software without specific prior written permission. 20123474Swpaul 21123474SwpaulTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22123474SwpaulAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23123474SwpaulIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24123474SwpaulARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25123474SwpaulLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26123474SwpaulCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27123474SwpaulSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28123474SwpaulINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29123474SwpaulCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30123474SwpaulARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31123474SwpaulPOSSIBILITY OF SUCH DAMAGE. 32123474Swpaul 33123474Swpaul***************************************************************************/ 34123474Swpaul/*$FreeBSD: stable/11/sys/dev/ixgb/if_ixgb.h 330897 2018-03-14 03:19:51Z eadler $*/ 35123474Swpaul 36123474Swpaul#ifndef _IXGB_H_DEFINED_ 37123474Swpaul#define _IXGB_H_DEFINED_ 38123474Swpaul 39123474Swpaul 40123474Swpaul#include <sys/param.h> 41123474Swpaul#include <sys/systm.h> 42123474Swpaul#include <sys/mbuf.h> 43123474Swpaul#include <sys/protosw.h> 44123474Swpaul#include <sys/socket.h> 45123474Swpaul#include <sys/malloc.h> 46123474Swpaul#include <sys/module.h> 47123474Swpaul#include <sys/kernel.h> 48123474Swpaul#include <sys/sockio.h> 49123474Swpaul 50123474Swpaul#include <net/if.h> 51123474Swpaul#include <net/if_var.h> 52129834Swpaul#include <net/if_arp.h> 53123474Swpaul#include <net/ethernet.h> 54123474Swpaul#include <net/if_dl.h> 55123474Swpaul#include <net/if_media.h> 56123474Swpaul#include <net/if_types.h> 57123474Swpaul 58123474Swpaul#include <net/bpf.h> 59123474Swpaul#include <net/if_types.h> 60123474Swpaul#include <net/if_vlan_var.h> 61123474Swpaul 62123474Swpaul#include <netinet/in_systm.h> 63123474Swpaul#include <netinet/in.h> 64123474Swpaul#include <netinet/ip.h> 65123504Swpaul#include <netinet/tcp.h> 66123848Swpaul#include <netinet/udp.h> 67124122Swpaul 68124272Swpaul#include <sys/bus.h> 69125377Swpaul#include <machine/bus.h> 70124272Swpaul#include <sys/rman.h> 71124272Swpaul#include <machine/resource.h> 72124272Swpaul#if __FreeBSD_version >= 502000 73125551Swpaul#include <dev/pci/pcivar.h> 74132973Swpaul#include <dev/pci/pcireg.h> 75132973Swpaul#else 76132973Swpaul#include <pci/pcivar.h> 77123474Swpaul#include <pci/pcireg.h> 78123474Swpaul#endif 79123474Swpaul#include <sys/proc.h> 80123474Swpaul#include <sys/sysctl.h> 81123474Swpaul#include <sys/endian.h> 82123474Swpaul 83123474Swpaul#include <dev/ixgb/ixgb_hw.h> 84124203Swpaul#include <dev/ixgb/ixgb_ee.h> 85123474Swpaul#include <dev/ixgb/ixgb_ids.h> 86123474Swpaul 87123474Swpaul/* Tunables */ 88123474Swpaul 89123474Swpaul/* 90123474Swpaul * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 91123474Swpaul * number of transmit descriptors allocated by the driver. Increasing this 92123474Swpaul * value allows the driver to queue more transmits. Each descriptor is 16 93123474Swpaul * bytes. 94123474Swpaul */ 95123695Swpaul#define IXGB_MAX_TXD 256 96123695Swpaul 97123695Swpaul/* 98123474Swpaul * RxDescriptors Valid Range: 64-4096 Default Value: 1024 This value is the 99123474Swpaul * number of receive descriptors allocated by the driver. Increasing this 100123474Swpaul * value allows the driver to buffer more incoming packets. Each descriptor 101123474Swpaul * is 16 bytes. A receive buffer is also allocated for each descriptor. The 102123474Swpaul * maximum MTU size is 16110. 103123512Swpaul * 104128229Swpaul */ 105123474Swpaul#define IXGB_MAX_RXD 1024 106123474Swpaul 107123474Swpaul/* 108123474Swpaul * TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value 109124272Swpaul * delays the generation of transmit interrupts in units of 1.024 110125057Swpaul * microseconds. Transmit interrupt reduction can improve CPU efficiency if 111123474Swpaul * properly tuned for specific network traffic. If the system is reporting 112124272Swpaul * dropped transmits, this value may be set too high causing the driver to 113124272Swpaul * run out of available transmit descriptors. 114124272Swpaul */ 115140751Swpaul#define TIDV 32 116141524Swpaul 117140751Swpaul/* 118123474Swpaul * RxIntDelay Valid Range: 0-65535 (0=off) Default Value: 72 This value 119140751Swpaul * delays the generation of receive interrupts in units of 1.024 120140751Swpaul * microseconds. Receive interrupt reduction can improve CPU efficiency if 121140751Swpaul * properly tuned for specific network traffic. Increasing this value adds 122123474Swpaul * extra latency to frame reception and can end up decreasing the throughput 123140751Swpaul * of TCP traffic. If the system is reporting dropped receives, this value 124140751Swpaul * may be set too high, causing the driver to run out of available receive 125123474Swpaul * descriptors. 126140751Swpaul * 127140751Swpaul */ 128140751Swpaul#define RDTR 72 129140751Swpaul 130140751Swpaul 131140751Swpaul/* 132123474Swpaul * This parameter controls the maximum no of times the driver will loop in 133123474Swpaul * the isr. Minimum Value = 1 134123526Swpaul */ 135123526Swpaul#define IXGB_MAX_INTR 3 136140751Swpaul 137123474Swpaul 138140751Swpaul/* 139123526Swpaul * Inform the stack about transmit checksum offload capabilities. 140140751Swpaul */ 141140751Swpaul#define IXGB_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 142140751Swpaul 143140751Swpaul/* 144140751Swpaul * This parameter controls the duration of transmit watchdog timer. 145140751Swpaul */ 146140751Swpaul#define IXGB_TX_TIMEOUT 5 /* set to 5 seconds */ 147140751Swpaul 148123474Swpaul/* 149140751Swpaul * This parameter controls when the driver calls the routine to reclaim 150123474Swpaul * transmit descriptors. 151140751Swpaul */ 152123474Swpaul#define IXGB_TX_CLEANUP_THRESHOLD IXGB_MAX_TXD / 8 153140751Swpaul 154140751Swpaul/* 155140751Swpaul * Flow Control Types. 156140751Swpaul * 1. ixgb_fc_none - Flow Control Disabled 157140751Swpaul * 2. ixgb_fc_rx_pause - Flow Control Receive Only 158123474Swpaul * 3. ixgb_fc_tx_pause - Flow Control Transmit Only 159140751Swpaul * 4. ixgb_fc_full - Flow Control Enabled 160125057Swpaul */ 161140751Swpaul#define FLOW_CONTROL_NONE ixgb_fc_none 162140751Swpaul#define FLOW_CONTROL_RX_PAUSE ixgb_fc_rx_pause 163140751Swpaul#define FLOW_CONTROL_TX_PAUSE ixgb_fc_tx_pause 164140751Swpaul#define FLOW_CONTROL_FULL ixgb_fc_full 165123474Swpaul 166140751Swpaul/* 167123474Swpaul * Set the flow control type. Assign one of the above flow control types to be enabled. 168140751Swpaul * Default Value: FLOW_CONTROL_FULL 169123474Swpaul */ 170140751Swpaul#define FLOW_CONTROL FLOW_CONTROL_FULL 171123474Swpaul 172140751Swpaul/* 173140751Swpaul * Receive Flow control low threshold (when we send a resume frame) (FCRTL) 174123474Swpaul * Valid Range: 64 - 262,136 (0x40 - 0x3FFF8, 8 byte granularity) must be 175140751Swpaul * less than high threshold by at least 8 bytes Default Value: 163,840 176123474Swpaul * (0x28000) 177140751Swpaul */ 178123474Swpaul#define FCRTL 0x28000 179125413Swpaul 180140751Swpaul/* 181123474Swpaul * Receive Flow control high threshold (when we send a pause frame) (FCRTH) 182140751Swpaul * Valid Range: 1,536 - 262,136 (0x600 - 0x3FFF8, 8 byte granularity) Default 183123474Swpaul * Value: 196,608 (0x30000) 184140751Swpaul */ 185123474Swpaul#define FCRTH 0x30000 186140751Swpaul 187140751Swpaul/* 188140751Swpaul * Flow control request timeout (how long to pause the link partner's tx) 189140751Swpaul * (PAP 15:0) Valid Range: 1 - 65535 Default Value: 256 (0x100) 190123474Swpaul */ 191140751Swpaul#define FCPAUSE 0x100 192140751Swpaul 193140751Swpaul/* Tunables -- End */ 194123474Swpaul 195140751Swpaul 196140751Swpaul#define IXGB_VENDOR_ID 0x8086 197123474Swpaul#define IXGB_MMBA 0x0010 /* Mem base address */ 198140751Swpaul#define IXGB_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 199140751Swpaul 200140751Swpaul#define IOCTL_CMD_TYPE u_long 201140751Swpaul#define MAX_NUM_MULTICAST_ADDRESSES 128 202123474Swpaul#define PCI_ANY_ID (~0U) 203140751Swpaul#define ETHER_ALIGN 2 204140751Swpaul 205140751Swpaul/* Defines for printing debug information */ 206140751Swpaul#define DEBUG_INIT 0 207140751Swpaul#define DEBUG_IOCTL 0 208140751Swpaul#define DEBUG_HW 0 209140751Swpaul#define _SV_ 0 210140751Swpaul 211140751Swpaul#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 212140751Swpaul#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 213123474Swpaul#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 214140751Swpaul#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 215140751Swpaul#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 216123526Swpaul#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 217140751Swpaul#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 218123474Swpaul#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 219140751Swpaul#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 220123474Swpaul 221123474Swpaul 222140751Swpaul/* Supported RX Buffer Sizes */ 223140751Swpaul#define IXGB_RXBUFFER_2048 2048 224123474Swpaul#define IXGB_RXBUFFER_4096 4096 225140751Swpaul#define IXGB_RXBUFFER_8192 8192 226140751Swpaul#define IXGB_RXBUFFER_16384 16384 227140751Swpaul 228140751Swpaul#define IXGB_MAX_SCATTER 100 229140751Swpaul 230123474Swpaul/* 231140751Swpaul * ****************************************************************************** 232140751Swpaul * vendor_info_array 233123474Swpaul * 234140751Swpaul * This array contains the list of Subvendor/Subdevice IDs on which the driver 235123474Swpaul * should load. 236140751Swpaul * 237125551Swpaul***************************************************************************** 238140751Swpaul */ 239123474Swpaultypedef struct _ixgb_vendor_info_t { 240140751Swpaul unsigned int vendor_id; 241125551Swpaul unsigned int device_id; 242140751Swpaul unsigned int subvendor_id; 243140751Swpaul unsigned int subdevice_id; 244123474Swpaul unsigned int index; 245140751Swpaul} ixgb_vendor_info_t; 246140751Swpaul 247140751Swpaul 248140751Swpaulstruct ixgb_buffer { 249140751Swpaul struct mbuf *m_head; 250123941Swpaul bus_dmamap_t map; /* bus_dma map for packet */ 251140751Swpaul}; 252140751Swpaul 253140751Swpaul/* 254140751Swpaul * Bus dma allocation structure used by ixgb_dma_malloc and ixgb_dma_free. 255125551Swpaul */ 256125551Swpaulstruct ixgb_dma_alloc { 257140751Swpaul bus_addr_t dma_paddr; 258140751Swpaul caddr_t dma_vaddr; 259140751Swpaul bus_dma_tag_t dma_tag; 260140751Swpaul bus_dmamap_t dma_map; 261132973Swpaul bus_dma_segment_t dma_seg; 262140751Swpaul bus_size_t dma_size; 263123822Swpaul int dma_nseg; 264140751Swpaul}; 265140751Swpaul 266140751Swpaultypedef enum _XSUM_CONTEXT_T { 267140751Swpaul OFFLOAD_NONE, 268140751Swpaul OFFLOAD_TCP_IP, 269140751Swpaul OFFLOAD_UDP_IP 270124116Swpaul} XSUM_CONTEXT_T; 271124697Swpaul 272140751Swpaul/* Our adapter structure */ 273140751Swpaulstruct adapter { 274140751Swpaul struct ifnet *ifp; 275140751Swpaul struct adapter *next; 276140751Swpaul struct adapter *prev; 277140751Swpaul struct ixgb_hw hw; 278125551Swpaul 279125551Swpaul /* FreeBSD operating-system-specific structures */ 280140751Swpaul struct ixgb_osdep osdep; 281140751Swpaul struct device *dev; 282140751Swpaul struct resource *res_memory; 283125551Swpaul struct resource *res_ioport; 284140751Swpaul struct resource *res_interrupt; 285123474Swpaul void *int_handler_tag; 286123474Swpaul struct ifmedia media; 287124116Swpaul struct callout timer; 288124116Swpaul int io_rid; 289124116Swpaul int tx_timer; 290124116Swpaul struct mtx mtx; 291124116Swpaul 292124116Swpaul /* Info about the board itself */ 293124116Swpaul u_int32_t part_num; 294124116Swpaul u_int8_t link_active; 295124116Swpaul u_int16_t link_speed; 296123474Swpaul u_int16_t link_duplex; 297123474Swpaul u_int32_t tx_int_delay; 298123474Swpaul u_int32_t tx_abs_int_delay; 299123474Swpaul u_int32_t rx_int_delay; 300141963Swpaul u_int32_t rx_abs_int_delay; 301141963Swpaul 302124272Swpaul int raidc; 303141963Swpaul 304141963Swpaul XSUM_CONTEXT_T active_checksum_context; 305141963Swpaul 306141963Swpaul /* 307141963Swpaul * Transmit definitions 308141963Swpaul * 309141963Swpaul * We have an array of num_tx_desc descriptors (handled by the 310141963Swpaul * controller) paired with an array of tx_buffers (at 311123474Swpaul * tx_buffer_area). The index of the next available descriptor is 312123474Swpaul * next_avail_tx_desc. The number of remaining tx_desc is 313123474Swpaul * num_tx_desc_avail. 314123474Swpaul */ 315123474Swpaul struct ixgb_dma_alloc txdma; /* bus_dma glue for tx desc */ 316123474Swpaul struct ixgb_tx_desc *tx_desc_base; 317141963Swpaul u_int32_t next_avail_tx_desc; 318141963Swpaul u_int32_t oldest_used_tx_desc; 319141963Swpaul volatile u_int16_t num_tx_desc_avail; 320141963Swpaul u_int16_t num_tx_desc; 321141963Swpaul u_int32_t txd_cmd; 322141963Swpaul struct ixgb_buffer *tx_buffer_area; 323141963Swpaul bus_dma_tag_t txtag; /* dma tag for tx */ 324141963Swpaul 325123474Swpaul /* 326123474Swpaul * Receive definitions 327123474Swpaul * 328123474Swpaul * we have an array of num_rx_desc rx_desc (handled by the controller), 329123474Swpaul * and paired with an array of rx_buffers (at rx_buffer_area). The 330123474Swpaul * next pair to check on receive is at offset next_rx_desc_to_check 331123474Swpaul */ 332123474Swpaul struct ixgb_dma_alloc rxdma; /* bus_dma glue for rx desc */ 333123474Swpaul struct ixgb_rx_desc *rx_desc_base; 334123474Swpaul u_int32_t next_rx_desc_to_check; 335123474Swpaul u_int16_t num_rx_desc; 336123474Swpaul u_int32_t rx_buffer_len; 337123474Swpaul struct ixgb_buffer *rx_buffer_area; 338123474Swpaul bus_dma_tag_t rxtag; /* dma tag for Rx */ 339123474Swpaul u_int32_t next_rx_desc_to_use; 340123474Swpaul 341123474Swpaul 342123474Swpaul /* Jumbo frame */ 343123474Swpaul struct mbuf *fmp; 344123474Swpaul struct mbuf *lmp; 345123474Swpaul 346123474Swpaul struct sysctl_ctx_list sysctl_ctx; 347123474Swpaul struct sysctl_oid *sysctl_tree; 348123474Swpaul 349123474Swpaul /* Multicast array memory */ 350123474Swpaul u_int8_t *mta; 351123474Swpaul /* Misc stats maintained by the driver */ 352123474Swpaul unsigned long dropped_pkts; 353123474Swpaul unsigned long mbuf_alloc_failed; 354123474Swpaul unsigned long mbuf_cluster_failed; 355123474Swpaul unsigned long no_tx_desc_avail1; 356123474Swpaul unsigned long no_tx_desc_avail2; 357123474Swpaul unsigned long no_tx_map_avail; 358123474Swpaul unsigned long no_tx_dma_setup; 359123474Swpaul 360123474Swpaul boolean_t in_detach; 361123474Swpaul 362123474Swpaul /* Board specific private data */ 363123474Swpaul#ifdef _SV_ 364123474Swpaul struct ixgb_sv_stats { 365123474Swpaul uint64_t icr_rxdmt0; 366123474Swpaul uint64_t icr_rxo; 367124100Swpaul uint64_t icr_rxt0; 368123474Swpaul uint64_t icr_TXDW; 369123474Swpaul } sv_stats; 370123474Swpaul unsigned long no_pkts_avail; 371124100Swpaul unsigned long clean_tx_interrupts; 372123474Swpaul#endif 373123474Swpaul 374123474Swpaul struct ixgb_hw_stats stats; 375123474Swpaul}; 376123474Swpaul 377123474Swpaul#define IXGB_LOCK_INIT(_sc, _name) \ 378123474Swpaul mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 379141524Swpaul#define IXGB_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 380141524Swpaul#define IXGB_LOCK(_sc) mtx_lock(&(_sc)->mtx) 381141524Swpaul#define IXGB_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 382141524Swpaul#define IXGB_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 383141524Swpaul 384123474Swpaul#endif /* _IXGB_H_DEFINED_ */ 385141524Swpaul