if_ath_beacon.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/sys/dev/ath/if_ath_beacon.c 330897 2018-03-14 03:19:51Z eadler $"); 34 35/* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42#include "opt_inet.h" 43#include "opt_ath.h" 44/* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51#include "opt_ah.h" 52#include "opt_wlan.h" 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/sysctl.h> 57#include <sys/mbuf.h> 58#include <sys/malloc.h> 59#include <sys/lock.h> 60#include <sys/mutex.h> 61#include <sys/kernel.h> 62#include <sys/socket.h> 63#include <sys/sockio.h> 64#include <sys/errno.h> 65#include <sys/callout.h> 66#include <sys/bus.h> 67#include <sys/endian.h> 68#include <sys/kthread.h> 69#include <sys/taskqueue.h> 70#include <sys/priv.h> 71#include <sys/module.h> 72#include <sys/ktr.h> 73#include <sys/smp.h> /* for mp_ncpus */ 74 75#include <machine/bus.h> 76 77#include <net/if.h> 78#include <net/if_var.h> 79#include <net/if_dl.h> 80#include <net/if_media.h> 81#include <net/if_types.h> 82#include <net/if_arp.h> 83#include <net/ethernet.h> 84#include <net/if_llc.h> 85 86#include <net80211/ieee80211_var.h> 87#include <net80211/ieee80211_regdomain.h> 88#ifdef IEEE80211_SUPPORT_SUPERG 89#include <net80211/ieee80211_superg.h> 90#endif 91 92#include <net/bpf.h> 93 94#ifdef INET 95#include <netinet/in.h> 96#include <netinet/if_ether.h> 97#endif 98 99#include <dev/ath/if_athvar.h> 100 101#include <dev/ath/if_ath_debug.h> 102#include <dev/ath/if_ath_misc.h> 103#include <dev/ath/if_ath_tx.h> 104#include <dev/ath/if_ath_beacon.h> 105 106#ifdef ATH_TX99_DIAG 107#include <dev/ath/ath_tx99/ath_tx99.h> 108#endif 109 110/* 111 * Setup a h/w transmit queue for beacons. 112 */ 113int 114ath_beaconq_setup(struct ath_softc *sc) 115{ 116 struct ath_hal *ah = sc->sc_ah; 117 HAL_TXQ_INFO qi; 118 119 memset(&qi, 0, sizeof(qi)); 120 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 121 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 122 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 123 /* NB: for dynamic turbo, don't enable any other interrupts */ 124 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 125 if (sc->sc_isedma) 126 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE | 127 HAL_TXQ_TXERRINT_ENABLE; 128 129 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 130} 131 132/* 133 * Setup the transmit queue parameters for the beacon queue. 134 */ 135int 136ath_beaconq_config(struct ath_softc *sc) 137{ 138#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 139 struct ieee80211com *ic = &sc->sc_ic; 140 struct ath_hal *ah = sc->sc_ah; 141 HAL_TXQ_INFO qi; 142 143 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 144 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 145 ic->ic_opmode == IEEE80211_M_MBSS) { 146 /* 147 * Always burst out beacon and CAB traffic. 148 */ 149 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 150 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 151 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 152 } else { 153 struct wmeParams *wmep = 154 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 155 /* 156 * Adhoc mode; important thing is to use 2x cwmin. 157 */ 158 qi.tqi_aifs = wmep->wmep_aifsn; 159 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 160 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 161 } 162 163 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 164 device_printf(sc->sc_dev, "unable to update parameters for " 165 "beacon hardware queue!\n"); 166 return 0; 167 } else { 168 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 169 return 1; 170 } 171#undef ATH_EXPONENT_TO_VALUE 172} 173 174/* 175 * Allocate and setup an initial beacon frame. 176 */ 177int 178ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 179{ 180 struct ieee80211vap *vap = ni->ni_vap; 181 struct ath_vap *avp = ATH_VAP(vap); 182 struct ath_buf *bf; 183 struct mbuf *m; 184 int error; 185 186 bf = avp->av_bcbuf; 187 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n", 188 __func__, bf->bf_m, bf->bf_node); 189 if (bf->bf_m != NULL) { 190 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 191 m_freem(bf->bf_m); 192 bf->bf_m = NULL; 193 } 194 if (bf->bf_node != NULL) { 195 ieee80211_free_node(bf->bf_node); 196 bf->bf_node = NULL; 197 } 198 199 /* 200 * NB: the beacon data buffer must be 32-bit aligned; 201 * we assume the mbuf routines will return us something 202 * with this alignment (perhaps should assert). 203 */ 204 m = ieee80211_beacon_alloc(ni); 205 if (m == NULL) { 206 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 207 sc->sc_stats.ast_be_nombuf++; 208 return ENOMEM; 209 } 210 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 211 bf->bf_segs, &bf->bf_nseg, 212 BUS_DMA_NOWAIT); 213 if (error != 0) { 214 device_printf(sc->sc_dev, 215 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 216 __func__, error); 217 m_freem(m); 218 return error; 219 } 220 221 /* 222 * Calculate a TSF adjustment factor required for staggered 223 * beacons. Note that we assume the format of the beacon 224 * frame leaves the tstamp field immediately following the 225 * header. 226 */ 227 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 228 uint64_t tsfadjust; 229 struct ieee80211_frame *wh; 230 231 /* 232 * The beacon interval is in TU's; the TSF is in usecs. 233 * We figure out how many TU's to add to align the timestamp 234 * then convert to TSF units and handle byte swapping before 235 * inserting it in the frame. The hardware will then add this 236 * each time a beacon frame is sent. Note that we align vap's 237 * 1..N and leave vap 0 untouched. This means vap 0 has a 238 * timestamp in one beacon interval while the others get a 239 * timstamp aligned to the next interval. 240 */ 241 tsfadjust = ni->ni_intval * 242 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 243 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 244 245 DPRINTF(sc, ATH_DEBUG_BEACON, 246 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 247 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 248 avp->av_bslot, ni->ni_intval, 249 (long long unsigned) le64toh(tsfadjust)); 250 251 wh = mtod(m, struct ieee80211_frame *); 252 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 253 } 254 bf->bf_m = m; 255 bf->bf_node = ieee80211_ref_node(ni); 256 257 return 0; 258} 259 260/* 261 * Setup the beacon frame for transmit. 262 */ 263static void 264ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 265{ 266#define USE_SHPREAMBLE(_ic) \ 267 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 268 == IEEE80211_F_SHPREAMBLE) 269 struct ieee80211_node *ni = bf->bf_node; 270 struct ieee80211com *ic = ni->ni_ic; 271 struct mbuf *m = bf->bf_m; 272 struct ath_hal *ah = sc->sc_ah; 273 struct ath_desc *ds; 274 int flags, antenna; 275 const HAL_RATE_TABLE *rt; 276 u_int8_t rix, rate; 277 HAL_DMA_ADDR bufAddrList[4]; 278 uint32_t segLenList[4]; 279 HAL_11N_RATE_SERIES rc[4]; 280 281 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 282 __func__, m, m->m_len); 283 284 /* setup descriptors */ 285 ds = bf->bf_desc; 286 bf->bf_last = bf; 287 bf->bf_lastds = ds; 288 289 flags = HAL_TXDESC_NOACK; 290 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 291 /* self-linked descriptor */ 292 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr); 293 flags |= HAL_TXDESC_VEOL; 294 /* 295 * Let hardware handle antenna switching. 296 */ 297 antenna = sc->sc_txantenna; 298 } else { 299 ath_hal_settxdesclink(sc->sc_ah, ds, 0); 300 /* 301 * Switch antenna every 4 beacons. 302 * XXX assumes two antenna 303 */ 304 if (sc->sc_txantenna != 0) 305 antenna = sc->sc_txantenna; 306 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 307 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 308 else 309 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 310 } 311 312 KASSERT(bf->bf_nseg == 1, 313 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 314 315 /* 316 * Calculate rate code. 317 * XXX everything at min xmit rate 318 */ 319 rix = 0; 320 rt = sc->sc_currates; 321 rate = rt->info[rix].rateCode; 322 if (USE_SHPREAMBLE(ic)) 323 rate |= rt->info[rix].shortPreamble; 324 ath_hal_setuptxdesc(ah, ds 325 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 326 , sizeof(struct ieee80211_frame)/* header length */ 327 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 328 , ieee80211_get_node_txpower(ni) /* txpower XXX */ 329 , rate, 1 /* series 0 rate/tries */ 330 , HAL_TXKEYIX_INVALID /* no encryption */ 331 , antenna /* antenna mode */ 332 , flags /* no ack, veol for beacons */ 333 , 0 /* rts/cts rate */ 334 , 0 /* rts/cts duration */ 335 ); 336 337 /* 338 * The EDMA HAL currently assumes that _all_ rate control 339 * settings are done in ath_hal_set11nratescenario(), rather 340 * than in ath_hal_setuptxdesc(). 341 */ 342 if (sc->sc_isedma) { 343 memset(&rc, 0, sizeof(rc)); 344 345 rc[0].ChSel = sc->sc_txchainmask; 346 rc[0].Tries = 1; 347 rc[0].Rate = rt->info[rix].rateCode; 348 rc[0].RateIndex = rix; 349 rc[0].tx_power_cap = 0x3f; 350 rc[0].PktDuration = 351 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4), 352 rix, 0); 353 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags); 354 } 355 356 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 357 segLenList[0] = roundup(m->m_len, 4); 358 segLenList[1] = segLenList[2] = segLenList[3] = 0; 359 bufAddrList[0] = bf->bf_segs[0].ds_addr; 360 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0; 361 ath_hal_filltxdesc(ah, ds 362 , bufAddrList 363 , segLenList 364 , 0 /* XXX desc id */ 365 , sc->sc_bhalq /* hardware TXQ */ 366 , AH_TRUE /* first segment */ 367 , AH_TRUE /* last segment */ 368 , ds /* first descriptor */ 369 ); 370#if 0 371 ath_desc_swap(ds); 372#endif 373#undef USE_SHPREAMBLE 374} 375 376void 377ath_beacon_update(struct ieee80211vap *vap, int item) 378{ 379 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 380 381 setbit(bo->bo_flags, item); 382} 383 384/* 385 * Handle a beacon miss. 386 */ 387void 388ath_beacon_miss(struct ath_softc *sc) 389{ 390 HAL_SURVEY_SAMPLE hs; 391 HAL_BOOL ret; 392 uint32_t hangs; 393 394 bzero(&hs, sizeof(hs)); 395 396 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs); 397 398 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) { 399 DPRINTF(sc, ATH_DEBUG_BEACON, 400 "%s: hang=0x%08x\n", 401 __func__, 402 hangs); 403 } 404 405#ifdef ATH_DEBUG_ALQ 406 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON)) 407 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL); 408#endif 409 410 DPRINTF(sc, ATH_DEBUG_BEACON, 411 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, " 412 "extchanbusy=%u, cyclecount=%u\n", 413 __func__, 414 ret, 415 hs.tx_busy, 416 hs.rx_busy, 417 hs.chan_busy, 418 hs.ext_chan_busy, 419 hs.cycle_count); 420} 421 422/* 423 * Transmit a beacon frame at SWBA. Dynamic updates to the 424 * frame contents are done as needed and the slot time is 425 * also adjusted based on current state. 426 */ 427void 428ath_beacon_proc(void *arg, int pending) 429{ 430 struct ath_softc *sc = arg; 431 struct ath_hal *ah = sc->sc_ah; 432 struct ieee80211vap *vap; 433 struct ath_buf *bf; 434 int slot, otherant; 435 uint32_t bfaddr; 436 437 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 438 __func__, pending); 439 /* 440 * Check if the previous beacon has gone out. If 441 * not don't try to post another, skip this period 442 * and wait for the next. Missed beacons indicate 443 * a problem and should not occur. If we miss too 444 * many consecutive beacons reset the device. 445 */ 446 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 447 sc->sc_bmisscount++; 448 sc->sc_stats.ast_be_missed++; 449 ath_beacon_miss(sc); 450 DPRINTF(sc, ATH_DEBUG_BEACON, 451 "%s: missed %u consecutive beacons\n", 452 __func__, sc->sc_bmisscount); 453 if (sc->sc_bmisscount >= ath_bstuck_threshold) 454 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 455 return; 456 } 457 if (sc->sc_bmisscount != 0) { 458 DPRINTF(sc, ATH_DEBUG_BEACON, 459 "%s: resume beacon xmit after %u misses\n", 460 __func__, sc->sc_bmisscount); 461 sc->sc_bmisscount = 0; 462#ifdef ATH_DEBUG_ALQ 463 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON)) 464 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL); 465#endif 466 } 467 468 if (sc->sc_stagbeacons) { /* staggered beacons */ 469 struct ieee80211com *ic = &sc->sc_ic; 470 uint32_t tsftu; 471 472 tsftu = ath_hal_gettsf32(ah) >> 10; 473 /* XXX lintval */ 474 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 475 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 476 bfaddr = 0; 477 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 478 bf = ath_beacon_generate(sc, vap); 479 if (bf != NULL) 480 bfaddr = bf->bf_daddr; 481 } 482 } else { /* burst'd beacons */ 483 uint32_t *bflink = &bfaddr; 484 485 for (slot = 0; slot < ATH_BCBUF; slot++) { 486 vap = sc->sc_bslot[slot]; 487 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 488 bf = ath_beacon_generate(sc, vap); 489 /* 490 * XXX TODO: this should use settxdesclinkptr() 491 * otherwise it won't work for EDMA chipsets! 492 */ 493 if (bf != NULL) { 494 /* XXX should do this using the ds */ 495 *bflink = bf->bf_daddr; 496 ath_hal_gettxdesclinkptr(sc->sc_ah, 497 bf->bf_desc, &bflink); 498 } 499 } 500 } 501 /* 502 * XXX TODO: this should use settxdesclinkptr() 503 * otherwise it won't work for EDMA chipsets! 504 */ 505 *bflink = 0; /* terminate list */ 506 } 507 508 /* 509 * Handle slot time change when a non-ERP station joins/leaves 510 * an 11g network. The 802.11 layer notifies us via callback, 511 * we mark updateslot, then wait one beacon before effecting 512 * the change. This gives associated stations at least one 513 * beacon interval to note the state change. 514 */ 515 /* XXX locking */ 516 if (sc->sc_updateslot == UPDATE) { 517 sc->sc_updateslot = COMMIT; /* commit next beacon */ 518 sc->sc_slotupdate = slot; 519 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 520 ath_setslottime(sc); /* commit change to h/w */ 521 522 /* 523 * Check recent per-antenna transmit statistics and flip 524 * the default antenna if noticeably more frames went out 525 * on the non-default antenna. 526 * XXX assumes 2 anntenae 527 */ 528 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 529 otherant = sc->sc_defant & 1 ? 2 : 1; 530 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 531 ath_setdefantenna(sc, otherant); 532 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 533 } 534 535 /* Program the CABQ with the contents of the CABQ txq and start it */ 536 ATH_TXQ_LOCK(sc->sc_cabq); 537 ath_beacon_cabq_start(sc); 538 ATH_TXQ_UNLOCK(sc->sc_cabq); 539 540 /* Program the new beacon frame if we have one for this interval */ 541 if (bfaddr != 0) { 542 /* 543 * Stop any current dma and put the new frame on the queue. 544 * This should never fail since we check above that no frames 545 * are still pending on the queue. 546 */ 547 if (! sc->sc_isedma) { 548 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 549 DPRINTF(sc, ATH_DEBUG_ANY, 550 "%s: beacon queue %u did not stop?\n", 551 __func__, sc->sc_bhalq); 552 } 553 } 554 /* NB: cabq traffic should already be queued and primed */ 555 556 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 557 ath_hal_txstart(ah, sc->sc_bhalq); 558 559 sc->sc_stats.ast_be_xmit++; 560 } 561} 562 563static void 564ath_beacon_cabq_start_edma(struct ath_softc *sc) 565{ 566 struct ath_buf *bf, *bf_last; 567 struct ath_txq *cabq = sc->sc_cabq; 568#if 0 569 struct ath_buf *bfi; 570 int i = 0; 571#endif 572 573 ATH_TXQ_LOCK_ASSERT(cabq); 574 575 if (TAILQ_EMPTY(&cabq->axq_q)) 576 return; 577 bf = TAILQ_FIRST(&cabq->axq_q); 578 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s); 579 580 /* 581 * This is a dirty, dirty hack to push the contents of 582 * the cabq staging queue into the FIFO. 583 * 584 * This ideally should live in the EDMA code file 585 * and only push things into the CABQ if there's a FIFO 586 * slot. 587 * 588 * We can't treat this like a normal TX queue because 589 * in the case of multi-VAP traffic, we may have to flush 590 * the CABQ each new (staggered) beacon that goes out. 591 * But for non-staggered beacons, we could in theory 592 * handle multicast traffic for all VAPs in one FIFO 593 * push. Just keep all of this in mind if you're wondering 594 * how to correctly/better handle multi-VAP CABQ traffic 595 * with EDMA. 596 */ 597 598 /* 599 * Is the CABQ FIFO free? If not, complain loudly and 600 * don't queue anything. Maybe we'll flush the CABQ 601 * traffic, maybe we won't. But that'll happen next 602 * beacon interval. 603 */ 604 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) { 605 device_printf(sc->sc_dev, 606 "%s: Q%d: CAB FIFO queue=%d?\n", 607 __func__, 608 cabq->axq_qnum, 609 cabq->axq_fifo_depth); 610 return; 611 } 612 613 /* 614 * Ok, so here's the gymnastics reqiured to make this 615 * all sensible. 616 */ 617 618 /* 619 * Tag the first/last buffer appropriately. 620 */ 621 bf->bf_flags |= ATH_BUF_FIFOPTR; 622 bf_last->bf_flags |= ATH_BUF_FIFOEND; 623 624#if 0 625 i = 0; 626 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) { 627 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0); 628 i++; 629 } 630#endif 631 632 /* 633 * We now need to push this set of frames onto the tail 634 * of the FIFO queue. We don't adjust the aggregate 635 * count, only the queue depth counter(s). 636 * We also need to blank the link pointer now. 637 */ 638 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list); 639 cabq->axq_link = NULL; 640 cabq->fifo.axq_depth += cabq->axq_depth; 641 cabq->axq_depth = 0; 642 643 /* Bump FIFO queue */ 644 cabq->axq_fifo_depth++; 645 646 /* Push the first entry into the hardware */ 647 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 648 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 649 650 /* NB: gated by beacon so safe to start here */ 651 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 652 653} 654 655static void 656ath_beacon_cabq_start_legacy(struct ath_softc *sc) 657{ 658 struct ath_buf *bf; 659 struct ath_txq *cabq = sc->sc_cabq; 660 661 ATH_TXQ_LOCK_ASSERT(cabq); 662 if (TAILQ_EMPTY(&cabq->axq_q)) 663 return; 664 bf = TAILQ_FIRST(&cabq->axq_q); 665 666 /* Push the first entry into the hardware */ 667 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 668 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 669 670 /* NB: gated by beacon so safe to start here */ 671 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 672} 673 674/* 675 * Start CABQ transmission - this assumes that all frames are prepped 676 * and ready in the CABQ. 677 */ 678void 679ath_beacon_cabq_start(struct ath_softc *sc) 680{ 681 struct ath_txq *cabq = sc->sc_cabq; 682 683 ATH_TXQ_LOCK_ASSERT(cabq); 684 685 if (TAILQ_EMPTY(&cabq->axq_q)) 686 return; 687 688 if (sc->sc_isedma) 689 ath_beacon_cabq_start_edma(sc); 690 else 691 ath_beacon_cabq_start_legacy(sc); 692} 693 694struct ath_buf * 695ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 696{ 697 struct ath_vap *avp = ATH_VAP(vap); 698 struct ath_txq *cabq = sc->sc_cabq; 699 struct ath_buf *bf; 700 struct mbuf *m; 701 int nmcastq, error; 702 703 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 704 ("not running, state %d", vap->iv_state)); 705 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 706 707 /* 708 * Update dynamic beacon contents. If this returns 709 * non-zero then we need to remap the memory because 710 * the beacon frame changed size (probably because 711 * of the TIM bitmap). 712 */ 713 bf = avp->av_bcbuf; 714 m = bf->bf_m; 715 /* XXX lock mcastq? */ 716 nmcastq = avp->av_mcastq.axq_depth; 717 718 if (ieee80211_beacon_update(bf->bf_node, m, nmcastq)) { 719 /* XXX too conservative? */ 720 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 721 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 722 bf->bf_segs, &bf->bf_nseg, 723 BUS_DMA_NOWAIT); 724 if (error != 0) { 725 if_printf(vap->iv_ifp, 726 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 727 __func__, error); 728 return NULL; 729 } 730 } 731 if ((vap->iv_bcn_off.bo_tim[4] & 1) && cabq->axq_depth) { 732 DPRINTF(sc, ATH_DEBUG_BEACON, 733 "%s: cabq did not drain, mcastq %u cabq %u\n", 734 __func__, nmcastq, cabq->axq_depth); 735 sc->sc_stats.ast_cabq_busy++; 736 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 737 /* 738 * CABQ traffic from a previous vap is still pending. 739 * We must drain the q before this beacon frame goes 740 * out as otherwise this vap's stations will get cab 741 * frames from a different vap. 742 * XXX could be slow causing us to miss DBA 743 */ 744 /* 745 * XXX TODO: this doesn't stop CABQ DMA - it assumes 746 * that since we're about to transmit a beacon, we've 747 * already stopped transmitting on the CABQ. But this 748 * doesn't at all mean that the CABQ DMA QCU will 749 * accept a new TXDP! So what, should we do a DMA 750 * stop? What if it fails? 751 * 752 * More thought is required here. 753 */ 754 /* 755 * XXX can we even stop TX DMA here? Check what the 756 * reference driver does for cabq for beacons, given 757 * that stopping TX requires RX is paused. 758 */ 759 ath_tx_draintxq(sc, cabq); 760 } 761 } 762 ath_beacon_setup(sc, bf); 763 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 764 765 /* 766 * Enable the CAB queue before the beacon queue to 767 * insure cab frames are triggered by this beacon. 768 */ 769 if (vap->iv_bcn_off.bo_tim[4] & 1) { 770 771 /* NB: only at DTIM */ 772 ATH_TXQ_LOCK(&avp->av_mcastq); 773 if (nmcastq) { 774 struct ath_buf *bfm, *bfc_last; 775 776 /* 777 * Move frames from the s/w mcast q to the h/w cab q. 778 * 779 * XXX TODO: if we chain together multiple VAPs 780 * worth of CABQ traffic, should we keep the 781 * MORE data bit set on the last frame of each 782 * intermediary VAP (ie, only clear the MORE 783 * bit of the last frame on the last vap?) 784 */ 785 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q); 786 ATH_TXQ_LOCK(cabq); 787 788 /* 789 * If there's already a frame on the CABQ, we 790 * need to link to the end of the last frame. 791 * We can't use axq_link here because 792 * EDMA descriptors require some recalculation 793 * (checksum) to occur. 794 */ 795 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s); 796 if (bfc_last != NULL) { 797 ath_hal_settxdesclink(sc->sc_ah, 798 bfc_last->bf_lastds, 799 bfm->bf_daddr); 800 } 801 ath_txqmove(cabq, &avp->av_mcastq); 802 ATH_TXQ_UNLOCK(cabq); 803 /* 804 * XXX not entirely accurate, in case a mcast 805 * queue frame arrived before we grabbed the TX 806 * lock. 807 */ 808 sc->sc_stats.ast_cabq_xmit += nmcastq; 809 } 810 ATH_TXQ_UNLOCK(&avp->av_mcastq); 811 } 812 return bf; 813} 814 815void 816ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 817{ 818 struct ath_vap *avp = ATH_VAP(vap); 819 struct ath_hal *ah = sc->sc_ah; 820 struct ath_buf *bf; 821 struct mbuf *m; 822 int error; 823 824 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 825 826 /* 827 * Update dynamic beacon contents. If this returns 828 * non-zero then we need to remap the memory because 829 * the beacon frame changed size (probably because 830 * of the TIM bitmap). 831 */ 832 bf = avp->av_bcbuf; 833 m = bf->bf_m; 834 if (ieee80211_beacon_update(bf->bf_node, m, 0)) { 835 /* XXX too conservative? */ 836 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 837 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 838 bf->bf_segs, &bf->bf_nseg, 839 BUS_DMA_NOWAIT); 840 if (error != 0) { 841 if_printf(vap->iv_ifp, 842 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 843 __func__, error); 844 return; 845 } 846 } 847 ath_beacon_setup(sc, bf); 848 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 849 850 /* NB: caller is known to have already stopped tx dma */ 851 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 852 ath_hal_txstart(ah, sc->sc_bhalq); 853} 854 855/* 856 * Reclaim beacon resources and return buffer to the pool. 857 */ 858void 859ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 860{ 861 862 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 863 __func__, bf, bf->bf_m, bf->bf_node); 864 if (bf->bf_m != NULL) { 865 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 866 m_freem(bf->bf_m); 867 bf->bf_m = NULL; 868 } 869 if (bf->bf_node != NULL) { 870 ieee80211_free_node(bf->bf_node); 871 bf->bf_node = NULL; 872 } 873 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 874} 875 876/* 877 * Reclaim beacon resources. 878 */ 879void 880ath_beacon_free(struct ath_softc *sc) 881{ 882 struct ath_buf *bf; 883 884 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 885 DPRINTF(sc, ATH_DEBUG_NODE, 886 "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 887 __func__, bf, bf->bf_m, bf->bf_node); 888 if (bf->bf_m != NULL) { 889 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 890 m_freem(bf->bf_m); 891 bf->bf_m = NULL; 892 } 893 if (bf->bf_node != NULL) { 894 ieee80211_free_node(bf->bf_node); 895 bf->bf_node = NULL; 896 } 897 } 898} 899 900/* 901 * Configure the beacon and sleep timers. 902 * 903 * When operating as an AP this resets the TSF and sets 904 * up the hardware to notify us when we need to issue beacons. 905 * 906 * When operating in station mode this sets up the beacon 907 * timers according to the timestamp of the last received 908 * beacon and the current TSF, configures PCF and DTIM 909 * handling, programs the sleep registers so the hardware 910 * will wakeup in time to receive beacons, and configures 911 * the beacon miss handling so we'll receive a BMISS 912 * interrupt when we stop seeing beacons from the AP 913 * we've associated with. 914 */ 915void 916ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 917{ 918#define TSF_TO_TU(_h,_l) \ 919 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 920#define FUDGE 2 921 struct ath_hal *ah = sc->sc_ah; 922 struct ieee80211com *ic = &sc->sc_ic; 923 struct ieee80211_node *ni; 924 u_int32_t nexttbtt, intval, tsftu; 925 u_int32_t nexttbtt_u8, intval_u8; 926 u_int64_t tsf, tsf_beacon; 927 928 if (vap == NULL) 929 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 930 /* 931 * Just ensure that we aren't being called when the last 932 * VAP is destroyed. 933 */ 934 if (vap == NULL) { 935 device_printf(sc->sc_dev, "%s: called with no VAPs\n", 936 __func__); 937 return; 938 } 939 940 ni = ieee80211_ref_node(vap->iv_bss); 941 942 ATH_LOCK(sc); 943 ath_power_set_power_state(sc, HAL_PM_AWAKE); 944 ATH_UNLOCK(sc); 945 946 /* extract tstamp from last beacon and convert to TU */ 947 nexttbtt = TSF_TO_TU(le32dec(ni->ni_tstamp.data + 4), 948 le32dec(ni->ni_tstamp.data)); 949 950 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 951 tsf_beacon |= le32dec(ni->ni_tstamp.data); 952 953 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 954 ic->ic_opmode == IEEE80211_M_MBSS) { 955 /* 956 * For multi-bss ap/mesh support beacons are either staggered 957 * evenly over N slots or burst together. For the former 958 * arrange for the SWBA to be delivered for each slot. 959 * Slots that are not occupied will generate nothing. 960 */ 961 /* NB: the beacon interval is kept internally in TU's */ 962 intval = ni->ni_intval & HAL_BEACON_PERIOD; 963 if (sc->sc_stagbeacons) 964 intval /= ATH_BCBUF; 965 } else { 966 /* NB: the beacon interval is kept internally in TU's */ 967 intval = ni->ni_intval & HAL_BEACON_PERIOD; 968 } 969 if (nexttbtt == 0) /* e.g. for ap mode */ 970 nexttbtt = intval; 971 else if (intval) /* NB: can be 0 for monitor mode */ 972 nexttbtt = roundup(nexttbtt, intval); 973 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 974 __func__, nexttbtt, intval, ni->ni_intval); 975 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 976 HAL_BEACON_STATE bs; 977 int dtimperiod, dtimcount; 978 int cfpperiod, cfpcount; 979 980 /* 981 * Setup dtim and cfp parameters according to 982 * last beacon we received (which may be none). 983 */ 984 dtimperiod = ni->ni_dtim_period; 985 if (dtimperiod <= 0) /* NB: 0 if not known */ 986 dtimperiod = 1; 987 dtimcount = ni->ni_dtim_count; 988 if (dtimcount >= dtimperiod) /* NB: sanity check */ 989 dtimcount = 0; /* XXX? */ 990 cfpperiod = 1; /* NB: no PCF support yet */ 991 cfpcount = 0; 992 /* 993 * Pull nexttbtt forward to reflect the current 994 * TSF and calculate dtim+cfp state for the result. 995 */ 996 tsf = ath_hal_gettsf64(ah); 997 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 998 999 DPRINTF(sc, ATH_DEBUG_BEACON, 1000 "%s: beacon tsf=%llu, hw tsf=%llu, nexttbtt=%u, tsftu=%u\n", 1001 __func__, 1002 (unsigned long long) tsf_beacon, 1003 (unsigned long long) tsf, 1004 nexttbtt, 1005 tsftu); 1006 DPRINTF(sc, ATH_DEBUG_BEACON, 1007 "%s: beacon tsf=%llu, hw tsf=%llu, tsf delta=%lld\n", 1008 __func__, 1009 (unsigned long long) tsf_beacon, 1010 (unsigned long long) tsf, 1011 (long long) tsf - 1012 (long long) tsf_beacon); 1013 1014 DPRINTF(sc, ATH_DEBUG_BEACON, 1015 "%s: nexttbtt=%llu, beacon tsf delta=%lld\n", 1016 __func__, 1017 (unsigned long long) nexttbtt, 1018 (long long) ((long long) nexttbtt * 1024LL) - (long long) tsf_beacon); 1019 1020 /* XXX cfpcount? */ 1021 1022 if (nexttbtt > tsftu) { 1023 uint32_t countdiff, oldtbtt, remainder; 1024 1025 oldtbtt = nexttbtt; 1026 remainder = (nexttbtt - tsftu) % intval; 1027 nexttbtt = tsftu + remainder; 1028 1029 countdiff = (oldtbtt - nexttbtt) / intval % dtimperiod; 1030 if (dtimcount > countdiff) { 1031 dtimcount -= countdiff; 1032 } else { 1033 dtimcount += dtimperiod - countdiff; 1034 } 1035 } else { //nexttbtt <= tsftu 1036 uint32_t countdiff, oldtbtt, remainder; 1037 1038 oldtbtt = nexttbtt; 1039 remainder = (tsftu - nexttbtt) % intval; 1040 nexttbtt = tsftu - remainder + intval; 1041 countdiff = (nexttbtt - oldtbtt) / intval % dtimperiod; 1042 if (dtimcount > countdiff) { 1043 dtimcount -= countdiff; 1044 } else { 1045 dtimcount += dtimperiod - countdiff; 1046 } 1047 } 1048 1049 DPRINTF(sc, ATH_DEBUG_BEACON, 1050 "%s: adj nexttbtt=%llu, rx tsf delta=%lld\n", 1051 __func__, 1052 (unsigned long long) nexttbtt, 1053 (long long) ((long long)nexttbtt * 1024LL) - (long long)tsf); 1054 1055 memset(&bs, 0, sizeof(bs)); 1056 bs.bs_intval = intval; 1057 bs.bs_nexttbtt = nexttbtt; 1058 bs.bs_dtimperiod = dtimperiod*intval; 1059 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 1060 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 1061 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 1062 bs.bs_cfpmaxduration = 0; 1063#if 0 1064 /* 1065 * The 802.11 layer records the offset to the DTIM 1066 * bitmap while receiving beacons; use it here to 1067 * enable h/w detection of our AID being marked in 1068 * the bitmap vector (to indicate frames for us are 1069 * pending at the AP). 1070 * XXX do DTIM handling in s/w to WAR old h/w bugs 1071 * XXX enable based on h/w rev for newer chips 1072 */ 1073 bs.bs_timoffset = ni->ni_timoff; 1074#endif 1075 /* 1076 * Calculate the number of consecutive beacons to miss 1077 * before taking a BMISS interrupt. 1078 * Note that we clamp the result to at most 10 beacons. 1079 */ 1080 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 1081 if (bs.bs_bmissthreshold > 10) 1082 bs.bs_bmissthreshold = 10; 1083 else if (bs.bs_bmissthreshold <= 0) 1084 bs.bs_bmissthreshold = 1; 1085 1086 /* 1087 * Calculate sleep duration. The configuration is 1088 * given in ms. We insure a multiple of the beacon 1089 * period is used. Also, if the sleep duration is 1090 * greater than the DTIM period then it makes senses 1091 * to make it a multiple of that. 1092 * 1093 * XXX fixed at 100ms 1094 */ 1095 bs.bs_sleepduration = 1096 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 1097 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1098 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1099 1100 DPRINTF(sc, ATH_DEBUG_BEACON, 1101 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u " 1102 "nextdtim %u bmiss %u sleep %u cfp:period %u " 1103 "maxdur %u next %u timoffset %u\n" 1104 , __func__ 1105 , tsf 1106 , tsftu 1107 , bs.bs_intval 1108 , bs.bs_nexttbtt 1109 , bs.bs_dtimperiod 1110 , bs.bs_nextdtim 1111 , bs.bs_bmissthreshold 1112 , bs.bs_sleepduration 1113 , bs.bs_cfpperiod 1114 , bs.bs_cfpmaxduration 1115 , bs.bs_cfpnext 1116 , bs.bs_timoffset 1117 ); 1118 ath_hal_intrset(ah, 0); 1119 ath_hal_beacontimers(ah, &bs); 1120 sc->sc_imask |= HAL_INT_BMISS; 1121 ath_hal_intrset(ah, sc->sc_imask); 1122 } else { 1123 ath_hal_intrset(ah, 0); 1124 if (nexttbtt == intval) 1125 intval |= HAL_BEACON_RESET_TSF; 1126 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1127 /* 1128 * In IBSS mode enable the beacon timers but only 1129 * enable SWBA interrupts if we need to manually 1130 * prepare beacon frames. Otherwise we use a 1131 * self-linked tx descriptor and let the hardware 1132 * deal with things. 1133 */ 1134 intval |= HAL_BEACON_ENA; 1135 if (!sc->sc_hasveol) 1136 sc->sc_imask |= HAL_INT_SWBA; 1137 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 1138 /* 1139 * Pull nexttbtt forward to reflect 1140 * the current TSF. 1141 */ 1142 tsf = ath_hal_gettsf64(ah); 1143 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1144 do { 1145 nexttbtt += intval; 1146 } while (nexttbtt < tsftu); 1147 } 1148 ath_beaconq_config(sc); 1149 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1150 ic->ic_opmode == IEEE80211_M_MBSS) { 1151 /* 1152 * In AP/mesh mode we enable the beacon timers 1153 * and SWBA interrupts to prepare beacon frames. 1154 */ 1155 intval |= HAL_BEACON_ENA; 1156 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1157 ath_beaconq_config(sc); 1158 } 1159 1160 /* 1161 * Now dirty things because for now, the EDMA HAL has 1162 * nexttbtt and intval is TU/8. 1163 */ 1164 if (sc->sc_isedma) { 1165 nexttbtt_u8 = (nexttbtt << 3); 1166 intval_u8 = (intval << 3); 1167 if (intval & HAL_BEACON_ENA) 1168 intval_u8 |= HAL_BEACON_ENA; 1169 if (intval & HAL_BEACON_RESET_TSF) 1170 intval_u8 |= HAL_BEACON_RESET_TSF; 1171 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8); 1172 } else 1173 ath_hal_beaconinit(ah, nexttbtt, intval); 1174 sc->sc_bmisscount = 0; 1175 ath_hal_intrset(ah, sc->sc_imask); 1176 /* 1177 * When using a self-linked beacon descriptor in 1178 * ibss mode load it once here. 1179 */ 1180 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 1181 ath_beacon_start_adhoc(sc, vap); 1182 } 1183 ieee80211_free_node(ni); 1184 1185 ATH_LOCK(sc); 1186 ath_power_restore_power_state(sc); 1187 ATH_UNLOCK(sc); 1188#undef FUDGE 1189#undef TSF_TO_TU 1190} 1191