iw_cxgbe.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses.  You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 *     Redistribution and use in source and binary forms, with or
13 *     without modification, are permitted provided that the following
14 *     conditions are met:
15 *
16 *      - Redistributions of source code must retain the above
17 *	  copyright notice, this list of conditions and the following
18 *	  disclaimer.
19 *      - Redistributions in binary form must reproduce the above
20 *	  copyright notice, this list of conditions and the following
21 *	  disclaimer in the documentation and/or other materials
22 *	  provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 * $FreeBSD: stable/11/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h 330897 2018-03-14 03:19:51Z eadler $
34 */
35#ifndef __IW_CXGB4_H__
36#define __IW_CXGB4_H__
37
38#include <linux/list.h>
39#include <linux/spinlock.h>
40#include <linux/idr.h>
41#include <linux/completion.h>
42#include <linux/netdevice.h>
43#include <linux/sched.h>
44#include <linux/pci.h>
45#include <linux/dma-mapping.h>
46#include <linux/wait.h>
47#include <linux/kref.h>
48#include <linux/timer.h>
49#include <linux/io.h>
50#include <sys/vmem.h>
51
52#include <asm/byteorder.h>
53
54#include <netinet/in.h>
55#include <netinet/toecore.h>
56
57#include <rdma/ib_verbs.h>
58#include <rdma/iw_cm.h>
59
60#undef prefetch
61
62#include "common/common.h"
63#include "common/t4_msg.h"
64#include "common/t4_regs.h"
65#include "common/t4_tcb.h"
66#include "t4_l2t.h"
67
68#define DRV_NAME "iw_cxgbe"
69#define MOD DRV_NAME ":"
70#define KTR_IW_CXGBE	KTR_SPARE3
71
72extern int c4iw_debug;
73#define PDBG(fmt, args...) \
74do { \
75	if (c4iw_debug) \
76		printf(MOD fmt, ## args); \
77} while (0)
78
79#include "t4.h"
80
81static inline void *cplhdr(struct mbuf *m)
82{
83	return mtod(m, void*);
84}
85
86#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
87#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
88
89#define C4IW_ID_TABLE_F_RANDOM 1       /* Pseudo-randomize the id's returned */
90#define C4IW_ID_TABLE_F_EMPTY  2       /* Table is initially empty */
91
92struct c4iw_id_table {
93	u32 flags;
94	u32 start;              /* logical minimal id */
95	u32 last;               /* hint for find */
96	u32 max;
97	spinlock_t lock;
98	unsigned long *table;
99};
100
101struct c4iw_resource {
102	struct c4iw_id_table tpt_table;
103	struct c4iw_id_table qid_table;
104	struct c4iw_id_table pdid_table;
105};
106
107struct c4iw_qid_list {
108	struct list_head entry;
109	u32 qid;
110};
111
112struct c4iw_dev_ucontext {
113	struct list_head qpids;
114	struct list_head cqids;
115	struct mutex lock;
116};
117
118enum c4iw_rdev_flags {
119	T4_FATAL_ERROR = (1<<0),
120};
121
122struct c4iw_stat {
123	u64 total;
124	u64 cur;
125	u64 max;
126	u64 fail;
127};
128
129struct c4iw_stats {
130	struct mutex lock;
131	struct c4iw_stat qid;
132	struct c4iw_stat pd;
133	struct c4iw_stat stag;
134	struct c4iw_stat pbl;
135	struct c4iw_stat rqt;
136};
137
138struct c4iw_rdev {
139	struct adapter *adap;
140	struct c4iw_resource resource;
141	unsigned long qpshift;
142	u32 qpmask;
143	unsigned long cqshift;
144	u32 cqmask;
145	struct c4iw_dev_ucontext uctx;
146	vmem_t          *rqt_arena;
147	vmem_t          *pbl_arena;
148	u32 flags;
149	struct c4iw_stats stats;
150};
151
152static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
153{
154	return rdev->flags & T4_FATAL_ERROR;
155}
156
157static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
158{
159	return (int)(rdev->adap->vres.stag.size >> 5);
160}
161
162#define C4IW_WR_TO (60*HZ)
163
164struct c4iw_wr_wait {
165	int ret;
166	struct completion completion;
167};
168
169static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
170{
171	wr_waitp->ret = 0;
172	init_completion(&wr_waitp->completion);
173}
174
175static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
176{
177	wr_waitp->ret = ret;
178	complete(&wr_waitp->completion);
179}
180
181static inline int
182c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
183					u32 hwtid, u32 qpid, const char *func)
184{
185	struct adapter *sc = rdev->adap;
186	unsigned to = C4IW_WR_TO;
187	int ret;
188	int timedout = 0;
189	struct timeval t1, t2;
190
191	if (c4iw_fatal_error(rdev)) {
192		wr_waitp->ret = -EIO;
193		goto out;
194	}
195
196	getmicrotime(&t1);
197	do {
198		ret = wait_for_completion_timeout(&wr_waitp->completion, to);
199		if (!ret) {
200			getmicrotime(&t2);
201			timevalsub(&t2, &t1);
202			printf("%s - Device %s not responding after %ld.%06ld "
203			    "seconds - tid %u qpid %u\n", func,
204			    device_get_nameunit(sc->dev), t2.tv_sec, t2.tv_usec,
205			    hwtid, qpid);
206			if (c4iw_fatal_error(rdev)) {
207				wr_waitp->ret = -EIO;
208				break;
209			}
210			to = to << 2;
211			timedout = 1;
212		}
213	} while (!ret);
214
215out:
216	if (timedout) {
217		getmicrotime(&t2);
218		timevalsub(&t2, &t1);
219		printf("%s - Device %s reply after %ld.%06ld seconds - "
220		    "tid %u qpid %u\n", func, device_get_nameunit(sc->dev),
221		    t2.tv_sec, t2.tv_usec, hwtid, qpid);
222	}
223	if (wr_waitp->ret)
224		CTR4(KTR_IW_CXGBE, "%p: FW reply %d tid %u qpid %u", sc,
225		    wr_waitp->ret, hwtid, qpid);
226	return (wr_waitp->ret);
227}
228
229struct c4iw_dev {
230	struct ib_device ibdev;
231	struct c4iw_rdev rdev;
232	u32 device_cap_flags;
233	struct idr cqidr;
234	struct idr qpidr;
235	struct idr mmidr;
236	spinlock_t lock;
237	struct dentry *debugfs_root;
238};
239
240static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
241{
242	return container_of(ibdev, struct c4iw_dev, ibdev);
243}
244
245static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
246{
247	return container_of(rdev, struct c4iw_dev, rdev);
248}
249
250static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
251{
252	return idr_find(&rhp->cqidr, cqid);
253}
254
255static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
256{
257	return idr_find(&rhp->qpidr, qpid);
258}
259
260static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
261{
262	return idr_find(&rhp->mmidr, mmid);
263}
264
265static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
266				 void *handle, u32 id, int lock)
267{
268	int ret;
269	int newid;
270
271	do {
272		if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
273			return -ENOMEM;
274		if (lock)
275			spin_lock_irq(&rhp->lock);
276		ret = idr_get_new_above(idr, handle, id, &newid);
277		BUG_ON(!ret && newid != id);
278		if (lock)
279			spin_unlock_irq(&rhp->lock);
280	} while (ret == -EAGAIN);
281
282	return ret;
283}
284
285static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
286				void *handle, u32 id)
287{
288	return _insert_handle(rhp, idr, handle, id, 1);
289}
290
291static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
292				       void *handle, u32 id)
293{
294	return _insert_handle(rhp, idr, handle, id, 0);
295}
296
297static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
298				   u32 id, int lock)
299{
300	if (lock)
301		spin_lock_irq(&rhp->lock);
302	idr_remove(idr, id);
303	if (lock)
304		spin_unlock_irq(&rhp->lock);
305}
306
307static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
308{
309	_remove_handle(rhp, idr, id, 1);
310}
311
312static inline void remove_handle_nolock(struct c4iw_dev *rhp,
313					 struct idr *idr, u32 id)
314{
315	_remove_handle(rhp, idr, id, 0);
316}
317
318struct c4iw_pd {
319	struct ib_pd ibpd;
320	u32 pdid;
321	struct c4iw_dev *rhp;
322};
323
324static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
325{
326	return container_of(ibpd, struct c4iw_pd, ibpd);
327}
328
329struct tpt_attributes {
330	u64 len;
331	u64 va_fbo;
332	enum fw_ri_mem_perms perms;
333	u32 stag;
334	u32 pdid;
335	u32 qpid;
336	u32 pbl_addr;
337	u32 pbl_size;
338	u32 state:1;
339	u32 type:2;
340	u32 rsvd:1;
341	u32 remote_invaliate_disable:1;
342	u32 zbva:1;
343	u32 mw_bind_enable:1;
344	u32 page_size:5;
345};
346
347struct c4iw_mr {
348	struct ib_mr ibmr;
349	struct ib_umem *umem;
350	struct c4iw_dev *rhp;
351	u64 kva;
352	struct tpt_attributes attr;
353};
354
355static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
356{
357	return container_of(ibmr, struct c4iw_mr, ibmr);
358}
359
360struct c4iw_mw {
361	struct ib_mw ibmw;
362	struct c4iw_dev *rhp;
363	u64 kva;
364	struct tpt_attributes attr;
365};
366
367static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
368{
369	return container_of(ibmw, struct c4iw_mw, ibmw);
370}
371
372struct c4iw_fr_page_list {
373	struct ib_fast_reg_page_list ibpl;
374	DECLARE_PCI_UNMAP_ADDR(mapping);
375	dma_addr_t dma_addr;
376	struct c4iw_dev *dev;
377	int size;
378};
379
380static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
381					struct ib_fast_reg_page_list *ibpl)
382{
383	return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
384}
385
386struct c4iw_cq {
387	struct ib_cq ibcq;
388	struct c4iw_dev *rhp;
389	struct t4_cq cq;
390	spinlock_t lock;
391	spinlock_t comp_handler_lock;
392	atomic_t refcnt;
393	wait_queue_head_t wait;
394};
395
396static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
397{
398	return container_of(ibcq, struct c4iw_cq, ibcq);
399}
400
401struct c4iw_mpa_attributes {
402	u8 initiator;
403	u8 recv_marker_enabled;
404	u8 xmit_marker_enabled;
405	u8 crc_enabled;
406	u8 enhanced_rdma_conn;
407	u8 version;
408	u8 p2p_type;
409};
410
411struct c4iw_qp_attributes {
412	u32 scq;
413	u32 rcq;
414	u32 sq_num_entries;
415	u32 rq_num_entries;
416	u32 sq_max_sges;
417	u32 sq_max_sges_rdma_write;
418	u32 rq_max_sges;
419	u32 state;
420	u8 enable_rdma_read;
421	u8 enable_rdma_write;
422	u8 enable_bind;
423	u8 enable_mmid0_fastreg;
424	u32 max_ord;
425	u32 max_ird;
426	u32 pd;
427	u32 next_state;
428	char terminate_buffer[52];
429	u32 terminate_msg_len;
430	u8 is_terminate_local;
431	struct c4iw_mpa_attributes mpa_attr;
432	struct c4iw_ep *llp_stream_handle;
433	u8 layer_etype;
434	u8 ecode;
435	u16 sq_db_inc;
436	u16 rq_db_inc;
437};
438
439struct c4iw_qp {
440	struct ib_qp ibqp;
441	struct c4iw_dev *rhp;
442	struct c4iw_ep *ep;
443	struct c4iw_qp_attributes attr;
444	struct t4_wq wq;
445	spinlock_t lock;
446	struct mutex mutex;
447	atomic_t refcnt;
448	wait_queue_head_t wait;
449	struct timer_list timer;
450	int sq_sig_all;
451};
452
453static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
454{
455	return container_of(ibqp, struct c4iw_qp, ibqp);
456}
457
458struct c4iw_ucontext {
459	struct ib_ucontext ibucontext;
460	struct c4iw_dev_ucontext uctx;
461	u32 key;
462	spinlock_t mmap_lock;
463	struct list_head mmaps;
464};
465
466static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
467{
468	return container_of(c, struct c4iw_ucontext, ibucontext);
469}
470
471struct c4iw_mm_entry {
472	struct list_head entry;
473	u64 addr;
474	u32 key;
475	unsigned len;
476};
477
478static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
479						u32 key, unsigned len)
480{
481	struct list_head *pos, *nxt;
482	struct c4iw_mm_entry *mm;
483
484	spin_lock(&ucontext->mmap_lock);
485	list_for_each_safe(pos, nxt, &ucontext->mmaps) {
486
487		mm = list_entry(pos, struct c4iw_mm_entry, entry);
488		if (mm->key == key && mm->len == len) {
489			list_del_init(&mm->entry);
490			spin_unlock(&ucontext->mmap_lock);
491			CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
492			     __func__, key, (unsigned long long) mm->addr,
493			     mm->len);
494			return mm;
495		}
496	}
497	spin_unlock(&ucontext->mmap_lock);
498	return NULL;
499}
500
501static inline void insert_mmap(struct c4iw_ucontext *ucontext,
502			       struct c4iw_mm_entry *mm)
503{
504	spin_lock(&ucontext->mmap_lock);
505	CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
506	    (unsigned long long) mm->addr, mm->len);
507	list_add_tail(&mm->entry, &ucontext->mmaps);
508	spin_unlock(&ucontext->mmap_lock);
509}
510
511enum c4iw_qp_attr_mask {
512	C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
513	C4IW_QP_ATTR_SQ_DB = 1<<1,
514	C4IW_QP_ATTR_RQ_DB = 1<<2,
515	C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
516	C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
517	C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
518	C4IW_QP_ATTR_MAX_ORD = 1 << 11,
519	C4IW_QP_ATTR_MAX_IRD = 1 << 12,
520	C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
521	C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
522	C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
523	C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
524	C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
525				     C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
526				     C4IW_QP_ATTR_MAX_ORD |
527				     C4IW_QP_ATTR_MAX_IRD |
528				     C4IW_QP_ATTR_LLP_STREAM_HANDLE |
529				     C4IW_QP_ATTR_STREAM_MSG_BUFFER |
530				     C4IW_QP_ATTR_MPA_ATTR |
531				     C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
532};
533
534int c4iw_modify_qp(struct c4iw_dev *rhp,
535				struct c4iw_qp *qhp,
536				enum c4iw_qp_attr_mask mask,
537				struct c4iw_qp_attributes *attrs,
538				int internal);
539
540enum c4iw_qp_state {
541	C4IW_QP_STATE_IDLE,
542	C4IW_QP_STATE_RTS,
543	C4IW_QP_STATE_ERROR,
544	C4IW_QP_STATE_TERMINATE,
545	C4IW_QP_STATE_CLOSING,
546	C4IW_QP_STATE_TOT
547};
548
549/*
550 * IW_CXGBE event bits.
551 * These bits are used for handling all events for a particular 'ep' serially.
552 */
553#define	C4IW_EVENT_SOCKET	0x0001
554#define	C4IW_EVENT_TIMEOUT	0x0002
555#define	C4IW_EVENT_TERM		0x0004
556
557static inline int c4iw_convert_state(enum ib_qp_state ib_state)
558{
559	switch (ib_state) {
560	case IB_QPS_RESET:
561	case IB_QPS_INIT:
562		return C4IW_QP_STATE_IDLE;
563	case IB_QPS_RTS:
564		return C4IW_QP_STATE_RTS;
565	case IB_QPS_SQD:
566		return C4IW_QP_STATE_CLOSING;
567	case IB_QPS_SQE:
568		return C4IW_QP_STATE_TERMINATE;
569	case IB_QPS_ERR:
570		return C4IW_QP_STATE_ERROR;
571	default:
572		return -1;
573	}
574}
575
576static inline int to_ib_qp_state(int c4iw_qp_state)
577{
578	switch (c4iw_qp_state) {
579	case C4IW_QP_STATE_IDLE:
580		return IB_QPS_INIT;
581	case C4IW_QP_STATE_RTS:
582		return IB_QPS_RTS;
583	case C4IW_QP_STATE_CLOSING:
584		return IB_QPS_SQD;
585	case C4IW_QP_STATE_TERMINATE:
586		return IB_QPS_SQE;
587	case C4IW_QP_STATE_ERROR:
588		return IB_QPS_ERR;
589	}
590	return IB_QPS_ERR;
591}
592
593#define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
594
595static inline u32 c4iw_ib_to_tpt_access(int a)
596{
597	return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
598	       (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
599	       (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
600	       FW_RI_MEM_ACCESS_LOCAL_READ;
601}
602
603static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
604{
605	return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
606	       (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
607}
608
609enum c4iw_mmid_state {
610	C4IW_STAG_STATE_VALID,
611	C4IW_STAG_STATE_INVALID
612};
613
614#define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
615
616#define MPA_KEY_REQ "MPA ID Req Frame"
617#define MPA_KEY_REP "MPA ID Rep Frame"
618
619#define MPA_MAX_PRIVATE_DATA	256
620#define MPA_ENHANCED_RDMA_CONN	0x10
621#define MPA_REJECT		0x20
622#define MPA_CRC			0x40
623#define MPA_MARKERS		0x80
624#define MPA_FLAGS_MASK		0xE0
625
626#define MPA_V2_PEER2PEER_MODEL          0x8000
627#define MPA_V2_ZERO_LEN_FPDU_RTR        0x4000
628#define MPA_V2_RDMA_WRITE_RTR           0x8000
629#define MPA_V2_RDMA_READ_RTR            0x4000
630#define MPA_V2_IRD_ORD_MASK             0x3FFF
631
632#define c4iw_put_ep(ep) { \
633	CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
634	     __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
635	WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \
636        kref_put(&((ep)->kref), _c4iw_free_ep); \
637}
638
639#define c4iw_get_ep(ep) { \
640	CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
641	      __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
642        kref_get(&((ep)->kref));  \
643}
644
645void _c4iw_free_ep(struct kref *kref);
646
647struct mpa_message {
648	u8 key[16];
649	u8 flags;
650	u8 revision;
651	__be16 private_data_size;
652	u8 private_data[0];
653};
654
655struct mpa_v2_conn_params {
656	__be16 ird;
657	__be16 ord;
658};
659
660struct terminate_message {
661	u8 layer_etype;
662	u8 ecode;
663	__be16 hdrct_rsvd;
664	u8 len_hdrs[0];
665};
666
667#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
668
669enum c4iw_layers_types {
670	LAYER_RDMAP		= 0x00,
671	LAYER_DDP		= 0x10,
672	LAYER_MPA		= 0x20,
673	RDMAP_LOCAL_CATA	= 0x00,
674	RDMAP_REMOTE_PROT	= 0x01,
675	RDMAP_REMOTE_OP		= 0x02,
676	DDP_LOCAL_CATA		= 0x00,
677	DDP_TAGGED_ERR		= 0x01,
678	DDP_UNTAGGED_ERR	= 0x02,
679	DDP_LLP			= 0x03
680};
681
682enum c4iw_rdma_ecodes {
683	RDMAP_INV_STAG		= 0x00,
684	RDMAP_BASE_BOUNDS	= 0x01,
685	RDMAP_ACC_VIOL		= 0x02,
686	RDMAP_STAG_NOT_ASSOC	= 0x03,
687	RDMAP_TO_WRAP		= 0x04,
688	RDMAP_INV_VERS		= 0x05,
689	RDMAP_INV_OPCODE	= 0x06,
690	RDMAP_STREAM_CATA	= 0x07,
691	RDMAP_GLOBAL_CATA	= 0x08,
692	RDMAP_CANT_INV_STAG	= 0x09,
693	RDMAP_UNSPECIFIED	= 0xff
694};
695
696enum c4iw_ddp_ecodes {
697	DDPT_INV_STAG		= 0x00,
698	DDPT_BASE_BOUNDS	= 0x01,
699	DDPT_STAG_NOT_ASSOC	= 0x02,
700	DDPT_TO_WRAP		= 0x03,
701	DDPT_INV_VERS		= 0x04,
702	DDPU_INV_QN		= 0x01,
703	DDPU_INV_MSN_NOBUF	= 0x02,
704	DDPU_INV_MSN_RANGE	= 0x03,
705	DDPU_INV_MO		= 0x04,
706	DDPU_MSG_TOOBIG		= 0x05,
707	DDPU_INV_VERS		= 0x06
708};
709
710enum c4iw_mpa_ecodes {
711	MPA_CRC_ERR		= 0x02,
712	MPA_MARKER_ERR		= 0x03,
713	MPA_LOCAL_CATA          = 0x05,
714	MPA_INSUFF_IRD          = 0x06,
715	MPA_NOMATCH_RTR         = 0x07,
716};
717
718enum c4iw_ep_state {
719	IDLE = 0,
720	LISTEN,
721	CONNECTING,
722	MPA_REQ_WAIT,
723	MPA_REQ_SENT,
724	MPA_REQ_RCVD,
725	MPA_REP_SENT,
726	FPDU_MODE,
727	ABORTING,
728	CLOSING,
729	MORIBUND,
730	DEAD,
731};
732
733enum c4iw_ep_flags {
734	PEER_ABORT_IN_PROGRESS	= 0,
735	ABORT_REQ_IN_PROGRESS	= 1,
736	RELEASE_RESOURCES	= 2,
737	CLOSE_SENT		= 3,
738	TIMEOUT                 = 4,
739	QP_REFERENCED		= 5
740};
741
742enum c4iw_ep_history {
743        ACT_OPEN_REQ            = 0,
744        ACT_OFLD_CONN           = 1,
745        ACT_OPEN_RPL            = 2,
746        ACT_ESTAB               = 3,
747        PASS_ACCEPT_REQ         = 4,
748        PASS_ESTAB              = 5,
749        ABORT_UPCALL            = 6,
750        ESTAB_UPCALL            = 7,
751        CLOSE_UPCALL            = 8,
752        ULP_ACCEPT              = 9,
753        ULP_REJECT              = 10,
754        TIMEDOUT                = 11,
755        PEER_ABORT              = 12,
756        PEER_CLOSE              = 13,
757        CONNREQ_UPCALL          = 14,
758        ABORT_CONN              = 15,
759        DISCONN_UPCALL          = 16,
760        EP_DISC_CLOSE           = 17,
761        EP_DISC_ABORT           = 18,
762        CONN_RPL_UPCALL         = 19,
763        ACT_RETRY_NOMEM         = 20,
764        ACT_RETRY_INUSE         = 21,
765        CLOSE_CON_RPL           = 22,
766        EP_DISC_FAIL            = 24,
767        QP_REFED                = 25,
768        QP_DEREFED              = 26,
769        CM_ID_REFED             = 27,
770        CM_ID_DEREFED           = 28
771};
772
773struct c4iw_ep_common {
774	TAILQ_ENTRY(c4iw_ep_common) entry;	/* Work queue attachment */
775	struct iw_cm_id *cm_id;
776	struct c4iw_qp *qp;
777	struct c4iw_dev *dev;
778	enum c4iw_ep_state state;
779	struct kref kref;
780	struct mutex mutex;
781	struct sockaddr_in local_addr;
782	struct sockaddr_in remote_addr;
783	struct c4iw_wr_wait wr_wait;
784	unsigned long flags;
785	unsigned long history;
786        int rpl_err;
787        int rpl_done;
788        struct thread *thread;
789        struct socket *so;
790	int ep_events;
791};
792
793struct c4iw_listen_ep {
794	struct c4iw_ep_common com;
795	unsigned int stid;
796	int backlog;
797};
798
799struct c4iw_ep {
800	struct c4iw_ep_common com;
801	struct c4iw_ep *parent_ep;
802	struct timer_list timer;
803	unsigned int atid;
804	u32 hwtid;
805	u32 snd_seq;
806	u32 rcv_seq;
807	struct l2t_entry *l2t;
808	struct dst_entry *dst;
809	struct c4iw_mpa_attributes mpa_attr;
810	u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
811	unsigned int mpa_pkt_len;
812	u32 ird;
813	u32 ord;
814	u32 smac_idx;
815	u32 tx_chan;
816	u32 mtu;
817	u16 mss;
818	u16 emss;
819	u16 plen;
820	u16 rss_qid;
821	u16 txq_idx;
822	u16 ctrlq_idx;
823	u8 tos;
824	u8 retry_with_mpa_v1;
825	u8 tried_with_mpa_v1;
826};
827
828static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
829{
830	return cm_id->provider_data;
831}
832
833static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
834{
835	return cm_id->provider_data;
836}
837
838static inline int compute_wscale(int win)
839{
840	int wscale = 0;
841
842	while (wscale < 14 && (65535<<wscale) < win)
843		wscale++;
844	return wscale;
845}
846
847u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
848void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
849int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
850			u32 reserved, u32 flags);
851void c4iw_id_table_free(struct c4iw_id_table *alloc);
852
853typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
854
855int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
856		     struct l2t_entry *l2t);
857u32 c4iw_get_resource(struct c4iw_id_table *id_table);
858void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
859int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
860int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
861int c4iw_pblpool_create(struct c4iw_rdev *rdev);
862int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
863void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
864void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
865void c4iw_destroy_resource(struct c4iw_resource *rscp);
866int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
867int c4iw_register_device(struct c4iw_dev *dev);
868void c4iw_unregister_device(struct c4iw_dev *dev);
869int __init c4iw_cm_init(void);
870void __exit c4iw_cm_term(void);
871void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
872			       struct c4iw_dev_ucontext *uctx);
873void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
874			    struct c4iw_dev_ucontext *uctx);
875int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
876int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
877		      struct ib_send_wr **bad_wr);
878int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
879		      struct ib_recv_wr **bad_wr);
880int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
881		 struct ib_mw_bind *mw_bind);
882int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
883int c4iw_create_listen_ep(struct iw_cm_id *cm_id, int backlog);
884void c4iw_destroy_listen_ep(struct iw_cm_id *cm_id);
885int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
886int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
887void c4iw_qp_add_ref(struct ib_qp *qp);
888void c4iw_qp_rem_ref(struct ib_qp *qp);
889void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
890struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
891					struct ib_device *device,
892					int page_list_len);
893struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
894int c4iw_dealloc_mw(struct ib_mw *mw);
895struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
896struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
897    virt, int acc, struct ib_udata *udata, int mr_id);
898struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
899struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
900					struct ib_phys_buf *buffer_list,
901					int num_phys_buf,
902					int acc,
903					u64 *iova_start);
904int c4iw_reregister_phys_mem(struct ib_mr *mr,
905				     int mr_rereg_mask,
906				     struct ib_pd *pd,
907				     struct ib_phys_buf *buffer_list,
908				     int num_phys_buf,
909				     int acc, u64 *iova_start);
910int c4iw_dereg_mr(struct ib_mr *ib_mr);
911int c4iw_destroy_cq(struct ib_cq *ib_cq);
912struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, struct ib_cq_init_attr *attr,
913					struct ib_ucontext *ib_context,
914					struct ib_udata *udata);
915int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
916int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
917int c4iw_destroy_qp(struct ib_qp *ib_qp);
918struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
919			     struct ib_qp_init_attr *attrs,
920			     struct ib_udata *udata);
921int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
922				 int attr_mask, struct ib_udata *udata);
923int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
924		     int attr_mask, struct ib_qp_init_attr *init_attr);
925struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
926u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
927void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
928u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
929void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
930int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
931void c4iw_flush_hw_cq(struct c4iw_cq *chp);
932void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
933int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
934int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
935int c4iw_flush_sq(struct c4iw_qp *qhp);
936int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
937u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
938int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
939u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
940void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
941		struct c4iw_dev_ucontext *uctx);
942u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
943void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
944		struct c4iw_dev_ucontext *uctx);
945void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
946void process_newconn(struct iw_cm_id *parent_cm_id,
947		struct socket *child_so);
948
949extern struct cxgb4_client t4c_client;
950extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
951extern int c4iw_max_read_depth;
952
953#if defined(__i386__) || defined(__amd64__)
954#define L1_CACHE_BYTES 128
955#else
956#define L1_CACHE_BYTES 32
957#endif
958
959void your_reg_device(struct c4iw_dev *dev);
960
961#define SGE_CTRLQ_NUM	0
962
963#endif
964