a_api.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012 Bjoern A. Zeeb
5 * All rights reserved.
6 *
7 * This software was developed by SRI International and the University of
8 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249)
9 * ("MRC2"), as part of the DARPA MRC research programme.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD: stable/11/sys/dev/altera/atse/a_api.h 330897 2018-03-14 03:19:51Z eadler $
33 */
34/*
35 * Altera, Embedded Peripherals IP, User Guide, v. 11.0, June 2011.
36 * UG-01085-11.0.
37 */
38
39#ifndef _A_API_H
40#define _A_API_H
41
42/* Table 16-1. Memory Map. */
43#define	A_ONCHIP_FIFO_MEM_CORE_DATA		0x00
44#define	A_ONCHIP_FIFO_MEM_CORE_METADATA		0x04
45
46#define	A_ONCHIP_FIFO_MEM_CORE_SOP		(1<<0)
47#define	A_ONCHIP_FIFO_MEM_CORE_EOP		(1<<1)
48#define	A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK	0x000000f7
49#define	A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT	2
50	/* Reserved				(1<<7)	   */
51#define	A_ONCHIP_FIFO_MEM_CORE_CHANNEL_MASK	0x0000ff00
52#define	A_ONCHIP_FIFO_MEM_CORE_CHANNEL_SHIFT	8
53#define	A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK	0x00ff0000
54#define	A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT	16
55	/* Reserved				0xff000000 */
56
57/* Table 16-3. FIFO Status Register Memory Map. */
58#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_FILL_LEVEL	0x00
59#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_I_STATUS	0x04
60#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT		0x08
61#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE	0x0c
62#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_ALMOSTFULL	0x10
63#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_ALMOSTEMPTY	0x14
64
65/* Table 16-5. Status Bit Field Descriptions. */
66#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_FULL		(1<<0)
67#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_EMPTY		(1<<1)
68#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_ALMOSTFULL	(1<<2)
69#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_ALMOSTEMPTY	(1<<3)
70#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_OVERFLOW		(1<<4)
71#define	A_ONCHIP_FIFO_MEM_CORE_STATUS_UNDERFLOW		(1<<5)
72
73/* Table 16-6. Event Bit Field Descriptions. */
74/* XXX Datasheet has incorrect bit fields. Validate. */
75#define	A_ONCHIP_FIFO_MEM_CORE_EVENT_FULL		(1<<0)
76#define	A_ONCHIP_FIFO_MEM_CORE_EVENT_EMPTY		(1<<1)
77#define	A_ONCHIP_FIFO_MEM_CORE_EVENT_ALMOSTFULL		(1<<2)
78#define	A_ONCHIP_FIFO_MEM_CORE_EVENT_ALMOSTEMPTY	(1<<3)
79#define	A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW		(1<<4)
80#define	A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW		(1<<5)
81
82/* Table 16-7. InterruptEnable Bit Field Descriptions. */
83/* XXX Datasheet has incorrect bit fields. Validate. */
84#define	A_ONCHIP_FIFO_MEM_CORE_INTR_FULL		(1<<0)
85#define	A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY		(1<<1)
86#define	A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTFULL		(1<<2)
87#define	A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTEMPTY		(1<<3)
88#define	A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW		(1<<4)
89#define	A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW		(1<<5)
90#define	A_ONCHIP_FIFO_MEM_CORE_INTR_ALL			\
91	    (A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY|		\
92	    A_ONCHIP_FIFO_MEM_CORE_INTR_FULL|		\
93	    A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTEMPTY|	\
94	    A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTFULL|	\
95	    A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW|	\
96	    A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW)
97
98#endif /* _A_API_H */
99
100/* end */
101