maltareg.h revision 330897
1/* $NetBSD: maltareg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */ 2 3/*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright 2002 Wasabi Systems, Inc. 7 * All rights reserved. 8 * 9 * Written by Simon Burge for Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed for the NetBSD Project by 22 * Wasabi Systems, Inc. 23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 * or promote products derived from this software without specific prior 25 * written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 * 39 * $FreeBSD: stable/11/sys/mips/malta/maltareg.h 330897 2018-03-14 03:19:51Z eadler $ 40 */ 41 42/* 43 Memory Map 44 45 0000.0000 * 128MB Typically SDRAM (on Core Board) 46 0800.0000 * 256MB Typically PCI 47 1800.0000 * 62MB Typically PCI 48 1be0.0000 * 2MB Typically System controller's internal registers 49 1c00.0000 * 32MB Typically not used 50 1e00.0000 4MB Monitor Flash 51 1e40.0000 12MB reserved 52 1f00.0000 12MB Switches 53 LEDs 54 ASCII display 55 Soft reset 56 FPGA revision number 57 CBUS UART (tty2) 58 General Purpose I/O 59 I2C controller 60 1f10.0000 * 11MB Typically System Controller specific 61 1fc0.0000 4MB Maps to Monitor Flash 62 1fd0.0000 * 3MB Typically System Controller specific 63 64 * depends on implementation of the Core Board and of software 65 */ 66 67/* 68 CPU interrupts 69 70 NMI South Bridge or NMI button 71 0 South Bridge INTR 72 1 South Bridge SMI 73 2 CBUS UART (tty2) 74 3 COREHI (Core Card) 75 4 CORELO (Core Card) 76 5 Not used, driven inactive (typically CPU internal timer interrupt 77 78 IRQ mapping (as used by YAMON) 79 80 0 Timer South Bridge 81 1 Keyboard SuperIO 82 2 Reserved by South Bridge (for cascading) 83 3 UART (tty1) SuperIO 84 4 UART (tty0) SuperIO 85 5 Not used 86 6 Floppy Disk SuperIO 87 7 Parallel Port SuperIO 88 8 Real Time Clock South Bridge 89 9 I2C bus South Bridge 90 10 PCI A,B,eth PCI slot 1..4, Ethernet 91 11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge) 92 PCI D,USB 93 12 Mouse SuperIO 94 13 Reserved by South Bridge 95 14 Primary IDE Primary IDE slot 96 15 Secondary IDE Secondary IDE slot/Compact flash connector 97 */ 98 99#define MALTA_SYSTEMRAM_BASE 0x00000000ul /* System RAM: */ 100#define MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */ 101 102#define MALTA_PCIMEM1_BASE 0x08000000ul /* PCI 1 memory: */ 103#define MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */ 104 105#define MALTA_PCIMEM2_BASE 0x10000000ul /* PCI 2 memory: */ 106#define MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */ 107 108#define MALTA_PCIMEM3_BASE 0x18000000ul /* PCI 3 memory */ 109#define MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */ 110 111#define MALTA_CORECTRL_BASE 0x1be00000ul /* Core control: */ 112#define MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */ 113 114#define MALTA_RESERVED_BASE1 0x1c000000ul /* Reserved: */ 115#define MALTA_RESERVED_SIZE1 0x02000000 /* 32 MByte */ 116 117#define MALTA_MONITORFLASH_BASE 0x1e000000ul /* Monitor Flash: */ 118#define MALTA_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */ 119#define MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 120 121#define MALTA_FILEFLASH_BASE 0x1e3e0000ul /* File Flash (for monitor): */ 122#define MALTA_FILEFLASH_SIZE 0x00020000 /* 128 KByte */ 123 124#define MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 125 126#define MALTA_RESERVED_BASE2 0x1e400000ul /* Reserved: */ 127#define MALTA_RESERVED_SIZE2 0x00c00000 /* 12 MByte */ 128 129#define MALTA_FPGA_BASE 0x1f000000ul /* FPGA: */ 130#define MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */ 131 132#define MALTA_NMISTATUS (MALTA_FPGA_BASE + 0x24) 133#define MALTA_NMI_SB 0x2 /* Pending NMI from the South Bridge */ 134#define MALTA_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */ 135 136#define MALTA_NMIACK (MALTA_FPGA_BASE + 0x104) 137#define MALTA_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */ 138 139#define MALTA_SWITCH (MALTA_FPGA_BASE + 0x200) 140#define MALTA_SWITCH_MASK 0xff /* settings of DIP switch S2 */ 141 142#define MALTA_STATUS (MALTA_FPGA_BASE + 0x208) 143#define MALTA_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */ 144#define MALTA_S54 0x08 /* switch S5-4 - set YAMON factory default mode */ 145#define MALTA_S53 0x04 /* switch S5-3 */ 146#define MALTA_BIGEND 0x02 /* switch S5-2 - big endian mode */ 147 148#define MALTA_JMPRS (MALTA_FPGA_BASE + 0x210) 149#define MALTA_JMPRS_PCICLK 0x1c /* PCI clock frequency */ 150#define MALTA_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */ 151 152#define MALTA_LEDBAR (MALTA_FPGA_BASE + 0x408) 153#define MALTA_ASCIIWORD (MALTA_FPGA_BASE + 0x410) 154#define MALTA_ASCII_BASE (MALTA_FPGA_BASE + 0x418) 155#define MALTA_ASCIIPOS0 0x00 156#define MALTA_ASCIIPOS1 0x08 157#define MALTA_ASCIIPOS2 0x10 158#define MALTA_ASCIIPOS3 0x18 159#define MALTA_ASCIIPOS4 0x20 160#define MALTA_ASCIIPOS5 0x28 161#define MALTA_ASCIIPOS6 0x30 162#define MALTA_ASCIIPOS7 0x38 163 164#define MALTA_SOFTRES (MALTA_FPGA_BASE + 0x500) 165#define MALTA_GORESET 0x42 /* write this to MALTA_SOFTRES for board reset */ 166 167/* 168 * BRKRES is the number of milliseconds before a "break" on tty will 169 * trigger a reset. A value of 0 will disable the reset. 170 */ 171#define MALTA_BRKRES (MALTA_FPGA_BASE + 0x508) 172#define MALTA_BRKRES_MASK 0xff 173 174#define MALTA_CBUSUART (MALTA_FPGA_BASE + 0x900) 175/* 16C550C UART, 8 bit registers on 8 byte boundaries */ 176/* RXTX 0x00 */ 177/* INTEN 0x08 */ 178/* IIFIFO 0x10 */ 179/* LCTRL 0x18 */ 180/* MCTRL 0x20 */ 181/* LSTAT 0x28 */ 182/* MSTAT 0x30 */ 183/* SCRATCH 0x38 */ 184#define MALTA_CBUSUART_INTR 2 185 186#define MALTA_GPIO_BASE (MALTA_FPGA_BASE + 0xa00) 187#define MALTA_GPOUT 0x0 188#define MALTA_GPINP 0x8 189 190#define MALTA_I2C_BASE (MALTA_FPGA_BASE + 0xb00) 191#define MALTA_I2CINP 0x00 192#define MALTA_I2COE 0x08 193#define MALTA_I2COUT 0x10 194#define MALTA_I2CSEL 0x18 195 196#define MALTA_BOOTROM_BASE 0x1fc00000ul /* Boot ROM: */ 197#define MALTA_BOOTROM_SIZE 0x00400000 /* 4 MByte */ 198 199#define MALTA_REVISION 0x1fc00010ul 200#define MALTA_REV_FPGRV 0xff0000 /* CBUS FPGA revision */ 201#define MALTA_REV_CORID 0x00fc00 /* Core Board ID */ 202#define MALTA_REV_CORRV 0x000300 /* Core Board Revision */ 203#define MALTA_REV_PROID 0x0000f0 /* Product ID */ 204#define MALTA_REV_PRORV 0x00000f /* Product Revision */ 205 206/* PCI definitions */ 207#define MALTA_SOUTHBRIDGE_INTR 0 208 209#define MALTA_PCI0_IO_BASE MALTA_PCIMEM3_BASE 210#define MALTA_PCI0_ADDR( addr ) (MALTA_PCI0_IO_BASE + (addr)) 211 212#define MALTA_RTCADR 0x70 // MALTA_PCI_IO_ADDR8(0x70) 213#define MALTA_RTCDAT 0x71 // MALTA_PCI_IO_ADDR8(0x71) 214 215#define MALTA_SMSC_COM1_ADR 0x3f8 216#define MALTA_SMSC_COM2_ADR 0x2f8 217#define MALTA_UART0ADR MALTA_PCI0_ADDR(MALTA_SMSC_COM1_ADR) 218#define MALTA_UART1ADR MALTA_SMSC_COM2_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_COM2_ADR) 219 220#define MALTA_SMSC_1284_ADR 0x378 221#define MALTA_1284ADR MALTA_SMSC_1284_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_1284_ADR) 222 223#define MALTA_SMSC_FDD_ADR 0x3f0 224#define MALTA_FDDADR MALTA_SMSC_FDD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_FDD_ADR) 225 226#define MALTA_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */ 227#define MALTA_KYBDADR MALTA_SMSC_KYBD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_KYBD_ADR) 228#define MALTA_SMSC_MOUSE_ADR MALTA_SMSC_KYBD_ADR 229#define MALTA_MOUSEADR MALTA_KYBDADR 230 231 232#define MALTA_DMA_PCI_PCIBASE 0x00000000UL 233#define MALTA_DMA_PCI_PHYSBASE 0x00000000UL 234#define MALTA_DMA_PCI_SIZE (256 * 1024 * 1024) 235 236#define MALTA_DMA_ISA_PCIBASE 0x00800000UL 237#define MALTA_DMA_ISA_PHYSBASE 0x00000000UL 238#define MALTA_DMA_ISA_SIZE (8 * 1024 * 1024) 239 240#ifndef _LOCORE 241void led_bar(uint8_t); 242void led_display_word(uint32_t); 243void led_display_str(const char *); 244void led_display_char(int, uint8_t); 245#endif 246