ti_gpio.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/** 31 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 32 * here uses 0-5. 33 */ 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD: stable/11/sys/arm/ti/ti_gpio.c 330897 2018-03-14 03:19:51Z eadler $"); 37 38#include "opt_platform.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43 44#include <sys/kernel.h> 45#include <sys/module.h> 46#include <sys/proc.h> 47#include <sys/rman.h> 48#include <sys/lock.h> 49#include <sys/mutex.h> 50#include <sys/gpio.h> 51#include <sys/interrupt.h> 52 53#include <machine/bus.h> 54#include <machine/intr.h> 55#include <machine/resource.h> 56 57#include <arm/ti/ti_cpuid.h> 58#include <arm/ti/ti_gpio.h> 59#include <arm/ti/ti_scm.h> 60#include <arm/ti/ti_prcm.h> 61#include <arm/ti/ti_hwmods.h> 62 63#include <dev/fdt/fdt_common.h> 64#include <dev/gpio/gpiobusvar.h> 65#include <dev/ofw/openfirm.h> 66#include <dev/ofw/ofw_bus.h> 67#include <dev/ofw/ofw_bus_subr.h> 68 69#include "gpio_if.h" 70#include "ti_gpio_if.h" 71#ifdef INTRNG 72#include "pic_if.h" 73#endif 74 75#if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 76#error "Unknown SoC" 77#endif 78 79/* Register definitions */ 80#define TI_GPIO_REVISION 0x0000 81#define TI_GPIO_SYSCONFIG 0x0010 82#define TI_GPIO_IRQSTATUS_RAW_0 0x0024 83#define TI_GPIO_IRQSTATUS_RAW_1 0x0028 84#define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */ 85#define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */ 86#define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */ 87#define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */ 88#define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */ 89#define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */ 90#define TI_GPIO_IRQWAKEN_0 0x0044 91#define TI_GPIO_IRQWAKEN_1 0x0048 92#define TI_GPIO_SYSSTATUS 0x0114 93#define TI_GPIO_IRQSTATUS1 0x0118 94#define TI_GPIO_IRQENABLE1 0x011C 95#define TI_GPIO_WAKEUPENABLE 0x0120 96#define TI_GPIO_IRQSTATUS2 0x0128 97#define TI_GPIO_IRQENABLE2 0x012C 98#define TI_GPIO_CTRL 0x0130 99#define TI_GPIO_OE 0x0134 100#define TI_GPIO_DATAIN 0x0138 101#define TI_GPIO_DATAOUT 0x013C 102#define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */ 103#define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */ 104#define TI_GPIO_RISINGDETECT 0x0148 /* RW register */ 105#define TI_GPIO_FALLINGDETECT 0x014C /* RW register */ 106#define TI_GPIO_DEBOUNCENABLE 0x0150 107#define TI_GPIO_DEBOUNCINGTIME 0x0154 108#define TI_GPIO_CLEARWKUPENA 0x0180 109#define TI_GPIO_SETWKUENA 0x0184 110#define TI_GPIO_CLEARDATAOUT 0x0190 111#define TI_GPIO_SETDATAOUT 0x0194 112 113/* Other SoC Specific definitions */ 114#define OMAP4_FIRST_GPIO_BANK 1 115#define OMAP4_INTR_PER_BANK 1 116#define OMAP4_GPIO_REV 0x50600801 117#define AM335X_FIRST_GPIO_BANK 0 118#define AM335X_INTR_PER_BANK 2 119#define AM335X_GPIO_REV 0x50600801 120#define PINS_PER_BANK 32 121#define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 122 123static int ti_gpio_intr(void *arg); 124static int ti_gpio_detach(device_t); 125 126#ifdef INTRNG 127static int ti_gpio_pic_attach(struct ti_gpio_softc *sc); 128static int ti_gpio_pic_detach(struct ti_gpio_softc *sc); 129#endif 130 131static u_int 132ti_first_gpio_bank(void) 133{ 134 switch(ti_chip()) { 135#ifdef SOC_OMAP4 136 case CHIP_OMAP_4: 137 return (OMAP4_FIRST_GPIO_BANK); 138#endif 139#ifdef SOC_TI_AM335X 140 case CHIP_AM335X: 141 return (AM335X_FIRST_GPIO_BANK); 142#endif 143 } 144 return (0); 145} 146 147static uint32_t 148ti_gpio_rev(void) 149{ 150 switch(ti_chip()) { 151#ifdef SOC_OMAP4 152 case CHIP_OMAP_4: 153 return (OMAP4_GPIO_REV); 154#endif 155#ifdef SOC_TI_AM335X 156 case CHIP_AM335X: 157 return (AM335X_GPIO_REV); 158#endif 159 } 160 return (0); 161} 162 163/** 164 * Macros for driver mutex locking 165 */ 166#define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 167#define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 168#define TI_GPIO_LOCK_INIT(_sc) \ 169 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 170 "ti_gpio", MTX_SPIN) 171#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 172#define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 173#define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 174 175/** 176 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 177 * @sc: GPIO device context 178 * @bank: The bank to read from 179 * @off: The offset of a register from the GPIO register address range 180 * 181 * 182 * RETURNS: 183 * 32-bit value read from the register. 184 */ 185static inline uint32_t 186ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off) 187{ 188 return (bus_read_4(sc->sc_mem_res, off)); 189} 190 191/** 192 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 193 * @sc: GPIO device context 194 * @bank: The bank to write to 195 * @off: The offset of a register from the GPIO register address range 196 * @val: The value to write into the register 197 * 198 * RETURNS: 199 * nothing 200 */ 201static inline void 202ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off, 203 uint32_t val) 204{ 205 bus_write_4(sc->sc_mem_res, off, val); 206} 207 208static inline void 209ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) 210{ 211 212 /* We clear both set of registers. */ 213 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); 214 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); 215} 216 217static inline void 218ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) 219{ 220 221 /* 222 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 223 * also activate only the first interrupt. 224 */ 225 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); 226} 227 228static inline void 229ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) 230{ 231 232 /* 233 * Acknowledge the interrupt on both registers even if we use only 234 * the first one. 235 */ 236 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); 237 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); 238} 239 240static inline uint32_t 241ti_gpio_intr_status(struct ti_gpio_softc *sc) 242{ 243 uint32_t reg; 244 245 /* Get the status from both registers. */ 246 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0); 247 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1); 248 249 return (reg); 250} 251 252static device_t 253ti_gpio_get_bus(device_t dev) 254{ 255 struct ti_gpio_softc *sc; 256 257 sc = device_get_softc(dev); 258 259 return (sc->sc_busdev); 260} 261 262/** 263 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 264 * @dev: gpio device handle 265 * @maxpin: pointer to a value that upon return will contain the maximum number 266 * of pins in the device. 267 * 268 * 269 * LOCKING: 270 * No locking required, returns static data. 271 * 272 * RETURNS: 273 * Returns 0 on success otherwise an error code 274 */ 275static int 276ti_gpio_pin_max(device_t dev, int *maxpin) 277{ 278 279 *maxpin = PINS_PER_BANK - 1; 280 281 return (0); 282} 283 284static int 285ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 286{ 287 288 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL) 289 return (EINVAL); 290 291 return (0); 292} 293 294/** 295 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin 296 * @dev: gpio device handle 297 * @pin: the number of the pin 298 * @caps: pointer to a value that upon return will contain the capabilities 299 * 300 * Currently all pins have the same capability, notably: 301 * - GPIO_PIN_INPUT 302 * - GPIO_PIN_OUTPUT 303 * - GPIO_PIN_PULLUP 304 * - GPIO_PIN_PULLDOWN 305 * - GPIO_INTR_LEVEL_LOW 306 * - GPIO_INTR_LEVEL_HIGH 307 * - GPIO_INTR_EDGE_RISING 308 * - GPIO_INTR_EDGE_FALLING 309 * - GPIO_INTR_EDGE_BOTH 310 * 311 * LOCKING: 312 * No locking required, returns static data. 313 * 314 * RETURNS: 315 * Returns 0 on success otherwise an error code 316 */ 317static int 318ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 319{ 320 struct ti_gpio_softc *sc; 321 322 sc = device_get_softc(dev); 323 if (ti_gpio_valid_pin(sc, pin) != 0) 324 return (EINVAL); 325 326#ifdef INTRNG 327 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 328 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 329 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 330 GPIO_INTR_EDGE_BOTH); 331#else 332 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 333 GPIO_PIN_PULLDOWN); 334#endif 335 336 return (0); 337} 338 339/** 340 * ti_gpio_pin_getflags - Gets the current flags of a given pin 341 * @dev: gpio device handle 342 * @pin: the number of the pin 343 * @flags: upon return will contain the current flags of the pin 344 * 345 * Reads the current flags of a given pin, here we actually read the H/W 346 * registers to determine the flags, rather than storing the value in the 347 * setflags call. 348 * 349 * LOCKING: 350 * Internally locks the context 351 * 352 * RETURNS: 353 * Returns 0 on success otherwise an error code 354 */ 355static int 356ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 357{ 358 struct ti_gpio_softc *sc; 359 360 sc = device_get_softc(dev); 361 if (ti_gpio_valid_pin(sc, pin) != 0) 362 return (EINVAL); 363 364 /* Get the current pin state */ 365 TI_GPIO_LOCK(sc); 366 TI_GPIO_GET_FLAGS(dev, pin, flags); 367 TI_GPIO_UNLOCK(sc); 368 369 return (0); 370} 371 372/** 373 * ti_gpio_pin_getname - Gets the name of a given pin 374 * @dev: gpio device handle 375 * @pin: the number of the pin 376 * @name: buffer to put the name in 377 * 378 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 379 * of the pin. 380 * 381 * LOCKING: 382 * No locking required, returns static data. 383 * 384 * RETURNS: 385 * Returns 0 on success otherwise an error code 386 */ 387static int 388ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 389{ 390 struct ti_gpio_softc *sc; 391 392 sc = device_get_softc(dev); 393 if (ti_gpio_valid_pin(sc, pin) != 0) 394 return (EINVAL); 395 396 /* Set a very simple name */ 397 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 398 name[GPIOMAXNAME - 1] = '\0'; 399 400 return (0); 401} 402 403/** 404 * ti_gpio_pin_setflags - Sets the flags for a given pin 405 * @dev: gpio device handle 406 * @pin: the number of the pin 407 * @flags: the flags to set 408 * 409 * The flags of the pin correspond to things like input/output mode, pull-ups, 410 * pull-downs, etc. This driver doesn't support all flags, only the following: 411 * - GPIO_PIN_INPUT 412 * - GPIO_PIN_OUTPUT 413 * - GPIO_PIN_PULLUP 414 * - GPIO_PIN_PULLDOWN 415 * 416 * LOCKING: 417 * Internally locks the context 418 * 419 * RETURNS: 420 * Returns 0 on success otherwise an error code 421 */ 422static int 423ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 424{ 425 struct ti_gpio_softc *sc; 426 uint32_t oe; 427 428 sc = device_get_softc(dev); 429 if (ti_gpio_valid_pin(sc, pin) != 0) 430 return (EINVAL); 431 432 /* Set the GPIO mode and state */ 433 TI_GPIO_LOCK(sc); 434 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 435 TI_GPIO_UNLOCK(sc); 436 return (EINVAL); 437 } 438 439 /* If configuring as an output set the "output enable" bit */ 440 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 441 if (flags & GPIO_PIN_INPUT) 442 oe |= TI_GPIO_MASK(pin); 443 else 444 oe &= ~TI_GPIO_MASK(pin); 445 ti_gpio_write_4(sc, TI_GPIO_OE, oe); 446 TI_GPIO_UNLOCK(sc); 447 448 return (0); 449} 450 451/** 452 * ti_gpio_pin_set - Sets the current level on a GPIO pin 453 * @dev: gpio device handle 454 * @pin: the number of the pin 455 * @value: non-zero value will drive the pin high, otherwise the pin is 456 * driven low. 457 * 458 * 459 * LOCKING: 460 * Internally locks the context 461 * 462 * RETURNS: 463 * Returns 0 on success otherwise a error code 464 */ 465static int 466ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 467{ 468 struct ti_gpio_softc *sc; 469 uint32_t reg; 470 471 sc = device_get_softc(dev); 472 if (ti_gpio_valid_pin(sc, pin) != 0) 473 return (EINVAL); 474 475 TI_GPIO_LOCK(sc); 476 if (value == GPIO_PIN_LOW) 477 reg = TI_GPIO_CLEARDATAOUT; 478 else 479 reg = TI_GPIO_SETDATAOUT; 480 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 481 TI_GPIO_UNLOCK(sc); 482 483 return (0); 484} 485 486/** 487 * ti_gpio_pin_get - Gets the current level on a GPIO pin 488 * @dev: gpio device handle 489 * @pin: the number of the pin 490 * @value: pointer to a value that upond return will contain the pin value 491 * 492 * The pin must be configured as an input pin beforehand, otherwise this 493 * function will fail. 494 * 495 * LOCKING: 496 * Internally locks the context 497 * 498 * RETURNS: 499 * Returns 0 on success otherwise a error code 500 */ 501static int 502ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 503{ 504 struct ti_gpio_softc *sc; 505 uint32_t oe, reg, val; 506 507 sc = device_get_softc(dev); 508 if (ti_gpio_valid_pin(sc, pin) != 0) 509 return (EINVAL); 510 511 /* 512 * Return data from output latch when set as output and from the 513 * input register otherwise. 514 */ 515 TI_GPIO_LOCK(sc); 516 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 517 if (oe & TI_GPIO_MASK(pin)) 518 reg = TI_GPIO_DATAIN; 519 else 520 reg = TI_GPIO_DATAOUT; 521 val = ti_gpio_read_4(sc, reg); 522 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 523 TI_GPIO_UNLOCK(sc); 524 525 return (0); 526} 527 528/** 529 * ti_gpio_pin_toggle - Toggles a given GPIO pin 530 * @dev: gpio device handle 531 * @pin: the number of the pin 532 * 533 * 534 * LOCKING: 535 * Internally locks the context 536 * 537 * RETURNS: 538 * Returns 0 on success otherwise a error code 539 */ 540static int 541ti_gpio_pin_toggle(device_t dev, uint32_t pin) 542{ 543 struct ti_gpio_softc *sc; 544 uint32_t reg, val; 545 546 sc = device_get_softc(dev); 547 if (ti_gpio_valid_pin(sc, pin) != 0) 548 return (EINVAL); 549 550 /* Toggle the pin */ 551 TI_GPIO_LOCK(sc); 552 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); 553 if (val & TI_GPIO_MASK(pin)) 554 reg = TI_GPIO_CLEARDATAOUT; 555 else 556 reg = TI_GPIO_SETDATAOUT; 557 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 558 TI_GPIO_UNLOCK(sc); 559 560 return (0); 561} 562 563#ifndef INTRNG 564/** 565 * ti_gpio_intr - ISR for all GPIO modules 566 * @arg: the soft context pointer 567 * 568 * LOCKING: 569 * Internally locks the context 570 * 571 */ 572static int 573ti_gpio_intr(void *arg) 574{ 575 int bank_last, irq; 576 struct intr_event *event; 577 struct ti_gpio_softc *sc; 578 uint32_t reg; 579 580 sc = (struct ti_gpio_softc *)arg; 581 bank_last = -1; 582 reg = 0; /* squelch bogus gcc warning */ 583 reg = ti_gpio_intr_status(sc); 584 for (irq = 0; irq < sc->sc_maxpin; irq++) { 585 if ((reg & TI_GPIO_MASK(irq)) == 0) 586 continue; 587 event = sc->sc_events[irq]; 588 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers)) 589 intr_event_handle(event, NULL); 590 else 591 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq); 592 /* Ack the IRQ Status bit. */ 593 ti_gpio_intr_ack(sc, TI_GPIO_MASK(irq)); 594 } 595 596 return (FILTER_HANDLED); 597} 598#endif 599 600static int 601ti_gpio_bank_init(device_t dev) 602{ 603 int pin; 604 struct ti_gpio_softc *sc; 605 uint32_t flags, reg_oe, reg_set, rev; 606 clk_ident_t clk; 607 608 sc = device_get_softc(dev); 609 610 /* Enable the interface and functional clocks for the module. */ 611 clk = ti_hwmods_get_clock(dev); 612 if (clk == INVALID_CLK_IDENT) { 613 device_printf(dev, "failed to get device id based on ti,hwmods\n"); 614 return (EINVAL); 615 } 616 617 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank(); 618 ti_prcm_clk_enable(clk); 619 620 /* 621 * Read the revision number of the module. TI don't publish the 622 * actual revision numbers, so instead the values have been 623 * determined by experimentation. 624 */ 625 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION); 626 627 /* Check the revision. */ 628 if (rev != ti_gpio_rev()) { 629 device_printf(dev, "Warning: could not determine the revision " 630 "of GPIO module (revision:0x%08x)\n", rev); 631 return (EINVAL); 632 } 633 634 /* Disable interrupts for all pins. */ 635 ti_gpio_intr_clr(sc, 0xffffffff); 636 637 /* Init OE register based on pads configuration. */ 638 reg_oe = 0xffffffff; 639 reg_set = 0; 640 for (pin = 0; pin < PINS_PER_BANK; pin++) { 641 TI_GPIO_GET_FLAGS(dev, pin, &flags); 642 if (flags & GPIO_PIN_OUTPUT) { 643 reg_oe &= ~(1UL << pin); 644 if (flags & GPIO_PIN_PULLUP) 645 reg_set |= (1UL << pin); 646 } 647 } 648 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); 649 if (reg_set) 650 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); 651 652 return (0); 653} 654 655/** 656 * ti_gpio_attach - attach function for the driver 657 * @dev: gpio device handle 658 * 659 * Allocates and sets up the driver context for all GPIO banks. This function 660 * expects the memory ranges and IRQs to already be allocated to the driver. 661 * 662 * LOCKING: 663 * None 664 * 665 * RETURNS: 666 * Always returns 0 667 */ 668static int 669ti_gpio_attach(device_t dev) 670{ 671 struct ti_gpio_softc *sc; 672#ifndef INTRNG 673 unsigned int i; 674#endif 675 int err; 676 677 sc = device_get_softc(dev); 678 sc->sc_dev = dev; 679 TI_GPIO_LOCK_INIT(sc); 680 ti_gpio_pin_max(dev, &sc->sc_maxpin); 681 sc->sc_maxpin++; 682 683 sc->sc_mem_rid = 0; 684 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 685 &sc->sc_mem_rid, RF_ACTIVE); 686 if (!sc->sc_mem_res) { 687 device_printf(dev, "Error: could not allocate mem resources\n"); 688 ti_gpio_detach(dev); 689 return (ENXIO); 690 } 691 692 sc->sc_irq_rid = 0; 693 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 694 &sc->sc_irq_rid, RF_ACTIVE); 695 if (!sc->sc_irq_res) { 696 device_printf(dev, "Error: could not allocate irq resources\n"); 697 ti_gpio_detach(dev); 698 return (ENXIO); 699 } 700 701 /* 702 * Register our interrupt filter for each of the IRQ resources. 703 */ 704 if (bus_setup_intr(dev, sc->sc_irq_res, 705 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 706 &sc->sc_irq_hdl) != 0) { 707 device_printf(dev, 708 "WARNING: unable to register interrupt filter\n"); 709 ti_gpio_detach(dev); 710 return (ENXIO); 711 } 712 713#ifdef INTRNG 714 if (ti_gpio_pic_attach(sc) != 0) { 715 device_printf(dev, "WARNING: unable to attach PIC\n"); 716 ti_gpio_detach(dev); 717 return (ENXIO); 718 } 719#else 720 /* 721 * Initialize the interrupt settings. The default is active-low 722 * interrupts. 723 */ 724 sc->sc_irq_trigger = malloc( 725 sizeof(*sc->sc_irq_trigger) * sc->sc_maxpin, 726 M_DEVBUF, M_WAITOK | M_ZERO); 727 sc->sc_irq_polarity = malloc( 728 sizeof(*sc->sc_irq_polarity) * sc->sc_maxpin, 729 M_DEVBUF, M_WAITOK | M_ZERO); 730 for (i = 0; i < sc->sc_maxpin; i++) { 731 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL; 732 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW; 733 } 734 735 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin, 736 M_DEVBUF, M_WAITOK | M_ZERO); 737 738 sc->sc_mask_args = malloc(sizeof(struct ti_gpio_mask_arg) * sc->sc_maxpin, 739 M_DEVBUF, M_WAITOK | M_ZERO); 740#endif 741 /* We need to go through each block and ensure the clocks are running and 742 * the module is enabled. It might be better to do this only when the 743 * pins are configured which would result in less power used if the GPIO 744 * pins weren't used ... 745 */ 746 if (sc->sc_mem_res != NULL) { 747 /* Initialize the GPIO module. */ 748 err = ti_gpio_bank_init(dev); 749 if (err != 0) { 750 ti_gpio_detach(dev); 751 return (err); 752 } 753 } 754 755 sc->sc_busdev = gpiobus_attach_bus(dev); 756 if (sc->sc_busdev == NULL) { 757 ti_gpio_detach(dev); 758 return (ENXIO); 759 } 760 761 return (0); 762} 763 764/** 765 * ti_gpio_detach - detach function for the driver 766 * @dev: scm device handle 767 * 768 * Allocates and sets up the driver context, this simply entails creating a 769 * bus mappings for the SCM register set. 770 * 771 * LOCKING: 772 * None 773 * 774 * RETURNS: 775 * Always returns 0 776 */ 777static int 778ti_gpio_detach(device_t dev) 779{ 780 struct ti_gpio_softc *sc = device_get_softc(dev); 781 782 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 783 784 /* Disable all interrupts */ 785 if (sc->sc_mem_res != NULL) 786 ti_gpio_intr_clr(sc, 0xffffffff); 787 if (sc->sc_busdev != NULL) 788 gpiobus_detach_bus(dev); 789#ifdef INTRNG 790 if (sc->sc_isrcs != NULL) 791 ti_gpio_pic_detach(sc); 792#else 793 if (sc->sc_events) 794 free(sc->sc_events, M_DEVBUF); 795 if (sc->sc_mask_args) 796 free(sc->sc_mask_args, M_DEVBUF); 797 if (sc->sc_irq_polarity) 798 free(sc->sc_irq_polarity, M_DEVBUF); 799 if (sc->sc_irq_trigger) 800 free(sc->sc_irq_trigger, M_DEVBUF); 801#endif 802 /* Release the memory and IRQ resources. */ 803 if (sc->sc_irq_hdl) { 804 bus_teardown_intr(dev, sc->sc_irq_res, 805 sc->sc_irq_hdl); 806 } 807 if (sc->sc_irq_res) 808 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 809 sc->sc_irq_res); 810 if (sc->sc_mem_res) 811 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 812 sc->sc_mem_res); 813 TI_GPIO_LOCK_DESTROY(sc); 814 815 return (0); 816} 817 818#ifdef INTRNG 819static inline void 820ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask, 821 bool set_bits) 822{ 823 uint32_t value; 824 825 value = ti_gpio_read_4(sc, reg); 826 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask); 827} 828 829static inline void 830ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 831{ 832 833 /* Writing a 0 has no effect. */ 834 ti_gpio_intr_clr(sc, tgi->tgi_mask); 835} 836 837static inline void 838ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 839{ 840 841 /* Writing a 0 has no effect. */ 842 ti_gpio_intr_set(sc, tgi->tgi_mask); 843} 844 845static inline void 846ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 847{ 848 849 /* Writing a 0 has no effect. */ 850 ti_gpio_intr_ack(sc, tgi->tgi_mask); 851} 852 853static inline bool 854ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi) 855{ 856 857 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW || 858 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH); 859} 860 861static int 862ti_gpio_intr(void *arg) 863{ 864 u_int irq; 865 uint32_t reg; 866 struct ti_gpio_softc *sc; 867 struct trapframe *tf; 868 struct ti_gpio_irqsrc *tgi; 869 870 sc = (struct ti_gpio_softc *)arg; 871 tf = curthread->td_intr_frame; 872 873 reg = ti_gpio_intr_status(sc); 874 for (irq = 0; irq < sc->sc_maxpin; irq++) { 875 tgi = &sc->sc_isrcs[irq]; 876 if ((reg & tgi->tgi_mask) == 0) 877 continue; 878 if (!ti_gpio_isrc_is_level(tgi)) 879 ti_gpio_isrc_eoi(sc, tgi); 880 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) { 881 ti_gpio_isrc_mask(sc, tgi); 882 if (ti_gpio_isrc_is_level(tgi)) 883 ti_gpio_isrc_eoi(sc, tgi); 884 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 885 irq); 886 } 887 } 888 return (FILTER_HANDLED); 889} 890 891static int 892ti_gpio_pic_attach(struct ti_gpio_softc *sc) 893{ 894 int error; 895 uint32_t irq; 896 const char *name; 897 898 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF, 899 M_WAITOK | M_ZERO); 900 901 name = device_get_nameunit(sc->sc_dev); 902 for (irq = 0; irq < sc->sc_maxpin; irq++) { 903 sc->sc_isrcs[irq].tgi_irq = irq; 904 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq); 905 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM; 906 907 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc, 908 sc->sc_dev, 0, "%s,%u", name, irq); 909 if (error != 0) 910 return (error); /* XXX deregister ISRCs */ 911 } 912 if (intr_pic_register(sc->sc_dev, 913 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 914 return (ENXIO); 915 916 return (0); 917} 918 919static int 920ti_gpio_pic_detach(struct ti_gpio_softc *sc) 921{ 922 923 /* 924 * There has not been established any procedure yet 925 * how to detach PIC from living system correctly. 926 */ 927 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 928 return (EBUSY); 929} 930 931static void 932ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi, 933 uint32_t mode) 934{ 935 936 TI_GPIO_LOCK(sc); 937 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask, 938 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 939 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask, 940 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 941 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask, 942 mode == GPIO_INTR_LEVEL_HIGH); 943 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask, 944 mode == GPIO_INTR_LEVEL_LOW); 945 tgi->tgi_mode = mode; 946 TI_GPIO_UNLOCK(sc); 947} 948 949static void 950ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 951{ 952 struct ti_gpio_softc *sc = device_get_softc(dev); 953 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 954 955 ti_gpio_isrc_mask(sc, tgi); 956} 957 958static void 959ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 960{ 961 struct ti_gpio_softc *sc = device_get_softc(dev); 962 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 963 964 arm_irq_memory_barrier(tgi->tgi_irq); 965 ti_gpio_isrc_unmask(sc, tgi); 966} 967 968static int 969ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf, 970 u_int *irqp, uint32_t *modep) 971{ 972 uint32_t mode; 973 974 /* 975 * The first cell is the interrupt number. 976 * The second cell is used to specify flags: 977 * bits[3:0] trigger type and level flags: 978 * 1 = low-to-high edge triggered. 979 * 2 = high-to-low edge triggered. 980 * 4 = active high level-sensitive. 981 * 8 = active low level-sensitive. 982 */ 983 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin) 984 return (EINVAL); 985 986 /* Only reasonable modes are supported. */ 987 if (daf->cells[1] == 1) 988 mode = GPIO_INTR_EDGE_RISING; 989 else if (daf->cells[1] == 2) 990 mode = GPIO_INTR_EDGE_FALLING; 991 else if (daf->cells[1] == 3) 992 mode = GPIO_INTR_EDGE_BOTH; 993 else if (daf->cells[1] == 4) 994 mode = GPIO_INTR_LEVEL_HIGH; 995 else if (daf->cells[1] == 8) 996 mode = GPIO_INTR_LEVEL_LOW; 997 else 998 return (EINVAL); 999 1000 *irqp = daf->cells[0]; 1001 if (modep != NULL) 1002 *modep = mode; 1003 return (0); 1004} 1005 1006static int 1007ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag, 1008 u_int *irqp, uint32_t *modep) 1009{ 1010 uint32_t mode; 1011 1012 if (dag->gpio_pin_num >= sc->sc_maxpin) 1013 return (EINVAL); 1014 1015 mode = dag->gpio_intr_mode; 1016 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 1017 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 1018 mode != GPIO_INTR_EDGE_BOTH) 1019 return (EINVAL); 1020 1021 *irqp = dag->gpio_pin_num; 1022 if (modep != NULL) 1023 *modep = mode; 1024 return (0); 1025} 1026 1027static int 1028ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data, 1029 u_int *irqp, uint32_t *modep) 1030{ 1031 1032 switch (data->type) { 1033 case INTR_MAP_DATA_FDT: 1034 return (ti_gpio_pic_map_fdt(sc, 1035 (struct intr_map_data_fdt *)data, irqp, modep)); 1036 case INTR_MAP_DATA_GPIO: 1037 return (ti_gpio_pic_map_gpio(sc, 1038 (struct intr_map_data_gpio *)data, irqp, modep)); 1039 default: 1040 return (ENOTSUP); 1041 } 1042} 1043 1044static int 1045ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1046 struct intr_irqsrc **isrcp) 1047{ 1048 int error; 1049 u_int irq; 1050 struct ti_gpio_softc *sc = device_get_softc(dev); 1051 1052 error = ti_gpio_pic_map(sc, data, &irq, NULL); 1053 if (error == 0) 1054 *isrcp = &sc->sc_isrcs[irq].tgi_isrc; 1055 return (error); 1056} 1057 1058static void 1059ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1060{ 1061 struct ti_gpio_softc *sc = device_get_softc(dev); 1062 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1063 1064 if (ti_gpio_isrc_is_level(tgi)) 1065 ti_gpio_isrc_eoi(sc, tgi); 1066} 1067 1068static void 1069ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1070{ 1071 1072 ti_gpio_pic_enable_intr(dev, isrc); 1073} 1074 1075static void 1076ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1077{ 1078 struct ti_gpio_softc *sc = device_get_softc(dev); 1079 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1080 1081 ti_gpio_isrc_mask(sc, tgi); 1082 if (ti_gpio_isrc_is_level(tgi)) 1083 ti_gpio_isrc_eoi(sc, tgi); 1084} 1085 1086static int 1087ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1088 struct resource *res, struct intr_map_data *data) 1089{ 1090 u_int irq; 1091 uint32_t mode; 1092 struct ti_gpio_softc *sc; 1093 struct ti_gpio_irqsrc *tgi; 1094 1095 if (data == NULL) 1096 return (ENOTSUP); 1097 1098 sc = device_get_softc(dev); 1099 tgi = (struct ti_gpio_irqsrc *)isrc; 1100 1101 /* Get and check config for an interrupt. */ 1102 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq) 1103 return (EINVAL); 1104 1105 /* 1106 * If this is a setup for another handler, 1107 * only check that its configuration match. 1108 */ 1109 if (isrc->isrc_handlers != 0) 1110 return (tgi->tgi_mode == mode ? 0 : EINVAL); 1111 1112 ti_gpio_pic_config_intr(sc, tgi, mode); 1113 return (0); 1114} 1115 1116static int 1117ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1118 struct resource *res, struct intr_map_data *data) 1119{ 1120 struct ti_gpio_softc *sc = device_get_softc(dev); 1121 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1122 1123 if (isrc->isrc_handlers == 0) 1124 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM); 1125 return (0); 1126} 1127 1128#else 1129static uint32_t 1130ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq) 1131{ 1132 1133 if (ti_gpio_valid_pin(sc, irq) != 0) 1134 return (0); 1135 1136 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) { 1137 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1138 return (TI_GPIO_LEVELDETECT0); 1139 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1140 return (TI_GPIO_LEVELDETECT1); 1141 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) { 1142 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1143 return (TI_GPIO_FALLINGDETECT); 1144 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1145 return (TI_GPIO_RISINGDETECT); 1146 } 1147 1148 return (0); 1149} 1150 1151static void 1152ti_gpio_mask_irq_internal(struct ti_gpio_softc *sc, int irq) 1153{ 1154 uint32_t reg, val; 1155 1156 if (ti_gpio_valid_pin(sc, irq) != 0) 1157 return; 1158 1159 TI_GPIO_LOCK(sc); 1160 ti_gpio_intr_clr(sc, TI_GPIO_MASK(irq)); 1161 reg = ti_gpio_intr_reg(sc, irq); 1162 if (reg != 0) { 1163 val = ti_gpio_read_4(sc, reg); 1164 val &= ~TI_GPIO_MASK(irq); 1165 ti_gpio_write_4(sc, reg, val); 1166 } 1167 TI_GPIO_UNLOCK(sc); 1168} 1169 1170static void 1171ti_gpio_unmask_irq_internal(struct ti_gpio_softc *sc, int irq) 1172{ 1173 uint32_t reg, val; 1174 1175 if (ti_gpio_valid_pin(sc, irq) != 0) 1176 return; 1177 1178 TI_GPIO_LOCK(sc); 1179 reg = ti_gpio_intr_reg(sc, irq); 1180 if (reg != 0) { 1181 val = ti_gpio_read_4(sc, reg); 1182 val |= TI_GPIO_MASK(irq); 1183 ti_gpio_write_4(sc, reg, val); 1184 ti_gpio_intr_set(sc, TI_GPIO_MASK(irq)); 1185 } 1186 TI_GPIO_UNLOCK(sc); 1187} 1188 1189static void 1190ti_gpio_mask_irq(void *source) 1191{ 1192 struct ti_gpio_mask_arg *arg = source; 1193 1194 ti_gpio_mask_irq_internal(arg->softc, arg->pin); 1195} 1196 1197static void 1198ti_gpio_unmask_irq(void *source) 1199{ 1200 struct ti_gpio_mask_arg *arg = source; 1201 1202 ti_gpio_unmask_irq_internal(arg->softc, arg->pin); 1203} 1204 1205static int 1206ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid, 1207 struct resource *res) 1208{ 1209 struct ti_gpio_mask_arg mask_arg; 1210 1211 if (type != SYS_RES_IRQ) 1212 return (ENXIO); 1213 1214 /* Unmask the interrupt. */ 1215 mask_arg.pin = rman_get_start(res); 1216 mask_arg.softc = device_get_softc(dev); 1217 1218 ti_gpio_unmask_irq((void *)&mask_arg); 1219 1220 return (0); 1221} 1222 1223static int 1224ti_gpio_deactivate_resource(device_t dev, device_t child, int type, int rid, 1225 struct resource *res) 1226{ 1227 int pin; 1228 1229 if (type != SYS_RES_IRQ) 1230 return (ENXIO); 1231 1232 /* Mask the interrupt. */ 1233 pin = rman_get_start(res); 1234 ti_gpio_mask_irq((void *)(uintptr_t)pin); 1235 1236 return (0); 1237} 1238 1239static int 1240ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, 1241 enum intr_polarity pol) 1242{ 1243 struct ti_gpio_softc *sc; 1244 uint32_t oldreg, reg, val; 1245 1246 sc = device_get_softc(dev); 1247 if (ti_gpio_valid_pin(sc, irq) != 0) 1248 return (EINVAL); 1249 1250 /* There is no standard trigger or polarity. */ 1251 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) 1252 return (EINVAL); 1253 1254 TI_GPIO_LOCK(sc); 1255 /* 1256 * TRM recommends add the new event before remove the old one to 1257 * avoid losing interrupts. 1258 */ 1259 oldreg = ti_gpio_intr_reg(sc, irq); 1260 sc->sc_irq_trigger[irq] = trig; 1261 sc->sc_irq_polarity[irq] = pol; 1262 reg = ti_gpio_intr_reg(sc, irq); 1263 if (reg != 0) { 1264 /* Apply the new settings. */ 1265 val = ti_gpio_read_4(sc, reg); 1266 val |= TI_GPIO_MASK(irq); 1267 ti_gpio_write_4(sc, reg, val); 1268 } 1269 if (reg != oldreg && oldreg != 0) { 1270 /* Remove the old settings. */ 1271 val = ti_gpio_read_4(sc, oldreg); 1272 val &= ~TI_GPIO_MASK(irq); 1273 ti_gpio_write_4(sc, oldreg, val); 1274 } 1275 TI_GPIO_UNLOCK(sc); 1276 1277 return (0); 1278} 1279 1280static int 1281ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires, 1282 int flags, driver_filter_t *filt, driver_intr_t *handler, 1283 void *arg, void **cookiep) 1284{ 1285 struct ti_gpio_softc *sc; 1286 struct intr_event *event; 1287 int pin, error; 1288 1289 sc = device_get_softc(dev); 1290 pin = rman_get_start(ires); 1291 if (ti_gpio_valid_pin(sc, pin) != 0) 1292 panic("%s: bad pin %d", __func__, pin); 1293 1294 event = sc->sc_events[pin]; 1295 if (event == NULL) { 1296 sc->sc_mask_args[pin].softc = sc; 1297 sc->sc_mask_args[pin].pin = pin; 1298 error = intr_event_create(&event, (void *)&sc->sc_mask_args[pin], 0, 1299 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL, 1300 "gpio%d pin%d:", device_get_unit(dev), pin); 1301 if (error != 0) 1302 return (error); 1303 sc->sc_events[pin] = event; 1304 } 1305 intr_event_add_handler(event, device_get_nameunit(child), filt, 1306 handler, arg, intr_priority(flags), flags, cookiep); 1307 1308 return (0); 1309} 1310 1311static int 1312ti_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires, 1313 void *cookie) 1314{ 1315 struct ti_gpio_softc *sc; 1316 int pin, err; 1317 1318 sc = device_get_softc(dev); 1319 pin = rman_get_start(ires); 1320 if (ti_gpio_valid_pin(sc, pin) != 0) 1321 panic("%s: bad pin %d", __func__, pin); 1322 if (sc->sc_events[pin] == NULL) 1323 panic("Trying to teardown unoccupied IRQ"); 1324 err = intr_event_remove_handler(cookie); 1325 if (!err) 1326 sc->sc_events[pin] = NULL; 1327 1328 return (err); 1329} 1330#endif 1331 1332static phandle_t 1333ti_gpio_get_node(device_t bus, device_t dev) 1334{ 1335 1336 /* We only have one child, the GPIO bus, which needs our own node. */ 1337 return (ofw_bus_get_node(bus)); 1338} 1339 1340static device_method_t ti_gpio_methods[] = { 1341 DEVMETHOD(device_attach, ti_gpio_attach), 1342 DEVMETHOD(device_detach, ti_gpio_detach), 1343 1344 /* GPIO protocol */ 1345 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 1346 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1347 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1348 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1349 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1350 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1351 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1352 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1353 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1354 1355#ifdef INTRNG 1356 /* Interrupt controller interface */ 1357 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr), 1358 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr), 1359 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr), 1360 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr), 1361 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr), 1362 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter), 1363 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread), 1364 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread), 1365#else 1366 /* Bus interface */ 1367 DEVMETHOD(bus_activate_resource, ti_gpio_activate_resource), 1368 DEVMETHOD(bus_deactivate_resource, ti_gpio_deactivate_resource), 1369 DEVMETHOD(bus_config_intr, ti_gpio_config_intr), 1370 DEVMETHOD(bus_setup_intr, ti_gpio_setup_intr), 1371 DEVMETHOD(bus_teardown_intr, ti_gpio_teardown_intr), 1372#endif 1373 1374 /* ofw_bus interface */ 1375 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1376 1377 {0, 0}, 1378}; 1379 1380driver_t ti_gpio_driver = { 1381 "gpio", 1382 ti_gpio_methods, 1383 sizeof(struct ti_gpio_softc), 1384}; 1385