uart_dev_oct16550.c revision 331722
1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27/* 28 * uart_dev_oct16550.c 29 * 30 * Derived from uart_dev_ns8250.c 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 43 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 44 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 45 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 47 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 48 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 49 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 50 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 51 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 52 * 53 * 54 */ 55 56 57#include <sys/cdefs.h> 58__FBSDID("$FreeBSD: stable/11/sys/mips/cavium/uart_dev_oct16550.c 331722 2018-03-29 02:50:57Z eadler $"); 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/bus.h> 63#include <sys/conf.h> 64#include <machine/bus.h> 65#include <machine/pcpu.h> 66 67#include <dev/uart/uart.h> 68#include <dev/uart/uart_cpu.h> 69#include <dev/uart/uart_bus.h> 70 71#include <dev/ic/ns16550.h> 72 73#include <mips/cavium/octeon_pcmap_regs.h> 74 75#include <contrib/octeon-sdk/cvmx.h> 76 77#include "uart_if.h" 78 79/* 80 * Clear pending interrupts. THRE is cleared by reading IIR. Data 81 * that may have been received gets lost here. 82 */ 83static void 84oct16550_clrint (struct uart_bas *bas) 85{ 86 uint8_t iir; 87 88 iir = uart_getreg(bas, REG_IIR); 89 while ((iir & IIR_NOPEND) == 0) { 90 iir &= IIR_IMASK; 91 if (iir == IIR_RLS) 92 (void)uart_getreg(bas, REG_LSR); 93 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 94 (void)uart_getreg(bas, REG_DATA); 95 else if (iir == IIR_MLSC) 96 (void)uart_getreg(bas, REG_MSR); 97 else if (iir == IIR_BUSY) 98 (void) uart_getreg(bas, REG_USR); 99 uart_barrier(bas); 100 iir = uart_getreg(bas, REG_IIR); 101 } 102} 103 104static int delay_changed = 1; 105 106static int 107oct16550_delay (struct uart_bas *bas) 108{ 109 int divisor; 110 u_char lcr; 111 static int delay = 0; 112 113 if (!delay_changed) return delay; 114 delay_changed = 0; 115 lcr = uart_getreg(bas, REG_LCR); 116 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 117 uart_barrier(bas); 118 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 119 uart_barrier(bas); 120 uart_setreg(bas, REG_LCR, lcr); 121 uart_barrier(bas); 122 123 if(!bas->rclk) 124 return 10; /* return an approx delay value */ 125 126 /* 1/10th the time to transmit 1 character (estimate). */ 127 if (divisor <= 134) 128 return (16000000 * divisor / bas->rclk); 129 return (16000 * divisor / (bas->rclk / 1000)); 130 131} 132 133static int 134oct16550_divisor (int rclk, int baudrate) 135{ 136 int actual_baud, divisor; 137 int error; 138 139 if (baudrate == 0) 140 return (0); 141 142 divisor = (rclk / (baudrate << 3) + 1) >> 1; 143 if (divisor == 0 || divisor >= 65536) 144 return (0); 145 actual_baud = rclk / (divisor << 4); 146 147 /* 10 times error in percent: */ 148 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 149 150 /* 3.0% maximum error tolerance: */ 151 if (error < -30 || error > 30) 152 return (0); 153 154 return (divisor); 155} 156 157static int 158oct16550_drain (struct uart_bas *bas, int what) 159{ 160 int delay, limit; 161 162 delay = oct16550_delay(bas); 163 164 if (what & UART_DRAIN_TRANSMITTER) { 165 /* 166 * Pick an arbitrary high limit to avoid getting stuck in 167 * an infinite loop when the hardware is broken. Make the 168 * limit high enough to handle large FIFOs. 169 */ 170 limit = 10*10*10*1024; 171 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 172 DELAY(delay); 173 if (limit == 0) { 174 /* printf("oct16550: transmitter appears stuck... "); */ 175 return (0); 176 } 177 } 178 179 if (what & UART_DRAIN_RECEIVER) { 180 /* 181 * Pick an arbitrary high limit to avoid getting stuck in 182 * an infinite loop when the hardware is broken. Make the 183 * limit high enough to handle large FIFOs and integrated 184 * UARTs. The HP rx2600 for example has 3 UARTs on the 185 * management board that tend to get a lot of data send 186 * to it when the UART is first activated. 187 */ 188 limit=10*4096; 189 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 190 (void)uart_getreg(bas, REG_DATA); 191 uart_barrier(bas); 192 DELAY(delay << 2); 193 } 194 if (limit == 0) { 195 /* printf("oct16550: receiver appears broken... "); */ 196 return (EIO); 197 } 198 } 199 200 return (0); 201} 202 203/* 204 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 205 * drained. WARNING: this function clobbers the FIFO setting! 206 */ 207static void 208oct16550_flush (struct uart_bas *bas, int what) 209{ 210 uint8_t fcr; 211 212 fcr = FCR_ENABLE; 213 if (what & UART_FLUSH_TRANSMITTER) 214 fcr |= FCR_XMT_RST; 215 if (what & UART_FLUSH_RECEIVER) 216 fcr |= FCR_RCV_RST; 217 uart_setreg(bas, REG_FCR, fcr); 218 uart_barrier(bas); 219} 220 221static int 222oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits, 223 int parity) 224{ 225 int divisor; 226 uint8_t lcr; 227 228 lcr = 0; 229 if (databits >= 8) 230 lcr |= LCR_8BITS; 231 else if (databits == 7) 232 lcr |= LCR_7BITS; 233 else if (databits == 6) 234 lcr |= LCR_6BITS; 235 else 236 lcr |= LCR_5BITS; 237 if (stopbits > 1) 238 lcr |= LCR_STOPB; 239 lcr |= parity << 3; 240 241 /* Set baudrate. */ 242 if (baudrate > 0) { 243 divisor = oct16550_divisor(bas->rclk, baudrate); 244 if (divisor == 0) 245 return (EINVAL); 246 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 247 uart_barrier(bas); 248 uart_setreg(bas, REG_DLL, divisor & 0xff); 249 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 250 uart_barrier(bas); 251 delay_changed = 1; 252 } 253 254 /* Set LCR and clear DLAB. */ 255 uart_setreg(bas, REG_LCR, lcr); 256 uart_barrier(bas); 257 return (0); 258} 259 260/* 261 * Low-level UART interface. 262 */ 263static int oct16550_probe(struct uart_bas *bas); 264static void oct16550_init(struct uart_bas *bas, int, int, int, int); 265static void oct16550_term(struct uart_bas *bas); 266static void oct16550_putc(struct uart_bas *bas, int); 267static int oct16550_rxready(struct uart_bas *bas); 268static int oct16550_getc(struct uart_bas *bas, struct mtx *); 269 270struct uart_ops uart_oct16550_ops = { 271 .probe = oct16550_probe, 272 .init = oct16550_init, 273 .term = oct16550_term, 274 .putc = oct16550_putc, 275 .rxready = oct16550_rxready, 276 .getc = oct16550_getc, 277}; 278 279static int 280oct16550_probe (struct uart_bas *bas) 281{ 282 u_char val; 283 284 /* Check known 0 bits that don't depend on DLAB. */ 285 val = uart_getreg(bas, REG_IIR); 286 if (val & 0x30) 287 return (ENXIO); 288 val = uart_getreg(bas, REG_MCR); 289 if (val & 0xc0) 290 return (ENXIO); 291 val = uart_getreg(bas, REG_USR); 292 if (val & 0xe0) 293 return (ENXIO); 294 return (0); 295} 296 297static void 298oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits, 299 int parity) 300{ 301 u_char ier; 302 303 oct16550_param(bas, baudrate, databits, stopbits, parity); 304 305 /* Disable all interrupt sources. */ 306 ier = uart_getreg(bas, REG_IER) & 0x0; 307 uart_setreg(bas, REG_IER, ier); 308 uart_barrier(bas); 309 310 /* Disable the FIFO (if present). */ 311// uart_setreg(bas, REG_FCR, 0); 312 uart_barrier(bas); 313 314 /* Set RTS & DTR. */ 315 uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR); 316 uart_barrier(bas); 317 318 oct16550_clrint(bas); 319} 320 321static void 322oct16550_term (struct uart_bas *bas) 323{ 324 325 /* Clear RTS & DTR. */ 326 uart_setreg(bas, REG_MCR, 0); 327 uart_barrier(bas); 328} 329 330static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay) 331{ 332 while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) && 333 ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0)) 334 DELAY(delay); 335} 336 337static void 338oct16550_putc (struct uart_bas *bas, int c) 339{ 340 int delay; 341 342 /* 1/10th the time to transmit 1 character (estimate). */ 343 delay = oct16550_delay(bas); 344 oct16550_wait_txhr_empty(bas, 100, delay); 345 uart_setreg(bas, REG_DATA, c); 346 uart_barrier(bas); 347 oct16550_wait_txhr_empty(bas, 100, delay); 348} 349 350static int 351oct16550_rxready (struct uart_bas *bas) 352{ 353 354 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 355} 356 357static int 358oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx) 359{ 360 int c, delay; 361 362 uart_lock(hwmtx); 363 364 /* 1/10th the time to transmit 1 character (estimate). */ 365 delay = oct16550_delay(bas); 366 367 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 368 uart_unlock(hwmtx); 369 DELAY(delay); 370 uart_lock(hwmtx); 371 } 372 373 c = uart_getreg(bas, REG_DATA); 374 375 uart_unlock(hwmtx); 376 377 return (c); 378} 379 380/* 381 * High-level UART interface. 382 */ 383struct oct16550_softc { 384 struct uart_softc base; 385 uint8_t fcr; 386 uint8_t ier; 387 uint8_t mcr; 388}; 389 390static int oct16550_bus_attach(struct uart_softc *); 391static int oct16550_bus_detach(struct uart_softc *); 392static int oct16550_bus_flush(struct uart_softc *, int); 393static int oct16550_bus_getsig(struct uart_softc *); 394static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t); 395static int oct16550_bus_ipend(struct uart_softc *); 396static int oct16550_bus_param(struct uart_softc *, int, int, int, int); 397static int oct16550_bus_probe(struct uart_softc *); 398static int oct16550_bus_receive(struct uart_softc *); 399static int oct16550_bus_setsig(struct uart_softc *, int); 400static int oct16550_bus_transmit(struct uart_softc *); 401static void oct16550_bus_grab(struct uart_softc *); 402static void oct16550_bus_ungrab(struct uart_softc *); 403 404static kobj_method_t oct16550_methods[] = { 405 KOBJMETHOD(uart_attach, oct16550_bus_attach), 406 KOBJMETHOD(uart_detach, oct16550_bus_detach), 407 KOBJMETHOD(uart_flush, oct16550_bus_flush), 408 KOBJMETHOD(uart_getsig, oct16550_bus_getsig), 409 KOBJMETHOD(uart_ioctl, oct16550_bus_ioctl), 410 KOBJMETHOD(uart_ipend, oct16550_bus_ipend), 411 KOBJMETHOD(uart_param, oct16550_bus_param), 412 KOBJMETHOD(uart_probe, oct16550_bus_probe), 413 KOBJMETHOD(uart_receive, oct16550_bus_receive), 414 KOBJMETHOD(uart_setsig, oct16550_bus_setsig), 415 KOBJMETHOD(uart_transmit, oct16550_bus_transmit), 416 KOBJMETHOD(uart_grab, oct16550_bus_grab), 417 KOBJMETHOD(uart_ungrab, oct16550_bus_ungrab), 418 { 0, 0 } 419}; 420 421struct uart_class uart_oct16550_class = { 422 "oct16550 class", 423 oct16550_methods, 424 sizeof(struct oct16550_softc), 425 .uc_ops = &uart_oct16550_ops, 426 .uc_range = 8 << 3, 427 .uc_rclk = 0, 428 .uc_rshift = 0 429}; 430 431#define SIGCHG(c, i, s, d) \ 432 if (c) { \ 433 i |= (i & s) ? s : s | d; \ 434 } else { \ 435 i = (i & s) ? (i & ~s) | d : i; \ 436 } 437 438static int 439oct16550_bus_attach (struct uart_softc *sc) 440{ 441 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 442 struct uart_bas *bas; 443 int unit; 444 445 unit = device_get_unit(sc->sc_dev); 446 bas = &sc->sc_bas; 447 448 oct16550_drain(bas, UART_DRAIN_TRANSMITTER); 449 oct16550->mcr = uart_getreg(bas, REG_MCR); 450 oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH; 451 uart_setreg(bas, REG_FCR, oct16550->fcr); 452 uart_barrier(bas); 453 oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 454 455 if (oct16550->mcr & MCR_DTR) 456 sc->sc_hwsig |= SER_DTR; 457 if (oct16550->mcr & MCR_RTS) 458 sc->sc_hwsig |= SER_RTS; 459 oct16550_bus_getsig(sc); 460 461 oct16550_clrint(bas); 462 oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0; 463 oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY; 464 uart_setreg(bas, REG_IER, oct16550->ier); 465 uart_barrier(bas); 466 467 return (0); 468} 469 470static int 471oct16550_bus_detach (struct uart_softc *sc) 472{ 473 struct uart_bas *bas; 474 u_char ier; 475 476 bas = &sc->sc_bas; 477 ier = uart_getreg(bas, REG_IER) & 0xf0; 478 uart_setreg(bas, REG_IER, ier); 479 uart_barrier(bas); 480 oct16550_clrint(bas); 481 return (0); 482} 483 484static int 485oct16550_bus_flush (struct uart_softc *sc, int what) 486{ 487 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 488 struct uart_bas *bas; 489 int error; 490 491 bas = &sc->sc_bas; 492 uart_lock(sc->sc_hwmtx); 493 if (sc->sc_rxfifosz > 1) { 494 oct16550_flush(bas, what); 495 uart_setreg(bas, REG_FCR, oct16550->fcr); 496 uart_barrier(bas); 497 error = 0; 498 } else 499 error = oct16550_drain(bas, what); 500 uart_unlock(sc->sc_hwmtx); 501 return (error); 502} 503 504static int 505oct16550_bus_getsig (struct uart_softc *sc) 506{ 507 uint32_t new, old, sig; 508 uint8_t msr; 509 510 do { 511 old = sc->sc_hwsig; 512 sig = old; 513 uart_lock(sc->sc_hwmtx); 514 msr = uart_getreg(&sc->sc_bas, REG_MSR); 515 uart_unlock(sc->sc_hwmtx); 516 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 517 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 518 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 519 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 520 new = sig & ~SER_MASK_DELTA; 521 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 522 return (sig); 523} 524 525static int 526oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data) 527{ 528 struct uart_bas *bas; 529 int baudrate, divisor, error; 530 uint8_t efr, lcr; 531 532 bas = &sc->sc_bas; 533 error = 0; 534 uart_lock(sc->sc_hwmtx); 535 switch (request) { 536 case UART_IOCTL_BREAK: 537 lcr = uart_getreg(bas, REG_LCR); 538 if (data) 539 lcr |= LCR_SBREAK; 540 else 541 lcr &= ~LCR_SBREAK; 542 uart_setreg(bas, REG_LCR, lcr); 543 uart_barrier(bas); 544 break; 545 case UART_IOCTL_IFLOW: 546 lcr = uart_getreg(bas, REG_LCR); 547 uart_barrier(bas); 548 uart_setreg(bas, REG_LCR, 0xbf); 549 uart_barrier(bas); 550 efr = uart_getreg(bas, REG_EFR); 551 if (data) 552 efr |= EFR_RTS; 553 else 554 efr &= ~EFR_RTS; 555 uart_setreg(bas, REG_EFR, efr); 556 uart_barrier(bas); 557 uart_setreg(bas, REG_LCR, lcr); 558 uart_barrier(bas); 559 break; 560 case UART_IOCTL_OFLOW: 561 lcr = uart_getreg(bas, REG_LCR); 562 uart_barrier(bas); 563 uart_setreg(bas, REG_LCR, 0xbf); 564 uart_barrier(bas); 565 efr = uart_getreg(bas, REG_EFR); 566 if (data) 567 efr |= EFR_CTS; 568 else 569 efr &= ~EFR_CTS; 570 uart_setreg(bas, REG_EFR, efr); 571 uart_barrier(bas); 572 uart_setreg(bas, REG_LCR, lcr); 573 uart_barrier(bas); 574 break; 575 case UART_IOCTL_BAUD: 576 lcr = uart_getreg(bas, REG_LCR); 577 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 578 uart_barrier(bas); 579 divisor = uart_getreg(bas, REG_DLL) | 580 (uart_getreg(bas, REG_DLH) << 8); 581 uart_barrier(bas); 582 uart_setreg(bas, REG_LCR, lcr); 583 uart_barrier(bas); 584 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 585 delay_changed = 1; 586 if (baudrate > 0) 587 *(int*)data = baudrate; 588 else 589 error = ENXIO; 590 break; 591 default: 592 error = EINVAL; 593 break; 594 } 595 uart_unlock(sc->sc_hwmtx); 596 return (error); 597} 598 599 600static int 601oct16550_bus_ipend(struct uart_softc *sc) 602{ 603 struct uart_bas *bas; 604 int ipend = 0; 605 uint8_t iir, lsr; 606 607 bas = &sc->sc_bas; 608 uart_lock(sc->sc_hwmtx); 609 610 iir = uart_getreg(bas, REG_IIR) & IIR_IMASK; 611 if (iir != IIR_NOPEND) { 612 613 if (iir == IIR_RLS) { 614 lsr = uart_getreg(bas, REG_LSR); 615 if (lsr & LSR_OE) 616 ipend |= SER_INT_OVERRUN; 617 if (lsr & LSR_BI) 618 ipend |= SER_INT_BREAK; 619 if (lsr & LSR_RXRDY) 620 ipend |= SER_INT_RXREADY; 621 622 } else if (iir == IIR_RXRDY) { 623 ipend |= SER_INT_RXREADY; 624 625 } else if (iir == IIR_RXTOUT) { 626 ipend |= SER_INT_RXREADY; 627 628 } else if (iir == IIR_TXRDY) { 629 ipend |= SER_INT_TXIDLE; 630 631 } else if (iir == IIR_MLSC) { 632 ipend |= SER_INT_SIGCHG; 633 634 } else if (iir == IIR_BUSY) { 635 (void) uart_getreg(bas, REG_USR); 636 } 637 } 638 uart_unlock(sc->sc_hwmtx); 639 640 return (ipend); 641} 642 643static int 644oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits, 645 int stopbits, int parity) 646{ 647 struct uart_bas *bas; 648 int error; 649 650 bas = &sc->sc_bas; 651 uart_lock(sc->sc_hwmtx); 652 error = oct16550_param(bas, baudrate, databits, stopbits, parity); 653 uart_unlock(sc->sc_hwmtx); 654 return (error); 655} 656 657static int 658oct16550_bus_probe (struct uart_softc *sc) 659{ 660 struct uart_bas *bas; 661 int error; 662 663 bas = &sc->sc_bas; 664 bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK); 665 666 error = oct16550_probe(bas); 667 if (error) { 668 return (error); 669 } 670 671 uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS)); 672 673 /* 674 * Enable FIFOs. And check that the UART has them. If not, we're 675 * done. Since this is the first time we enable the FIFOs, we reset 676 * them. 677 */ 678 oct16550_drain(bas, UART_DRAIN_TRANSMITTER); 679#define ENABLE_OCTEON_FIFO 1 680#ifdef ENABLE_OCTEON_FIFO 681 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 682#endif 683 uart_barrier(bas); 684 685 oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 686 687 if (device_get_unit(sc->sc_dev)) { 688 device_set_desc(sc->sc_dev, "Octeon-16550 channel 1"); 689 } else { 690 device_set_desc(sc->sc_dev, "Octeon-16550 channel 0"); 691 } 692#ifdef ENABLE_OCTEON_FIFO 693 sc->sc_rxfifosz = 64; 694 sc->sc_txfifosz = 64; 695#else 696 sc->sc_rxfifosz = 1; 697 sc->sc_txfifosz = 1; 698#endif 699 700 701#if 0 702 /* 703 * XXX there are some issues related to hardware flow control and 704 * it's likely that uart(4) is the cause. This basicly needs more 705 * investigation, but we avoid using for hardware flow control 706 * until then. 707 */ 708 /* 16650s or higher have automatic flow control. */ 709 if (sc->sc_rxfifosz > 16) { 710 sc->sc_hwiflow = 1; 711 sc->sc_hwoflow = 1; 712 } 713#endif 714 715 return (0); 716} 717 718static int 719oct16550_bus_receive (struct uart_softc *sc) 720{ 721 struct uart_bas *bas; 722 int xc; 723 uint8_t lsr; 724 725 bas = &sc->sc_bas; 726 uart_lock(sc->sc_hwmtx); 727 lsr = uart_getreg(bas, REG_LSR); 728 729 while (lsr & LSR_RXRDY) { 730 if (uart_rx_full(sc)) { 731 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 732 break; 733 } 734 xc = uart_getreg(bas, REG_DATA); 735 if (lsr & LSR_FE) 736 xc |= UART_STAT_FRAMERR; 737 if (lsr & LSR_PE) 738 xc |= UART_STAT_PARERR; 739 uart_rx_put(sc, xc); 740 lsr = uart_getreg(bas, REG_LSR); 741 } 742 /* Discard everything left in the Rx FIFO. */ 743 /* 744 * First do a dummy read/discard anyway, in case the UART was lying to us. 745 * This problem was seen on board, when IIR said RBR, but LSR said no RXRDY 746 * Results in a stuck ipend loop. 747 */ 748 (void)uart_getreg(bas, REG_DATA); 749 while (lsr & LSR_RXRDY) { 750 (void)uart_getreg(bas, REG_DATA); 751 uart_barrier(bas); 752 lsr = uart_getreg(bas, REG_LSR); 753 } 754 uart_unlock(sc->sc_hwmtx); 755 return (0); 756} 757 758static int 759oct16550_bus_setsig (struct uart_softc *sc, int sig) 760{ 761 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 762 struct uart_bas *bas; 763 uint32_t new, old; 764 765 bas = &sc->sc_bas; 766 do { 767 old = sc->sc_hwsig; 768 new = old; 769 if (sig & SER_DDTR) { 770 SIGCHG(sig & SER_DTR, new, SER_DTR, 771 SER_DDTR); 772 } 773 if (sig & SER_DRTS) { 774 SIGCHG(sig & SER_RTS, new, SER_RTS, 775 SER_DRTS); 776 } 777 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 778 uart_lock(sc->sc_hwmtx); 779 oct16550->mcr &= ~(MCR_DTR|MCR_RTS); 780 if (new & SER_DTR) 781 oct16550->mcr |= MCR_DTR; 782 if (new & SER_RTS) 783 oct16550->mcr |= MCR_RTS; 784 uart_setreg(bas, REG_MCR, oct16550->mcr); 785 uart_barrier(bas); 786 uart_unlock(sc->sc_hwmtx); 787 return (0); 788} 789 790static int 791oct16550_bus_transmit (struct uart_softc *sc) 792{ 793 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 794 struct uart_bas *bas; 795 int i; 796 797 bas = &sc->sc_bas; 798 uart_lock(sc->sc_hwmtx); 799#ifdef NO_UART_INTERRUPTS 800 for (i = 0; i < sc->sc_txdatasz; i++) { 801 oct16550_putc(bas, sc->sc_txbuf[i]); 802 } 803#else 804 805 oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas)); 806 uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY); 807 uart_barrier(bas); 808 809 for (i = 0; i < sc->sc_txdatasz; i++) { 810 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 811 uart_barrier(bas); 812 } 813 sc->sc_txbusy = 1; 814#endif 815 uart_unlock(sc->sc_hwmtx); 816 return (0); 817} 818 819static void 820oct16550_bus_grab(struct uart_softc *sc) 821{ 822 struct uart_bas *bas = &sc->sc_bas; 823 824 /* 825 * turn off all interrupts to enter polling mode. Leave the 826 * saved mask alone. We'll restore whatever it was in ungrab. 827 * All pending interupt signals are reset when IER is set to 0. 828 */ 829 uart_lock(sc->sc_hwmtx); 830 uart_setreg(bas, REG_IER, 0); 831 uart_barrier(bas); 832 uart_unlock(sc->sc_hwmtx); 833} 834 835static void 836oct16550_bus_ungrab(struct uart_softc *sc) 837{ 838 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 839 struct uart_bas *bas = &sc->sc_bas; 840 841 /* 842 * Restore previous interrupt mask 843 */ 844 uart_lock(sc->sc_hwmtx); 845 uart_setreg(bas, REG_IER, oct16550->ier); 846 uart_barrier(bas); 847 uart_unlock(sc->sc_hwmtx); 848} 849