mvwin.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of MARVELL nor the names of contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: stable/11/sys/arm/mv/mvwin.h 330897 2018-03-14 03:19:51Z eadler $ 34 */ 35 36#ifndef _MVWIN_H_ 37#define _MVWIN_H_ 38 39/* 40 * Decode windows addresses. 41 * 42 * All decoding windows must be aligned to their size, which has to be 43 * a power of 2. 44 */ 45 46/* 47 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA) 48 */ 49 50/* SoC Regs */ 51#define MV_PHYS_BASE 0xF1000000 52#define MV_SIZE (1024 * 1024) /* 1 MB */ 53 54/* SRAM */ 55#define MV_CESA_SRAM_BASE 0xF1100000 56 57/* AXI Regs */ 58#ifdef SOC_MV_DOVE 59#define MV_AXI_PHYS_BASE 0xF1800000 60#define MV_AXI_BASE MV_AXI_PHYS_BASE 61#define MV_AXI_SIZE (16 * 1024 * 1024) /* 16 MB */ 62#endif 63 64/* 65 * External devices: 0x80000000, 1 GB (VA == PA) 66 * Includes Device Bus, PCI and PCIE. 67 */ 68#if defined(SOC_MV_ORION) 69#define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */ 70#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_FREY) 71#define MV_PCI_PORTS 1 /* 1x PCIE */ 72#elif defined(SOC_MV_DISCOVERY) 73#define MV_PCI_PORTS 8 /* 8x PCIE */ 74#elif defined(SOC_MV_DOVE) || defined(SOC_MV_LOKIPLUS) 75#define MV_PCI_PORTS 2 /* 2x PCIE */ 76#elif defined(SOC_MV_ARMADAXP) 77#define MV_PCI_PORTS 3 /* 3x PCIE */ 78#elif defined(SOC_MV_ARMADA38X) 79#define MV_PCI_PORTS 4 /* 4x PCIE */ 80#else 81#error "MV_PCI_PORTS not configured !" 82#endif 83 84/* PCI/PCIE Memory */ 85#define MV_PCI_MEM_PHYS_BASE 0x80000000 86#define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */ 87#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 88#define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS) 89#define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \ 90 MV_PCI_MEM_SLICE_SIZE)) 91/* PCI/PCIE I/O */ 92#define MV_PCI_IO_PHYS_BASE 0xBF000000 93#define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */ 94#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 95#define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS) 96#define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE)) 97 98#if defined(SOC_MV_FREY) 99#define MV_PCI_VA_MEM_BASE MV_PCI_MEM_BASE 100#else 101#define MV_PCI_VA_MEM_BASE 0 102#endif 103#define MV_PCI_VA_IO_BASE 0 104 105/* 106 * Device Bus (VA == PA) 107 */ 108#define MV_DEV_BOOT_BASE 0xF9300000 109#define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ 110 111#define MV_DEV_CS0_BASE 0xF9400000 112#define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ 113 114#define MV_DEV_CS1_BASE 0xF9500000 115#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 116 117#define MV_DEV_CS2_BASE 0xFB500000 118#define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 119 120 121/* 122 * Integrated SoC peripherals addresses 123 */ 124#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 125#if defined(SOC_MV_DOVE) 126#define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100) 127#elif defined(SOC_MV_LOKIPLUS) 128#define MV_DDR_CADR_BASE (MV_BASE + 0xF1500) 129#elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 130#define MV_DDR_CADR_BASE (MV_BASE + 0x20180) 131#else 132#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 133#endif 134#define MV_MPP_BASE (MV_BASE + 0x10000) 135 136#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 137#define MV_MISC_BASE (MV_BASE + 0x18200) 138#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 139#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 140#define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700) 141#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800) 142#elif !defined(SOC_MV_FREY) 143#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 144#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 145#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 146#else 147#define MV_CPU_CONTROL_BASE (MV_BASE + 0x10000) 148#endif 149 150#define MV_PCI_BASE (MV_BASE + 0x30000) 151#define MV_PCI_SIZE 0x2000 152 153#if defined(SOC_MV_FREY) 154#define MV_PCIE_BASE (MV_BASE + 0x8000) 155#elif defined(SOC_MV_ARMADA38X) 156#define MV_PCIE_BASE (MV_BASE + 0x80000) 157#else 158#define MV_PCIE_BASE (MV_BASE + 0x40000) 159#endif 160#define MV_PCIE_SIZE 0x2000 161 162#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 163#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 164#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 165#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 166#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 167#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 168#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 169#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 170 171#define MV_SDIO_BASE (MV_BASE + 0x90000) 172#define MV_SDIO_SIZE 0x10000 173 174/* 175 * Decode windows definitions and macros 176 */ 177#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 178#define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) 179#define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) 180#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008) 181#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C) 182#else 183#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 184#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 185#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 186#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 187#endif 188 189#if defined(SOC_MV_DISCOVERY) 190#define MV_WIN_CPU_MAX 14 191#elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 192#define MV_WIN_CPU_MAX 20 193#else 194#define MV_WIN_CPU_MAX 8 195#endif 196 197#define MV_WIN_CPU_ATTR_SHIFT 8 198#if defined(SOC_MV_LOKIPLUS) 199#define MV_WIN_CPU_TARGET_SHIFT 0 200#define MV_WIN_CPU_ENABLE_BIT (1 << 5) 201#else 202#define MV_WIN_CPU_TARGET_SHIFT 4 203#define MV_WIN_CPU_ENABLE_BIT 1 204#endif 205 206#if defined(SOC_MV_DOVE) 207#define MV_WIN_DDR_MAX 2 208#else /* SOC_MV_DOVE */ 209#if defined(SOC_MV_LOKIPLUS) 210#define MV_WIN_DDR_BASE(n) (0xc * (n) + 0x4) 211#define MV_WIN_DDR_SIZE(n) (0xc * (n) + 0x0) 212#else /* SOC_MV_LOKIPLUS */ 213#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 214#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 215#endif /* SOC_MV_LOKIPLUS */ 216#define MV_WIN_DDR_MAX 4 217#endif /* SOC_MV_DOVE */ 218 219/* 220 * These values are valid only for peripherals decoding windows 221 * Bit in ATTR is zeroed according to CS bank number 222 */ 223#define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs))) 224#define MV_WIN_DDR_TARGET 0x0 225 226#if defined(SOC_MV_DISCOVERY) 227#define MV_WIN_CESA_TARGET 9 228#define MV_WIN_CESA_ATTR(eng_sel) 1 229#elif defined(SOC_MV_ARMADAXP) 230#define MV_WIN_CESA_TARGET 9 231/* 232 * Bits [2:3] of cesa attribute select engine: 233 * eng_sel: 234 * 1: engine1 235 * 2: engine0 236 */ 237#define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2)) 238#elif defined(SOC_MV_ARMADA38X) 239#define MV_WIN_CESA_TARGET 9 240/* 241 * Bits [1:0] = Data swapping 242 * 0x0 = Byte swap 243 * 0x1 = No swap 244 * 0x2 = Byte and word swap 245 * 0x3 = Word swap 246 * Bits [4:2] = CESA select: 247 * 0x6 = CESA0 248 * 0x5 = CESA1 249 */ 250#define MV_WIN_CESA_ATTR(eng_sel) (0x11 | (1 << (3 - (eng_sel)))) 251#else 252#define MV_WIN_CESA_TARGET 3 253#define MV_WIN_CESA_ATTR(eng_sel) 0 254#endif 255 256#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) 257#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) 258#define MV_WIN_USB_MAX 4 259 260#define MV_WIN_USB3_CTRL(n) (0x8 * (n)) 261#define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4) 262#define MV_WIN_USB3_MAX 8 263 264#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 265#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 266#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 267#define MV_WIN_ETH_MAX 6 268 269#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 270#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 271#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 272#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 273#define MV_WIN_IDMA_MAX 8 274#define MV_IDMA_CHAN_MAX 4 275 276#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 277#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 278#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 279#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 280#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 281#define MV_WIN_XOR_MAX 8 282#define MV_XOR_CHAN_MAX 2 283#define MV_XOR_NON_REMAP 4 284 285#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DOVE) 286#define MV_WIN_PCIE_TARGET(n) 4 287#define MV_WIN_PCIE_MEM_ATTR(n) 0xE8 288#define MV_WIN_PCIE_IO_ATTR(n) 0xE0 289#elif defined(SOC_MV_ARMADAXP) 290#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2))) 291#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2))) 292#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2))) 293#elif defined(SOC_MV_ARMADA38X) 294#define MV_WIN_PCIE_TARGET(n) ((n) == 0 ? 8 : 4) 295#define MV_WIN_PCIE_MEM_ATTR(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20))) 296#define MV_WIN_PCIE_IO_ATTR(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20))) 297#elif defined(SOC_MV_ORION) 298#define MV_WIN_PCIE_TARGET(n) 4 299#define MV_WIN_PCIE_MEM_ATTR(n) 0x59 300#define MV_WIN_PCIE_IO_ATTR(n) 0x51 301#elif defined(SOC_MV_LOKIPLUS) 302#define MV_WIN_PCIE_TARGET(n) (3 + (n)) 303#define MV_WIN_PCIE_MEM_ATTR(n) 0x59 304#define MV_WIN_PCIE_IO_ATTR(n) 0x51 305#endif 306 307#define MV_WIN_PCI_TARGET 3 308#define MV_WIN_PCI_MEM_ATTR 0x59 309#define MV_WIN_PCI_IO_ATTR 0x51 310 311#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 312 (n) + 1) + 0x1820) 313#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 314 (n) + 1) + 0x1824) 315#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 316 (n) + 1) + 0x182C) 317#define MV_WIN_PCIE_MAX 6 318 319#define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800) 320#define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010) 321#define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) 322#define MV_PCIE_BAR_MAX 4 323#define MV_PCIE_BAR_64BIT (0x4) 324#define MV_PCIE_BAR_PREFETCH_EN (0x8) 325 326#define MV_PCIE_CONTROL (0x1a00) 327#define MV_PCIE_ROOT_CMPLX (1 << 1) 328 329#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 330#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 331#define MV_WIN_SATA_MAX 4 332 333#if defined(SOC_MV_ARMADA38X) 334#define MV_BOOTROM_MEM_ADDR 0xFFF00000 335#define MV_BOOTROM_WIN_SIZE 0xF 336#define MV_CPU_SUBSYS_REGS_LEN 0x100 337 338/* IO Window Control Register fields */ 339#define IO_WIN_SIZE_SHIFT 16 340#define IO_WIN_SIZE_MASK 0xFFFF 341#define IO_WIN_ATTR_SHIFT 8 342#define IO_WIN_ATTR_MASK 0xFF 343#define IO_WIN_TGT_SHIFT 4 344#define IO_WIN_TGT_MASK 0xF 345#define IO_WIN_SYNC_SHIFT 1 346#define IO_WIN_SYNC_MASK 0x1 347#define IO_WIN_ENA_SHIFT 0 348#define IO_WIN_ENA_MASK 0x1 349 350#define IO_WIN_9_CTRL_OFFSET 0x98 351#define IO_WIN_9_BASE_OFFSET 0x9C 352 353/* Mbus decoding unit IDs and attributes */ 354#define MBUS_BOOTROM_TGT_ID 0x1 355#define MBUS_BOOTROM_ATTR 0x1D 356 357/* Internal Units Sync Barrier Control Register */ 358#define MV_SYNC_BARRIER_CTRL 0x84 359#define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF 360#endif 361 362#define WIN_REG_IDX_RD(pre,reg,off,base) \ 363 static __inline uint32_t \ 364 pre ## _ ## reg ## _read(int i) \ 365 { \ 366 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 367 } 368 369#define WIN_REG_IDX_RD2(pre,reg,off,base) \ 370 static __inline uint32_t \ 371 pre ## _ ## reg ## _read(int i, int j) \ 372 { \ 373 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 374 } \ 375 376#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 377 static __inline uint32_t \ 378 pre ## _ ## reg ## _read(uint32_t base, int i) \ 379 { \ 380 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 381 } 382 383#define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 384 static __inline uint32_t \ 385 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 386 { \ 387 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 388 } 389 390#define WIN_REG_IDX_WR(pre,reg,off,base) \ 391 static __inline void \ 392 pre ## _ ## reg ## _write(int i, uint32_t val) \ 393 { \ 394 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 395 } 396 397#define WIN_REG_IDX_WR2(pre,reg,off,base) \ 398 static __inline void \ 399 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 400 { \ 401 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 402 } 403 404#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 405 static __inline void \ 406 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 407 { \ 408 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 409 } 410 411#define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 412 static __inline void \ 413 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 414 { \ 415 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 416 } 417 418#define WIN_REG_RD(pre,reg,off,base) \ 419 static __inline uint32_t \ 420 pre ## _ ## reg ## _read(void) \ 421 { \ 422 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 423 } 424 425#define WIN_REG_BASE_RD(pre,reg,off) \ 426 static __inline uint32_t \ 427 pre ## _ ## reg ## _read(uint32_t base) \ 428 { \ 429 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 430 } 431 432#define WIN_REG_WR(pre,reg,off,base) \ 433 static __inline void \ 434 pre ## _ ## reg ## _write(uint32_t val) \ 435 { \ 436 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 437 } 438 439#define WIN_REG_BASE_WR(pre,reg,off) \ 440 static __inline void \ 441 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 442 { \ 443 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 444 } 445 446#endif /* _MVWIN_H_ */ 447