hifn7751reg.h revision 330897
1/* $FreeBSD: stable/11/sys/dev/hifn/hifn7751reg.h 330897 2018-03-14 03:19:51Z eadler $ */ 2/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ 3 4/*- 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Invertex AEON / Hifn 7751 driver 8 * Copyright (c) 1999 Invertex Inc. All rights reserved. 9 * Copyright (c) 1999 Theo de Raadt 10 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 11 * http://www.netsec.net 12 * 13 * Please send any comments, feedback, bug-fixes, or feature requests to 14 * software@invertex.com. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. The name of the author may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 31 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 32 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 34 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 38 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Effort sponsored in part by the Defense Advanced Research Projects 41 * Agency (DARPA) and Air Force Research Laboratory, Air Force 42 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 43 * 44 */ 45#ifndef __HIFN_H__ 46#define __HIFN_H__ 47 48#include <sys/endian.h> 49 50/* 51 * Some PCI configuration space offset defines. The names were made 52 * identical to the names used by the Linux kernel. 53 */ 54#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ 55#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ 56#define HIFN_TRDY_TIMEOUT 0x40 57#define HIFN_RETRY_TIMEOUT 0x41 58 59/* 60 * PCI vendor and device identifiers 61 * (the names are preserved from their OpenBSD source). 62 */ 63#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ 64#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ 65#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ 66#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ 67#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ 68#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ 69#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ 70 71#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ 72#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ 73 74#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ 75#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ 76 77/* 78 * The values below should multiple of 4 -- and be large enough to handle 79 * any command the driver implements. 80 * 81 * MAX_COMMAND = base command + mac command + encrypt command + 82 * mac-key + rc4-key 83 * MAX_RESULT = base result + mac result + mac + encrypt result 84 * 85 * 86 */ 87#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) 88#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) 89 90/* 91 * hifn_desc_t 92 * 93 * Holds an individual descriptor for any of the rings. 94 */ 95typedef struct hifn_desc { 96 volatile u_int32_t l; /* length and status bits */ 97 volatile u_int32_t p; 98} hifn_desc_t; 99 100/* 101 * Masks for the "length" field of struct hifn_desc. 102 */ 103#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ 104#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ 105#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ 106#define HIFN_D_OVER 0x08000000 /* overflow */ 107#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ 108#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ 109#define HIFN_D_VALID 0x80000000 /* valid bit */ 110 111 112/* 113 * Processing Unit Registers (offset from BASEREG0) 114 */ 115#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ 116#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ 117#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ 118#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ 119#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ 120#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ 121#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ 122#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ 123#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ 124#define HIFN_0_MUTE1 0x80 125#define HIFN_0_MUTE2 0x90 126#define HIFN_0_SPACESIZE 0x100 /* Register space size */ 127 128/* Processing Unit Control Register (HIFN_0_PUCTRL) */ 129#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ 130#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ 131#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ 132#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ 133#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ 134 135/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ 136#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ 137#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ 138#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 139#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 140#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ 141#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ 142#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ 143#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ 144#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ 145#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ 146 147/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ 148#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ 149#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ 150#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ 151#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ 152#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ 153#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ 154#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ 155#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ 156#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ 157#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ 158#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ 159#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ 160#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ 161#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ 162#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ 163#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ 164#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ 165#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ 166#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ 167#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ 168#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ 169#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ 170#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ 171 172/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ 173#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ 174#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ 175#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 176#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 177#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ 178#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ 179#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ 180#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ 181#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ 182#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ 183 184/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ 185#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ 186#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ 187#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 188#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 189#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ 190#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ 191#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ 192#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ 193#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ 194#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ 195#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ 196#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ 197#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ 198#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ 199#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ 200#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ 201#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ 202 203/* FIFO Status Register (HIFN_0_FIFOSTAT) */ 204#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ 205#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ 206 207/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ 208#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ 209 210/* 211 * DMA Interface Registers (offset from BASEREG1) 212 */ 213#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ 214#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ 215#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ 216#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ 217#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ 218#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ 219#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ 220#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ 221#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ 222#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ 223#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ 224#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ 225#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ 226#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ 227#define HIFN_1_REVID 0x98 /* Revision ID */ 228 229#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ 230#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ 231#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ 232#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ 233#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ 234#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ 235#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ 236#define HIFN_1_RNG_DATA 0x318 /* RNG data */ 237#define HIFN_1_PUB_MODE 0x320 /* PK mode */ 238#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ 239#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ 240#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ 241#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ 242 243/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ 244#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ 245#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ 246#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ 247#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ 248#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ 249#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ 250#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ 251#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ 252#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ 253#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ 254#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ 255#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ 256#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ 257#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 258#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ 259#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ 260#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ 261#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ 262#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ 263#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ 264#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ 265#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ 266#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 267#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ 268#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ 269#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ 270#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ 271#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ 272#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ 273#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ 274#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ 275#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ 276#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 277#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ 278#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ 279#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ 280#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ 281#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ 282 283/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ 284#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ 285#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ 286#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ 287#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ 288#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ 289#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 290#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ 291#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ 292#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ 293#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ 294#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 295#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ 296#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ 297#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ 298#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ 299#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ 300#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 301#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ 302#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ 303#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ 304#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ 305#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ 306 307/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ 308#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ 309#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ 310#define HIFN_DMACNFG_UNLOCK 0x00000800 311#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ 312#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ 313#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ 314#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ 315#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ 316 317/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ 318#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ 319#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ 320#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ 321#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ 322#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 323#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 324#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 325#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 326 327/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ 328#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ 329 330/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ 331#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ 332#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ 333#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ 334 335/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ 336#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ 337#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ 338 339/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ 340#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ 341#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ 342#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ 343#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ 344#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ 345#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ 346#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ 347#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ 348#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ 349 350/* Public key reset register (HIFN_1_PUB_RESET) */ 351#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ 352 353/* Public operation register (HIFN_1_PUB_OP) */ 354#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ 355#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ 356#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ 357#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ 358#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ 359#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ 360#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ 361#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ 362#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ 363#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ 364#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ 365#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ 366#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ 367#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ 368#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ 369#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ 370#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ 371 372/* Public operand length register (HIFN_1_PUB_OPLEN) */ 373#define HIFN_PUBOPLEN_MODLEN 0x0000007f 374#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 375#define HIFN_PUBOPLEN_REDLEN 0x003c0000 376 377/* Public status register (HIFN_1_PUB_STATUS) */ 378#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ 379#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ 380#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ 381#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ 382#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ 383#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ 384#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ 385 386/* Public interrupt enable register (HIFN_1_PUB_IEN) */ 387#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ 388 389/* Random number generator config register (HIFN_1_RNG_CONFIG) */ 390#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ 391 392/* 393 * Register offsets in register set 1 394 */ 395 396#define HIFN_UNLOCK_SECRET1 0xf4 397#define HIFN_UNLOCK_SECRET2 0xfc 398 399/* 400 * PLL config register 401 * 402 * This register is present only on 7954/7955/7956 parts. It must be 403 * programmed according to the bus interface method used by the h/w. 404 * Note that the parts require a stable clock. Since the PCI clock 405 * may vary the reference clock must usually be used. To avoid 406 * overclocking the core logic, setup must be done carefully, refer 407 * to the driver for details. The exact multiplier required varies 408 * by part and system configuration; refer to the Hifn documentation. 409 */ 410#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ 411#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ 412/* bit 2 reserved */ 413#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ 414#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ 415/* bits 5-9 reserved */ 416#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ 417#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ 418#define HIFN_PLL_ND_SHIFT 11 419#define HIFN_PLL_ND_2 0x00000000 /* 2x */ 420#define HIFN_PLL_ND_4 0x00000800 /* 4x */ 421#define HIFN_PLL_ND_6 0x00001000 /* 6x */ 422#define HIFN_PLL_ND_8 0x00001800 /* 8x */ 423#define HIFN_PLL_ND_10 0x00002000 /* 10x */ 424#define HIFN_PLL_ND_12 0x00002800 /* 12x */ 425/* bits 14-15 reserved */ 426#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ 427/* bits 17-31 reserved */ 428 429/* 430 * Board configuration specifies only these bits. 431 */ 432#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) 433 434/* 435 * Public Key Engine Mode Register 436 */ 437#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ 438#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ 439 440 441/********************************************************************* 442 * Structs for board commands 443 * 444 *********************************************************************/ 445 446/* 447 * Structure to help build up the command data structure. 448 */ 449typedef struct hifn_base_command { 450 volatile u_int16_t masks; 451 volatile u_int16_t session_num; 452 volatile u_int16_t total_source_count; 453 volatile u_int16_t total_dest_count; 454} hifn_base_command_t; 455 456#define HIFN_BASE_CMD_MAC 0x0400 457#define HIFN_BASE_CMD_CRYPT 0x0800 458#define HIFN_BASE_CMD_DECODE 0x2000 459#define HIFN_BASE_CMD_SRCLEN_M 0xc000 460#define HIFN_BASE_CMD_SRCLEN_S 14 461#define HIFN_BASE_CMD_DSTLEN_M 0x3000 462#define HIFN_BASE_CMD_DSTLEN_S 12 463#define HIFN_BASE_CMD_LENMASK_HI 0x30000 464#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff 465 466/* 467 * Structure to help build up the command data structure. 468 */ 469typedef struct hifn_crypt_command { 470 volatile u_int16_t masks; 471 volatile u_int16_t header_skip; 472 volatile u_int16_t source_count; 473 volatile u_int16_t reserved; 474} hifn_crypt_command_t; 475 476#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ 477#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ 478#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ 479#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ 480#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ 481#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ 482#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ 483#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ 484#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ 485#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ 486#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ 487#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ 488#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ 489 490#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 491#define HIFN_CRYPT_CMD_SRCLEN_S 14 492 493#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ 494#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ 495#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ 496#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ 497 498/* 499 * Structure to help build up the command data structure. 500 */ 501typedef struct hifn_mac_command { 502 volatile u_int16_t masks; 503 volatile u_int16_t header_skip; 504 volatile u_int16_t source_count; 505 volatile u_int16_t reserved; 506} hifn_mac_command_t; 507 508#define HIFN_MAC_CMD_ALG_MASK 0x0001 509#define HIFN_MAC_CMD_ALG_SHA1 0x0000 510#define HIFN_MAC_CMD_ALG_MD5 0x0001 511#define HIFN_MAC_CMD_MODE_MASK 0x000c 512#define HIFN_MAC_CMD_MODE_HMAC 0x0000 513#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 514#define HIFN_MAC_CMD_MODE_HASH 0x0008 515#define HIFN_MAC_CMD_MODE_FULL 0x0004 516#define HIFN_MAC_CMD_TRUNC 0x0010 517#define HIFN_MAC_CMD_RESULT 0x0020 518#define HIFN_MAC_CMD_APPEND 0x0040 519#define HIFN_MAC_CMD_SRCLEN_M 0xc000 520#define HIFN_MAC_CMD_SRCLEN_S 14 521 522/* 523 * MAC POS IPsec initiates authentication after encryption on encodes 524 * and before decryption on decodes. 525 */ 526#define HIFN_MAC_CMD_POS_IPSEC 0x0200 527#define HIFN_MAC_CMD_NEW_KEY 0x0800 528 529/* 530 * The poll frequency and poll scalar defines are unshifted values used 531 * to set fields in the DMA Configuration Register. 532 */ 533#ifndef HIFN_POLL_FREQUENCY 534#define HIFN_POLL_FREQUENCY 0x1 535#endif 536 537#ifndef HIFN_POLL_SCALAR 538#define HIFN_POLL_SCALAR 0x0 539#endif 540 541#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ 542#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ 543#endif /* __HIFN_H__ */ 544