machdep.c revision 317004
1/* $NetBSD: arm32_machdep.c,v 1.44 2004/03/24 15:34:47 atatat Exp $ */ 2 3/*- 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 1994-1998 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Mark Brinicombe 22 * for the NetBSD Project. 23 * 4. The name of the company nor the name of the author may be used to 24 * endorse or promote products derived from this software without specific 25 * prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * Machine dependent functions for kernel setup 40 * 41 * Created : 17/09/94 42 * Updated : 18/04/01 updated for new wscons 43 */ 44 45#include "opt_compat.h" 46#include "opt_ddb.h" 47#include "opt_kstack_pages.h" 48#include "opt_platform.h" 49#include "opt_sched.h" 50#include "opt_timer.h" 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD: stable/11/sys/arm/arm/machdep.c 317004 2017-04-16 07:21:20Z mmel $"); 54 55#include <sys/param.h> 56#include <sys/buf.h> 57#include <sys/bus.h> 58#include <sys/cons.h> 59#include <sys/cpu.h> 60#include <sys/devmap.h> 61#include <sys/efi.h> 62#include <sys/imgact.h> 63#include <sys/kdb.h> 64#include <sys/kernel.h> 65#include <sys/linker.h> 66#include <sys/msgbuf.h> 67#include <sys/rwlock.h> 68#include <sys/sched.h> 69#include <sys/syscallsubr.h> 70#include <sys/sysent.h> 71#include <sys/sysproto.h> 72 73#include <vm/vm_object.h> 74#include <vm/vm_page.h> 75#include <vm/vm_pager.h> 76 77#include <machine/debug_monitor.h> 78#include <machine/machdep.h> 79#include <machine/metadata.h> 80#include <machine/pcb.h> 81#include <machine/physmem.h> 82#include <machine/platform.h> 83#include <machine/sysarch.h> 84#include <machine/undefined.h> 85#include <machine/vfp.h> 86#include <machine/vmparam.h> 87 88#ifdef FDT 89#include <dev/fdt/fdt_common.h> 90#include <machine/ofw_machdep.h> 91#endif 92 93#ifdef DEBUG 94#define debugf(fmt, args...) printf(fmt, ##args) 95#else 96#define debugf(fmt, args...) 97#endif 98 99#if defined(COMPAT_FREEBSD4) || defined(COMPAT_FREEBSD5) || \ 100 defined(COMPAT_FREEBSD6) || defined(COMPAT_FREEBSD7) || \ 101 defined(COMPAT_FREEBSD9) 102#error FreeBSD/arm doesn't provide compatibility with releases prior to 10 103#endif 104 105struct pcpu __pcpu[MAXCPU]; 106struct pcpu *pcpup = &__pcpu[0]; 107 108static struct trapframe proc0_tf; 109uint32_t cpu_reset_address = 0; 110int cold = 1; 111vm_offset_t vector_page; 112 113int (*_arm_memcpy)(void *, void *, int, int) = NULL; 114int (*_arm_bzero)(void *, int, int) = NULL; 115int _min_memcpy_size = 0; 116int _min_bzero_size = 0; 117 118extern int *end; 119 120#ifdef FDT 121vm_paddr_t pmap_pa; 122#if __ARM_ARCH >= 6 123vm_offset_t systempage; 124vm_offset_t irqstack; 125vm_offset_t undstack; 126vm_offset_t abtstack; 127#else 128/* 129 * This is the number of L2 page tables required for covering max 130 * (hypothetical) memsize of 4GB and all kernel mappings (vectors, msgbuf, 131 * stacks etc.), uprounded to be divisible by 4. 132 */ 133#define KERNEL_PT_MAX 78 134static struct pv_addr kernel_pt_table[KERNEL_PT_MAX]; 135struct pv_addr systempage; 136static struct pv_addr msgbufpv; 137struct pv_addr irqstack; 138struct pv_addr undstack; 139struct pv_addr abtstack; 140static struct pv_addr kernelstack; 141#endif /* __ARM_ARCH >= 6 */ 142#endif /* FDT */ 143 144#ifdef MULTIDELAY 145static delay_func *delay_impl; 146static void *delay_arg; 147#endif 148 149void 150sendsig(catcher, ksi, mask) 151 sig_t catcher; 152 ksiginfo_t *ksi; 153 sigset_t *mask; 154{ 155 struct thread *td; 156 struct proc *p; 157 struct trapframe *tf; 158 struct sigframe *fp, frame; 159 struct sigacts *psp; 160 struct sysentvec *sysent; 161 int onstack; 162 int sig; 163 int code; 164 165 td = curthread; 166 p = td->td_proc; 167 PROC_LOCK_ASSERT(p, MA_OWNED); 168 sig = ksi->ksi_signo; 169 code = ksi->ksi_code; 170 psp = p->p_sigacts; 171 mtx_assert(&psp->ps_mtx, MA_OWNED); 172 tf = td->td_frame; 173 onstack = sigonstack(tf->tf_usr_sp); 174 175 CTR4(KTR_SIG, "sendsig: td=%p (%s) catcher=%p sig=%d", td, p->p_comm, 176 catcher, sig); 177 178 /* Allocate and validate space for the signal handler context. */ 179 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !(onstack) && 180 SIGISMEMBER(psp->ps_sigonstack, sig)) { 181 fp = (struct sigframe *)((uintptr_t)td->td_sigstk.ss_sp + 182 td->td_sigstk.ss_size); 183#if defined(COMPAT_43) 184 td->td_sigstk.ss_flags |= SS_ONSTACK; 185#endif 186 } else 187 fp = (struct sigframe *)td->td_frame->tf_usr_sp; 188 189 /* make room on the stack */ 190 fp--; 191 192 /* make the stack aligned */ 193 fp = (struct sigframe *)STACKALIGN(fp); 194 /* Populate the siginfo frame. */ 195 get_mcontext(td, &frame.sf_uc.uc_mcontext, 0); 196 frame.sf_si = ksi->ksi_info; 197 frame.sf_uc.uc_sigmask = *mask; 198 frame.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK ) 199 ? ((onstack) ? SS_ONSTACK : 0) : SS_DISABLE; 200 frame.sf_uc.uc_stack = td->td_sigstk; 201 mtx_unlock(&psp->ps_mtx); 202 PROC_UNLOCK(td->td_proc); 203 204 /* Copy the sigframe out to the user's stack. */ 205 if (copyout(&frame, fp, sizeof(*fp)) != 0) { 206 /* Process has trashed its stack. Kill it. */ 207 CTR2(KTR_SIG, "sendsig: sigexit td=%p fp=%p", td, fp); 208 PROC_LOCK(p); 209 sigexit(td, SIGILL); 210 } 211 212 /* 213 * Build context to run handler in. We invoke the handler 214 * directly, only returning via the trampoline. Note the 215 * trampoline version numbers are coordinated with machine- 216 * dependent code in libc. 217 */ 218 219 tf->tf_r0 = sig; 220 tf->tf_r1 = (register_t)&fp->sf_si; 221 tf->tf_r2 = (register_t)&fp->sf_uc; 222 223 /* the trampoline uses r5 as the uc address */ 224 tf->tf_r5 = (register_t)&fp->sf_uc; 225 tf->tf_pc = (register_t)catcher; 226 tf->tf_usr_sp = (register_t)fp; 227 sysent = p->p_sysent; 228 if (sysent->sv_sigcode_base != 0) 229 tf->tf_usr_lr = (register_t)sysent->sv_sigcode_base; 230 else 231 tf->tf_usr_lr = (register_t)(sysent->sv_psstrings - 232 *(sysent->sv_szsigcode)); 233 /* Set the mode to enter in the signal handler */ 234#if __ARM_ARCH >= 7 235 if ((register_t)catcher & 1) 236 tf->tf_spsr |= PSR_T; 237 else 238 tf->tf_spsr &= ~PSR_T; 239#endif 240 241 CTR3(KTR_SIG, "sendsig: return td=%p pc=%#x sp=%#x", td, tf->tf_usr_lr, 242 tf->tf_usr_sp); 243 244 PROC_LOCK(p); 245 mtx_lock(&psp->ps_mtx); 246} 247 248struct kva_md_info kmi; 249 250/* 251 * arm32_vector_init: 252 * 253 * Initialize the vector page, and select whether or not to 254 * relocate the vectors. 255 * 256 * NOTE: We expect the vector page to be mapped at its expected 257 * destination. 258 */ 259 260extern unsigned int page0[], page0_data[]; 261void 262arm_vector_init(vm_offset_t va, int which) 263{ 264 unsigned int *vectors = (int *) va; 265 unsigned int *vectors_data = vectors + (page0_data - page0); 266 int vec; 267 268 /* 269 * Loop through the vectors we're taking over, and copy the 270 * vector's insn and data word. 271 */ 272 for (vec = 0; vec < ARM_NVEC; vec++) { 273 if ((which & (1 << vec)) == 0) { 274 /* Don't want to take over this vector. */ 275 continue; 276 } 277 vectors[vec] = page0[vec]; 278 vectors_data[vec] = page0_data[vec]; 279 } 280 281 /* Now sync the vectors. */ 282 icache_sync(va, (ARM_NVEC * 2) * sizeof(u_int)); 283 284 vector_page = va; 285#if __ARM_ARCH < 6 286 if (va == ARM_VECTORS_HIGH) { 287 /* 288 * Enable high vectors in the system control reg (SCTLR). 289 * 290 * Assume the MD caller knows what it's doing here, and really 291 * does want the vector page relocated. 292 * 293 * Note: This has to be done here (and not just in 294 * cpu_setup()) because the vector page needs to be 295 * accessible *before* cpu_startup() is called. 296 * Think ddb(9) ... 297 */ 298 cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC); 299 } 300#endif 301} 302 303static void 304cpu_startup(void *dummy) 305{ 306 struct pcb *pcb = thread0.td_pcb; 307 const unsigned int mbyte = 1024 * 1024; 308#if __ARM_ARCH < 6 && !defined(ARM_CACHE_LOCK_ENABLE) 309 vm_page_t m; 310#endif 311 312 identify_arm_cpu(); 313 314 vm_ksubmap_init(&kmi); 315 316 /* 317 * Display the RAM layout. 318 */ 319 printf("real memory = %ju (%ju MB)\n", 320 (uintmax_t)arm32_ptob(realmem), 321 (uintmax_t)arm32_ptob(realmem) / mbyte); 322 printf("avail memory = %ju (%ju MB)\n", 323 (uintmax_t)arm32_ptob(vm_cnt.v_free_count), 324 (uintmax_t)arm32_ptob(vm_cnt.v_free_count) / mbyte); 325 if (bootverbose) { 326 arm_physmem_print_tables(); 327 devmap_print_table(); 328 } 329 330 bufinit(); 331 vm_pager_bufferinit(); 332 pcb->pcb_regs.sf_sp = (u_int)thread0.td_kstack + 333 USPACE_SVC_STACK_TOP; 334 pmap_set_pcb_pagedir(kernel_pmap, pcb); 335#if __ARM_ARCH < 6 336 vector_page_setprot(VM_PROT_READ); 337 pmap_postinit(); 338#ifdef ARM_CACHE_LOCK_ENABLE 339 pmap_kenter_user(ARM_TP_ADDRESS, ARM_TP_ADDRESS); 340 arm_lock_cache_line(ARM_TP_ADDRESS); 341#else 342 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_ZERO); 343 pmap_kenter_user(ARM_TP_ADDRESS, VM_PAGE_TO_PHYS(m)); 344#endif 345 *(uint32_t *)ARM_RAS_START = 0; 346 *(uint32_t *)ARM_RAS_END = 0xffffffff; 347#endif 348} 349 350SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 351 352/* 353 * Flush the D-cache for non-DMA I/O so that the I-cache can 354 * be made coherent later. 355 */ 356void 357cpu_flush_dcache(void *ptr, size_t len) 358{ 359 360 dcache_wb_poc((vm_offset_t)ptr, (vm_paddr_t)vtophys(ptr), len); 361} 362 363/* Get current clock frequency for the given cpu id. */ 364int 365cpu_est_clockrate(int cpu_id, uint64_t *rate) 366{ 367 368 return (ENXIO); 369} 370 371void 372cpu_idle(int busy) 373{ 374 375 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", busy, curcpu); 376 spinlock_enter(); 377#ifndef NO_EVENTTIMERS 378 if (!busy) 379 cpu_idleclock(); 380#endif 381 if (!sched_runnable()) 382 cpu_sleep(0); 383#ifndef NO_EVENTTIMERS 384 if (!busy) 385 cpu_activeclock(); 386#endif 387 spinlock_exit(); 388 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", busy, curcpu); 389} 390 391int 392cpu_idle_wakeup(int cpu) 393{ 394 395 return (0); 396} 397 398/* 399 * Most ARM platforms don't need to do anything special to init their clocks 400 * (they get intialized during normal device attachment), and by not defining a 401 * cpu_initclocks() function they get this generic one. Any platform that needs 402 * to do something special can just provide their own implementation, which will 403 * override this one due to the weak linkage. 404 */ 405void 406arm_generic_initclocks(void) 407{ 408 409#ifndef NO_EVENTTIMERS 410#ifdef SMP 411 if (PCPU_GET(cpuid) == 0) 412 cpu_initclocks_bsp(); 413 else 414 cpu_initclocks_ap(); 415#else 416 cpu_initclocks_bsp(); 417#endif 418#endif 419} 420__weak_reference(arm_generic_initclocks, cpu_initclocks); 421 422#ifdef MULTIDELAY 423void 424arm_set_delay(delay_func *impl, void *arg) 425{ 426 427 KASSERT(impl != NULL, ("No DELAY implementation")); 428 delay_impl = impl; 429 delay_arg = arg; 430} 431 432void 433DELAY(int usec) 434{ 435 436 delay_impl(usec, delay_arg); 437} 438#endif 439 440void 441cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 442{ 443} 444 445void 446spinlock_enter(void) 447{ 448 struct thread *td; 449 register_t cspr; 450 451 td = curthread; 452 if (td->td_md.md_spinlock_count == 0) { 453 cspr = disable_interrupts(PSR_I | PSR_F); 454 td->td_md.md_spinlock_count = 1; 455 td->td_md.md_saved_cspr = cspr; 456 } else 457 td->td_md.md_spinlock_count++; 458 critical_enter(); 459} 460 461void 462spinlock_exit(void) 463{ 464 struct thread *td; 465 register_t cspr; 466 467 td = curthread; 468 critical_exit(); 469 cspr = td->td_md.md_saved_cspr; 470 td->td_md.md_spinlock_count--; 471 if (td->td_md.md_spinlock_count == 0) 472 restore_interrupts(cspr); 473} 474 475/* 476 * Clear registers on exec 477 */ 478void 479exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 480{ 481 struct trapframe *tf = td->td_frame; 482 483 memset(tf, 0, sizeof(*tf)); 484 tf->tf_usr_sp = stack; 485 tf->tf_usr_lr = imgp->entry_addr; 486 tf->tf_svc_lr = 0x77777777; 487 tf->tf_pc = imgp->entry_addr; 488 tf->tf_spsr = PSR_USR32_MODE; 489} 490 491/* 492 * Get machine context. 493 */ 494int 495get_mcontext(struct thread *td, mcontext_t *mcp, int clear_ret) 496{ 497 struct trapframe *tf = td->td_frame; 498 __greg_t *gr = mcp->__gregs; 499 500 if (clear_ret & GET_MC_CLEAR_RET) { 501 gr[_REG_R0] = 0; 502 gr[_REG_CPSR] = tf->tf_spsr & ~PSR_C; 503 } else { 504 gr[_REG_R0] = tf->tf_r0; 505 gr[_REG_CPSR] = tf->tf_spsr; 506 } 507 gr[_REG_R1] = tf->tf_r1; 508 gr[_REG_R2] = tf->tf_r2; 509 gr[_REG_R3] = tf->tf_r3; 510 gr[_REG_R4] = tf->tf_r4; 511 gr[_REG_R5] = tf->tf_r5; 512 gr[_REG_R6] = tf->tf_r6; 513 gr[_REG_R7] = tf->tf_r7; 514 gr[_REG_R8] = tf->tf_r8; 515 gr[_REG_R9] = tf->tf_r9; 516 gr[_REG_R10] = tf->tf_r10; 517 gr[_REG_R11] = tf->tf_r11; 518 gr[_REG_R12] = tf->tf_r12; 519 gr[_REG_SP] = tf->tf_usr_sp; 520 gr[_REG_LR] = tf->tf_usr_lr; 521 gr[_REG_PC] = tf->tf_pc; 522 523 return (0); 524} 525 526/* 527 * Set machine context. 528 * 529 * However, we don't set any but the user modifiable flags, and we won't 530 * touch the cs selector. 531 */ 532int 533set_mcontext(struct thread *td, mcontext_t *mcp) 534{ 535 struct trapframe *tf = td->td_frame; 536 const __greg_t *gr = mcp->__gregs; 537 538 tf->tf_r0 = gr[_REG_R0]; 539 tf->tf_r1 = gr[_REG_R1]; 540 tf->tf_r2 = gr[_REG_R2]; 541 tf->tf_r3 = gr[_REG_R3]; 542 tf->tf_r4 = gr[_REG_R4]; 543 tf->tf_r5 = gr[_REG_R5]; 544 tf->tf_r6 = gr[_REG_R6]; 545 tf->tf_r7 = gr[_REG_R7]; 546 tf->tf_r8 = gr[_REG_R8]; 547 tf->tf_r9 = gr[_REG_R9]; 548 tf->tf_r10 = gr[_REG_R10]; 549 tf->tf_r11 = gr[_REG_R11]; 550 tf->tf_r12 = gr[_REG_R12]; 551 tf->tf_usr_sp = gr[_REG_SP]; 552 tf->tf_usr_lr = gr[_REG_LR]; 553 tf->tf_pc = gr[_REG_PC]; 554 tf->tf_spsr = gr[_REG_CPSR]; 555 556 return (0); 557} 558 559int 560sys_sigreturn(td, uap) 561 struct thread *td; 562 struct sigreturn_args /* { 563 const struct __ucontext *sigcntxp; 564 } */ *uap; 565{ 566 ucontext_t uc; 567 int spsr; 568 569 if (uap == NULL) 570 return (EFAULT); 571 if (copyin(uap->sigcntxp, &uc, sizeof(uc))) 572 return (EFAULT); 573 /* 574 * Make sure the processor mode has not been tampered with and 575 * interrupts have not been disabled. 576 */ 577 spsr = uc.uc_mcontext.__gregs[_REG_CPSR]; 578 if ((spsr & PSR_MODE) != PSR_USR32_MODE || 579 (spsr & (PSR_I | PSR_F)) != 0) 580 return (EINVAL); 581 /* Restore register context. */ 582 set_mcontext(td, &uc.uc_mcontext); 583 584 /* Restore signal mask. */ 585 kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0); 586 587 return (EJUSTRETURN); 588} 589 590/* 591 * Construct a PCB from a trapframe. This is called from kdb_trap() where 592 * we want to start a backtrace from the function that caused us to enter 593 * the debugger. We have the context in the trapframe, but base the trace 594 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 595 * enough for a backtrace. 596 */ 597void 598makectx(struct trapframe *tf, struct pcb *pcb) 599{ 600 pcb->pcb_regs.sf_r4 = tf->tf_r4; 601 pcb->pcb_regs.sf_r5 = tf->tf_r5; 602 pcb->pcb_regs.sf_r6 = tf->tf_r6; 603 pcb->pcb_regs.sf_r7 = tf->tf_r7; 604 pcb->pcb_regs.sf_r8 = tf->tf_r8; 605 pcb->pcb_regs.sf_r9 = tf->tf_r9; 606 pcb->pcb_regs.sf_r10 = tf->tf_r10; 607 pcb->pcb_regs.sf_r11 = tf->tf_r11; 608 pcb->pcb_regs.sf_r12 = tf->tf_r12; 609 pcb->pcb_regs.sf_pc = tf->tf_pc; 610 pcb->pcb_regs.sf_lr = tf->tf_usr_lr; 611 pcb->pcb_regs.sf_sp = tf->tf_usr_sp; 612} 613 614void 615pcpu0_init(void) 616{ 617#if __ARM_ARCH >= 6 618 set_curthread(&thread0); 619#endif 620 pcpu_init(pcpup, 0, sizeof(struct pcpu)); 621 PCPU_SET(curthread, &thread0); 622} 623 624/* 625 * Initialize proc0 626 */ 627void 628init_proc0(vm_offset_t kstack) 629{ 630 proc_linkup0(&proc0, &thread0); 631 thread0.td_kstack = kstack; 632 thread0.td_pcb = (struct pcb *) 633 (thread0.td_kstack + kstack_pages * PAGE_SIZE) - 1; 634 thread0.td_pcb->pcb_flags = 0; 635 thread0.td_pcb->pcb_vfpcpu = -1; 636 thread0.td_pcb->pcb_vfpstate.fpscr = VFPSCR_DN; 637 thread0.td_frame = &proc0_tf; 638 pcpup->pc_curpcb = thread0.td_pcb; 639} 640 641#if __ARM_ARCH >= 6 642void 643set_stackptrs(int cpu) 644{ 645 646 set_stackptr(PSR_IRQ32_MODE, 647 irqstack + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 648 set_stackptr(PSR_ABT32_MODE, 649 abtstack + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 650 set_stackptr(PSR_UND32_MODE, 651 undstack + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 652} 653#else 654void 655set_stackptrs(int cpu) 656{ 657 658 set_stackptr(PSR_IRQ32_MODE, 659 irqstack.pv_va + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 660 set_stackptr(PSR_ABT32_MODE, 661 abtstack.pv_va + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 662 set_stackptr(PSR_UND32_MODE, 663 undstack.pv_va + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 664} 665#endif 666 667 668#ifdef FDT 669#if __ARM_ARCH < 6 670void * 671initarm(struct arm_boot_params *abp) 672{ 673 struct mem_region mem_regions[FDT_MEM_REGIONS]; 674 struct pv_addr kernel_l1pt; 675 struct pv_addr dpcpu; 676 vm_offset_t dtbp, freemempos, l2_start, lastaddr; 677 uint64_t memsize; 678 uint32_t l2size; 679 char *env; 680 void *kmdp; 681 u_int l1pagetable; 682 int i, j, err_devmap, mem_regions_sz; 683 684 lastaddr = parse_boot_param(abp); 685 arm_physmem_kernaddr = abp->abp_physaddr; 686 687 memsize = 0; 688 689 cpuinfo_init(); 690 set_cpufuncs(); 691 692 /* 693 * Find the dtb passed in by the boot loader. 694 */ 695 kmdp = preload_search_by_type("elf kernel"); 696 if (kmdp != NULL) 697 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t); 698 else 699 dtbp = (vm_offset_t)NULL; 700 701#if defined(FDT_DTB_STATIC) 702 /* 703 * In case the device tree blob was not retrieved (from metadata) try 704 * to use the statically embedded one. 705 */ 706 if (dtbp == (vm_offset_t)NULL) 707 dtbp = (vm_offset_t)&fdt_static_dtb; 708#endif 709 710 if (OF_install(OFW_FDT, 0) == FALSE) 711 panic("Cannot install FDT"); 712 713 if (OF_init((void *)dtbp) != 0) 714 panic("OF_init failed with the found device tree"); 715 716 /* Grab physical memory regions information from device tree. */ 717 if (fdt_get_mem_regions(mem_regions, &mem_regions_sz, &memsize) != 0) 718 panic("Cannot get physical memory regions"); 719 arm_physmem_hardware_regions(mem_regions, mem_regions_sz); 720 721 /* Grab reserved memory regions information from device tree. */ 722 if (fdt_get_reserved_regions(mem_regions, &mem_regions_sz) == 0) 723 arm_physmem_exclude_regions(mem_regions, mem_regions_sz, 724 EXFLAG_NODUMP | EXFLAG_NOALLOC); 725 726 /* Platform-specific initialisation */ 727 platform_probe_and_attach(); 728 729 pcpu0_init(); 730 731 /* Do basic tuning, hz etc */ 732 init_param1(); 733 734 /* Calculate number of L2 tables needed for mapping vm_page_array */ 735 l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page); 736 l2size = (l2size >> L1_S_SHIFT) + 1; 737 738 /* 739 * Add one table for end of kernel map, one for stacks, msgbuf and 740 * L1 and L2 tables map and one for vectors map. 741 */ 742 l2size += 3; 743 744 /* Make it divisible by 4 */ 745 l2size = (l2size + 3) & ~3; 746 747 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; 748 749 /* Define a macro to simplify memory allocation */ 750#define valloc_pages(var, np) \ 751 alloc_pages((var).pv_va, (np)); \ 752 (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR); 753 754#define alloc_pages(var, np) \ 755 (var) = freemempos; \ 756 freemempos += (np * PAGE_SIZE); \ 757 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 758 759 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 760 freemempos += PAGE_SIZE; 761 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 762 763 for (i = 0, j = 0; i < l2size; ++i) { 764 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 765 valloc_pages(kernel_pt_table[i], 766 L2_TABLE_SIZE / PAGE_SIZE); 767 j = i; 768 } else { 769 kernel_pt_table[i].pv_va = kernel_pt_table[j].pv_va + 770 L2_TABLE_SIZE_REAL * (i - j); 771 kernel_pt_table[i].pv_pa = 772 kernel_pt_table[i].pv_va - KERNVIRTADDR + 773 abp->abp_physaddr; 774 775 } 776 } 777 /* 778 * Allocate a page for the system page mapped to 0x00000000 779 * or 0xffff0000. This page will just contain the system vectors 780 * and can be shared by all processes. 781 */ 782 valloc_pages(systempage, 1); 783 784 /* Allocate dynamic per-cpu area. */ 785 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 786 dpcpu_init((void *)dpcpu.pv_va, 0); 787 788 /* Allocate stacks for all modes */ 789 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU); 790 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU); 791 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU); 792 valloc_pages(kernelstack, kstack_pages * MAXCPU); 793 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 794 795 /* 796 * Now we start construction of the L1 page table 797 * We start by mapping the L2 page tables into the L1. 798 * This means that we can replace L1 mappings later on if necessary 799 */ 800 l1pagetable = kernel_l1pt.pv_va; 801 802 /* 803 * Try to map as much as possible of kernel text and data using 804 * 1MB section mapping and for the rest of initial kernel address 805 * space use L2 coarse tables. 806 * 807 * Link L2 tables for mapping remainder of kernel (modulo 1MB) 808 * and kernel structures 809 */ 810 l2_start = lastaddr & ~(L1_S_OFFSET); 811 for (i = 0 ; i < l2size - 1; i++) 812 pmap_link_l2pt(l1pagetable, l2_start + i * L1_S_SIZE, 813 &kernel_pt_table[i]); 814 815 pmap_curmaxkvaddr = l2_start + (l2size - 1) * L1_S_SIZE; 816 817 /* Map kernel code and data */ 818 pmap_map_chunk(l1pagetable, KERNVIRTADDR, abp->abp_physaddr, 819 (((uint32_t)(lastaddr) - KERNVIRTADDR) + PAGE_MASK) & ~PAGE_MASK, 820 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 821 822 /* Map L1 directory and allocated L2 page tables */ 823 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 824 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 825 826 pmap_map_chunk(l1pagetable, kernel_pt_table[0].pv_va, 827 kernel_pt_table[0].pv_pa, 828 L2_TABLE_SIZE_REAL * l2size, 829 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 830 831 /* Map allocated DPCPU, stacks and msgbuf */ 832 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, 833 freemempos - dpcpu.pv_va, 834 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 835 836 /* Link and map the vector page */ 837 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH, 838 &kernel_pt_table[l2size - 1]); 839 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 840 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, PTE_CACHE); 841 842 /* Establish static device mappings. */ 843 err_devmap = platform_devmap_init(); 844 devmap_bootstrap(l1pagetable, NULL); 845 vm_max_kernel_address = platform_lastaddr(); 846 847 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT); 848 pmap_pa = kernel_l1pt.pv_pa; 849 cpu_setttb(kernel_l1pt.pv_pa); 850 cpu_tlb_flushID(); 851 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); 852 853 /* 854 * Now that proper page tables are installed, call cpu_setup() to enable 855 * instruction and data caches and other chip-specific features. 856 */ 857 cpu_setup(); 858 859 /* 860 * Only after the SOC registers block is mapped we can perform device 861 * tree fixups, as they may attempt to read parameters from hardware. 862 */ 863 OF_interpret("perform-fixup", 0); 864 865 platform_gpio_init(); 866 867 cninit(); 868 869 debugf("initarm: console initialized\n"); 870 debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp); 871 debugf(" boothowto = 0x%08x\n", boothowto); 872 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp); 873 arm_print_kenv(); 874 875 env = kern_getenv("kernelname"); 876 if (env != NULL) { 877 strlcpy(kernelname, env, sizeof(kernelname)); 878 freeenv(env); 879 } 880 881 if (err_devmap != 0) 882 printf("WARNING: could not fully configure devmap, error=%d\n", 883 err_devmap); 884 885 platform_late_init(); 886 887 /* 888 * Pages were allocated during the secondary bootstrap for the 889 * stacks for different CPU modes. 890 * We must now set the r13 registers in the different CPU modes to 891 * point to these stacks. 892 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 893 * of the stack memory. 894 */ 895 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); 896 897 set_stackptrs(0); 898 899 /* 900 * We must now clean the cache again.... 901 * Cleaning may be done by reading new data to displace any 902 * dirty data in the cache. This will have happened in cpu_setttb() 903 * but since we are boot strapping the addresses used for the read 904 * may have just been remapped and thus the cache could be out 905 * of sync. A re-clean after the switch will cure this. 906 * After booting there are no gross relocations of the kernel thus 907 * this problem will not occur after initarm(). 908 */ 909 cpu_idcache_wbinv_all(); 910 911 undefined_init(); 912 913 init_proc0(kernelstack.pv_va); 914 915 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 916 pmap_bootstrap(freemempos, &kernel_l1pt); 917 msgbufp = (void *)msgbufpv.pv_va; 918 msgbufinit(msgbufp, msgbufsize); 919 mutex_init(); 920 921 /* 922 * Exclude the kernel (and all the things we allocated which immediately 923 * follow the kernel) from the VM allocation pool but not from crash 924 * dumps. virtual_avail is a global variable which tracks the kva we've 925 * "allocated" while setting up pmaps. 926 * 927 * Prepare the list of physical memory available to the vm subsystem. 928 */ 929 arm_physmem_exclude_region(abp->abp_physaddr, 930 (virtual_avail - KERNVIRTADDR), EXFLAG_NOALLOC); 931 arm_physmem_init_kernel_globals(); 932 933 init_param2(physmem); 934 dbg_monitor_init(); 935 kdb_init(); 936 937 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 938 sizeof(struct pcb))); 939} 940#else /* __ARM_ARCH < 6 */ 941void * 942initarm(struct arm_boot_params *abp) 943{ 944 struct mem_region mem_regions[FDT_MEM_REGIONS]; 945 vm_paddr_t lastaddr; 946 vm_offset_t dtbp, kernelstack, dpcpu; 947 char *env; 948 void *kmdp; 949 int err_devmap, mem_regions_sz; 950#ifdef EFI 951 struct efi_map_header *efihdr; 952#endif 953 954 /* get last allocated physical address */ 955 arm_physmem_kernaddr = abp->abp_physaddr; 956 lastaddr = parse_boot_param(abp) - KERNVIRTADDR + arm_physmem_kernaddr; 957 958 set_cpufuncs(); 959 cpuinfo_init(); 960 961 /* 962 * Find the dtb passed in by the boot loader. 963 */ 964 kmdp = preload_search_by_type("elf kernel"); 965 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t); 966#if defined(FDT_DTB_STATIC) 967 /* 968 * In case the device tree blob was not retrieved (from metadata) try 969 * to use the statically embedded one. 970 */ 971 if (dtbp == (vm_offset_t)NULL) 972 dtbp = (vm_offset_t)&fdt_static_dtb; 973#endif 974 975 if (OF_install(OFW_FDT, 0) == FALSE) 976 panic("Cannot install FDT"); 977 978 if (OF_init((void *)dtbp) != 0) 979 panic("OF_init failed with the found device tree"); 980 981#if defined(LINUX_BOOT_ABI) 982 arm_parse_fdt_bootargs(); 983#endif 984 985#ifdef EFI 986 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 987 MODINFO_METADATA | MODINFOMD_EFI_MAP); 988 if (efihdr != NULL) { 989 arm_add_efi_map_entries(efihdr, mem_regions, &mem_regions_sz); 990 } else 991#endif 992 { 993 /* Grab physical memory regions information from device tree. */ 994 if (fdt_get_mem_regions(mem_regions, &mem_regions_sz,NULL) != 0) 995 panic("Cannot get physical memory regions"); 996 } 997 arm_physmem_hardware_regions(mem_regions, mem_regions_sz); 998 999 /* Grab reserved memory regions information from device tree. */ 1000 if (fdt_get_reserved_regions(mem_regions, &mem_regions_sz) == 0) 1001 arm_physmem_exclude_regions(mem_regions, mem_regions_sz, 1002 EXFLAG_NODUMP | EXFLAG_NOALLOC); 1003 1004 /* 1005 * Set TEX remapping registers. 1006 * Setup kernel page tables and switch to kernel L1 page table. 1007 */ 1008 pmap_set_tex(); 1009 pmap_bootstrap_prepare(lastaddr); 1010 1011 /* 1012 * Now that proper page tables are installed, call cpu_setup() to enable 1013 * instruction and data caches and other chip-specific features. 1014 */ 1015 cpu_setup(); 1016 1017 /* Platform-specific initialisation */ 1018 platform_probe_and_attach(); 1019 pcpu0_init(); 1020 1021 /* Do basic tuning, hz etc */ 1022 init_param1(); 1023 1024 /* 1025 * Allocate a page for the system page mapped to 0xffff0000 1026 * This page will just contain the system vectors and can be 1027 * shared by all processes. 1028 */ 1029 systempage = pmap_preboot_get_pages(1); 1030 1031 /* Map the vector page. */ 1032 pmap_preboot_map_pages(systempage, ARM_VECTORS_HIGH, 1); 1033 if (virtual_end >= ARM_VECTORS_HIGH) 1034 virtual_end = ARM_VECTORS_HIGH - 1; 1035 1036 /* Allocate dynamic per-cpu area. */ 1037 dpcpu = pmap_preboot_get_vpages(DPCPU_SIZE / PAGE_SIZE); 1038 dpcpu_init((void *)dpcpu, 0); 1039 1040 /* Allocate stacks for all modes */ 1041 irqstack = pmap_preboot_get_vpages(IRQ_STACK_SIZE * MAXCPU); 1042 abtstack = pmap_preboot_get_vpages(ABT_STACK_SIZE * MAXCPU); 1043 undstack = pmap_preboot_get_vpages(UND_STACK_SIZE * MAXCPU ); 1044 kernelstack = pmap_preboot_get_vpages(kstack_pages * MAXCPU); 1045 1046 /* Allocate message buffer. */ 1047 msgbufp = (void *)pmap_preboot_get_vpages( 1048 round_page(msgbufsize) / PAGE_SIZE); 1049 1050 /* 1051 * Pages were allocated during the secondary bootstrap for the 1052 * stacks for different CPU modes. 1053 * We must now set the r13 registers in the different CPU modes to 1054 * point to these stacks. 1055 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 1056 * of the stack memory. 1057 */ 1058 set_stackptrs(0); 1059 mutex_init(); 1060 1061 /* Establish static device mappings. */ 1062 err_devmap = platform_devmap_init(); 1063 devmap_bootstrap(0, NULL); 1064 vm_max_kernel_address = platform_lastaddr(); 1065 1066 /* 1067 * Only after the SOC registers block is mapped we can perform device 1068 * tree fixups, as they may attempt to read parameters from hardware. 1069 */ 1070 OF_interpret("perform-fixup", 0); 1071 platform_gpio_init(); 1072 cninit(); 1073 1074 debugf("initarm: console initialized\n"); 1075 debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp); 1076 debugf(" boothowto = 0x%08x\n", boothowto); 1077 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp); 1078 debugf(" lastaddr1: 0x%08x\n", lastaddr); 1079 arm_print_kenv(); 1080 1081 env = kern_getenv("kernelname"); 1082 if (env != NULL) 1083 strlcpy(kernelname, env, sizeof(kernelname)); 1084 1085 if (err_devmap != 0) 1086 printf("WARNING: could not fully configure devmap, error=%d\n", 1087 err_devmap); 1088 1089 platform_late_init(); 1090 1091 /* 1092 * We must now clean the cache again.... 1093 * Cleaning may be done by reading new data to displace any 1094 * dirty data in the cache. This will have happened in cpu_setttb() 1095 * but since we are boot strapping the addresses used for the read 1096 * may have just been remapped and thus the cache could be out 1097 * of sync. A re-clean after the switch will cure this. 1098 * After booting there are no gross relocations of the kernel thus 1099 * this problem will not occur after initarm(). 1100 */ 1101 /* Set stack for exception handlers */ 1102 undefined_init(); 1103 init_proc0(kernelstack); 1104 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 1105 enable_interrupts(PSR_A); 1106 pmap_bootstrap(0); 1107 1108 /* Exclude the kernel (and all the things we allocated which immediately 1109 * follow the kernel) from the VM allocation pool but not from crash 1110 * dumps. virtual_avail is a global variable which tracks the kva we've 1111 * "allocated" while setting up pmaps. 1112 * 1113 * Prepare the list of physical memory available to the vm subsystem. 1114 */ 1115 arm_physmem_exclude_region(abp->abp_physaddr, 1116 pmap_preboot_get_pages(0) - abp->abp_physaddr, EXFLAG_NOALLOC); 1117 arm_physmem_init_kernel_globals(); 1118 1119 init_param2(physmem); 1120 /* Init message buffer. */ 1121 msgbufinit(msgbufp, msgbufsize); 1122 dbg_monitor_init(); 1123 kdb_init(); 1124 return ((void *)STACKALIGN(thread0.td_pcb)); 1125 1126} 1127 1128#endif /* __ARM_ARCH < 6 */ 1129#endif /* FDT */ 1130