fpu_emu.h revision 331722
1/* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93 34 * $NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ 35 * $FreeBSD: stable/11/lib/libc/sparc64/fpu/fpu_emu.h 331722 2018-03-29 02:50:57Z eadler $ 36 */ 37 38/* 39 * Floating point emulator (tailored for SPARC, but structurally 40 * machine-independent). 41 * 42 * Floating point numbers are carried around internally in an `expanded' 43 * or `unpacked' form consisting of: 44 * - sign 45 * - unbiased exponent 46 * - mantissa (`1.' + 112-bit fraction + guard + round) 47 * - sticky bit 48 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 49 * always nonzero. Additional low-order `guard' and `round' bits are 50 * scrunched in, making the entire mantissa 115 bits long. This is divided 51 * into four 32-bit words, with `spare' bits left over in the upper part 52 * of the top word (the high bits of fp_mant[0]). An internal `exploded' 53 * number is thus kept within the half-open interval [1.0,2.0) (but see 54 * the `number classes' below). This holds even for denormalized numbers: 55 * when we explode an external denorm, we normalize it, introducing low-order 56 * zero bits, so that the rest of the code always sees normalized values. 57 * 58 * Note that a number of our algorithms use the `spare' bits at the top. 59 * The most demanding algorithm---the one for sqrt---depends on two such 60 * bits, so that it can represent values up to (but not including) 8.0, 61 * and then it needs a carry on top of that, so that we need three `spares'. 62 * 63 * The sticky-word is 32 bits so that we can use `OR' operators to goosh 64 * whole words from the mantissa into it. 65 * 66 * All operations are done in this internal extended precision. According 67 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 68 * it is OK to do a+b in extended precision and then round the result to 69 * single precision---provided single, double, and extended precisions are 70 * `far enough apart' (they always are), but we will try to avoid any such 71 * extra work where possible. 72 */ 73 74#ifndef _SPARC64_FPU_FPU_EMU_H_ 75#define _SPARC64_FPU_FPU_EMU_H_ 76 77#include "fpu_reg.h" 78 79struct fpn { 80 int fp_class; /* see below */ 81 int fp_sign; /* 0 => positive, 1 => negative */ 82 int fp_exp; /* exponent (unbiased) */ 83 int fp_sticky; /* nonzero bits lost at right end */ 84 u_int fp_mant[4]; /* 115-bit mantissa */ 85}; 86 87#define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 88#define FP_NG 2 /* number of low-order guard bits */ 89#define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 90#define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */ 91#define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 92#define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 93#define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 94 95/* 96 * Number classes. Since zero, Inf, and NaN cannot be represented using 97 * the above layout, we distinguish these from other numbers via a class. 98 * In addition, to make computation easier and to follow Appendix N of 99 * the SPARC Version 8 standard, we give each kind of NaN a separate class. 100 */ 101#define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 102#define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 103#define FPC_ZERO 0 /* zero (sign matters) */ 104#define FPC_NUM 1 /* number (sign matters) */ 105#define FPC_INF 2 /* infinity (sign matters) */ 106 107#define ISNAN(fp) ((fp)->fp_class < 0) 108#define ISZERO(fp) ((fp)->fp_class == 0) 109#define ISINF(fp) ((fp)->fp_class == FPC_INF) 110 111/* 112 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 113 * to the `more significant' operand for our purposes. Appendix N says that 114 * the result of a computation involving two numbers are: 115 * 116 * If both are SNaN: operand 2, converted to Quiet 117 * If only one is SNaN: the SNaN operand, converted to Quiet 118 * If both are QNaN: operand 2 119 * If only one is QNaN: the QNaN operand 120 * 121 * In addition, in operations with an Inf operand, the result is usually 122 * Inf. The class numbers are carefully arranged so that if 123 * (unsigned)class(op1) > (unsigned)class(op2) 124 * then op1 is the one we want; otherwise op2 is the one we want. 125 */ 126#define ORDER(x, y) { \ 127 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 128 SWAP(x, y); \ 129} 130#define SWAP(x, y) { \ 131 register struct fpn *swap; \ 132 swap = (x), (x) = (y), (y) = swap; \ 133} 134 135/* 136 * Floating point operand types. FTYPE_LNG is syntethic (it does not occur in 137 * instructions). 138 */ 139#define FTYPE_INT INSFP_i 140#define FTYPE_SNG INSFP_s 141#define FTYPE_DBL INSFP_d 142#define FTYPE_EXT INSFP_q 143#define FTYPE_LNG 4 144 145/* 146 * Emulator state. 147 */ 148struct fpemu { 149 u_long fe_fsr; /* fsr copy (modified during op) */ 150 int fe_cx; /* exceptions */ 151 int pad; /* align access to following fields */ 152 struct fpn fe_f1; /* operand 1 */ 153 struct fpn fe_f2; /* operand 2, if required */ 154 struct fpn fe_f3; /* available storage for result */ 155}; 156 157/* 158 * Arithmetic functions. 159 * Each of these may modify its inputs (f1,f2) and/or the temporary. 160 * Each returns a pointer to the result and/or sets exceptions. 161 */ 162#define __fpu_sub(fe) (ISNAN(&(fe)->fe_f2) ? 0 : ((fe)->fe_f2.fp_sign ^= 1), \ 163 __fpu_add(fe)) 164 165#ifdef FPU_DEBUG 166#define FPE_INSN 0x1 167#define FPE_REG 0x2 168extern int __fpe_debug; 169void __fpu_dumpfpn(struct fpn *); 170#define DPRINTF(x, y) if (__fpe_debug & (x)) printf y 171#define DUMPFPN(x, f) if (__fpe_debug & (x)) __fpu_dumpfpn((f)) 172#else 173#define DPRINTF(x, y) 174#define DUMPFPN(x, f) 175#endif 176 177#endif /* !_SPARC64_FPU_FPU_EXTERN_H_ */ 178