ar724x_chip.c revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010 Adrian Chadd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: stable/11/sys/mips/atheros/ar724x_chip.c 330897 2018-03-14 03:19:51Z eadler $");
31
32#include "opt_ddb.h"
33
34#include <sys/param.h>
35#include <sys/conf.h>
36#include <sys/kernel.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39#include <sys/cons.h>
40#include <sys/kdb.h>
41#include <sys/reboot.h>
42
43#include <vm/vm.h>
44#include <vm/vm_page.h>
45
46#include <net/ethernet.h>
47
48#include <machine/clock.h>
49#include <machine/cpu.h>
50#include <machine/cpuregs.h>
51#include <machine/hwfunc.h>
52#include <machine/md_var.h>
53#include <machine/trap.h>
54#include <machine/vmparam.h>
55
56#include <mips/atheros/ar71xxreg.h>
57#include <mips/atheros/ar724xreg.h>
58
59#include <mips/atheros/ar71xx_cpudef.h>
60#include <mips/atheros/ar71xx_setup.h>
61#include <mips/atheros/ar71xx_chip.h>
62#include <mips/atheros/ar724x_chip.h>
63
64static void
65ar724x_chip_detect_mem_size(void)
66{
67}
68
69static void
70ar724x_chip_detect_sys_frequency(void)
71{
72	uint32_t pll;
73	uint32_t freq;
74	uint32_t div;
75
76	u_ar71xx_mdio_freq = u_ar71xx_refclk = AR724X_BASE_FREQ;
77
78	pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
79
80	div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
81	freq = div * AR724X_BASE_FREQ;
82
83	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
84	freq *= div;
85
86	u_ar71xx_cpu_freq = freq;
87
88	div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
89	u_ar71xx_ddr_freq = freq / div;
90
91	div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
92	u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
93	u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
94	u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
95}
96
97static void
98ar724x_chip_device_stop(uint32_t mask)
99{
100	uint32_t mask_inv, reg;
101
102	mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
103	reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
104	reg |= mask;
105	reg &= ~mask_inv;
106	ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
107}
108
109static void
110ar724x_chip_device_start(uint32_t mask)
111{
112	uint32_t mask_inv, reg;
113
114	mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
115	reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
116	reg &= ~mask;
117	reg |= mask_inv;
118	ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
119}
120
121static int
122ar724x_chip_device_stopped(uint32_t mask)
123{
124	uint32_t reg;
125
126	reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
127	return ((reg & mask) == mask);
128}
129
130static void
131ar724x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
132{
133
134	/* XXX TODO */
135	return;
136}
137
138/*
139 * XXX TODO: set the PLL for arge0 only on AR7242.
140 * The PLL/clock requirements are different.
141 *
142 * Otherwise, it's a NULL function for AR7240, AR7241 and
143 * AR7242 arge1.
144 */
145static void
146ar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
147{
148
149	switch (unit) {
150	case 0:
151		/* XXX TODO */
152		break;
153	case 1:
154		/* XXX TODO */
155		break;
156	default:
157		printf("%s: invalid PLL set for arge unit: %d\n",
158		    __func__, unit);
159		return;
160	}
161}
162
163static void
164ar724x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
165{
166
167	switch (id) {
168	case AR71XX_CPU_DDR_FLUSH_GE0:
169		ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
170		break;
171	case AR71XX_CPU_DDR_FLUSH_GE1:
172		ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
173		break;
174	case AR71XX_CPU_DDR_FLUSH_USB:
175		ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB);
176		break;
177	case AR71XX_CPU_DDR_FLUSH_PCIE:
178		ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
179		break;
180	default:
181		printf("%s: invalid DDR flush id (%d)\n", __func__, id);
182		break;
183	}
184}
185
186static uint32_t
187ar724x_chip_get_eth_pll(unsigned int mac, int speed)
188{
189
190	return (0);
191}
192
193static void
194ar724x_chip_init_usb_peripheral(void)
195{
196
197	switch (ar71xx_soc) {
198	case AR71XX_SOC_AR7240:
199		ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL |
200		    AR724X_RESET_USB_HOST);
201		DELAY(1000);
202
203		ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL |
204		    AR724X_RESET_USB_HOST);
205		DELAY(1000);
206
207		/*
208		 * WAR for HW bug. Here it adjusts the duration
209		 * between two SOFS.
210		 */
211		ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
212		    (3 << USB_CTRL_FLADJ_A0_SHIFT));
213
214		break;
215
216	case AR71XX_SOC_AR7241:
217	case AR71XX_SOC_AR7242:
218		ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL);
219		DELAY(100);
220
221		ar71xx_device_start(AR724X_RESET_USB_HOST);
222		DELAY(100);
223
224		ar71xx_device_start(AR724X_RESET_USB_PHY);
225		DELAY(100);
226
227		break;
228
229	default:
230		break;
231	}
232}
233
234struct ar71xx_cpu_def ar724x_chip_def = {
235	&ar724x_chip_detect_mem_size,
236	&ar724x_chip_detect_sys_frequency,
237	&ar724x_chip_device_stop,
238	&ar724x_chip_device_start,
239	&ar724x_chip_device_stopped,
240	&ar724x_chip_set_pll_ge,
241	&ar724x_chip_set_mii_speed,
242	&ar71xx_chip_set_mii_if,
243	&ar724x_chip_get_eth_pll,
244	&ar724x_chip_ddr_flush,
245	&ar724x_chip_init_usb_peripheral
246};
247