aintc.c revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * All rights reserved.
6 *
7 * Based on OMAP3 INTC code by Ben Gray
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: stable/11/sys/arm/ti/aintc.c 330897 2018-03-14 03:19:51Z eadler $");
34
35#include "opt_platform.h"
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/kernel.h>
41#include <sys/ktr.h>
42#include <sys/module.h>
43#include <sys/proc.h>
44#include <sys/rman.h>
45#include <machine/bus.h>
46#include <machine/intr.h>
47
48#include <dev/fdt/fdt_common.h>
49#include <dev/ofw/openfirm.h>
50#include <dev/ofw/ofw_bus.h>
51#include <dev/ofw/ofw_bus_subr.h>
52
53#ifdef INTRNG
54#include "pic_if.h"
55#endif
56
57#define INTC_REVISION		0x00
58#define INTC_SYSCONFIG		0x10
59#define INTC_SYSSTATUS		0x14
60#define INTC_SIR_IRQ		0x40
61#define INTC_CONTROL		0x48
62#define INTC_THRESHOLD		0x68
63#define INTC_MIR_CLEAR(x)	(0x88 + ((x) * 0x20))
64#define INTC_MIR_SET(x)		(0x8C + ((x) * 0x20))
65#define INTC_ISR_SET(x)		(0x90 + ((x) * 0x20))
66#define INTC_ISR_CLEAR(x)	(0x94 + ((x) * 0x20))
67
68#define INTC_SIR_SPURIOUS_MASK	0xffffff80
69#define INTC_SIR_ACTIVE_MASK	0x7f
70
71#define INTC_NIRQS	128
72
73#ifdef INTRNG
74struct ti_aintc_irqsrc {
75	struct intr_irqsrc	tai_isrc;
76	u_int			tai_irq;
77};
78#endif
79
80struct ti_aintc_softc {
81	device_t		sc_dev;
82	struct resource *	aintc_res[3];
83	bus_space_tag_t		aintc_bst;
84	bus_space_handle_t	aintc_bsh;
85	uint8_t			ver;
86#ifdef INTRNG
87	struct ti_aintc_irqsrc	aintc_isrcs[INTC_NIRQS];
88#endif
89};
90
91static struct resource_spec ti_aintc_spec[] = {
92	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
93	{ -1, 0 }
94};
95
96static struct ti_aintc_softc *ti_aintc_sc = NULL;
97
98#define	aintc_read_4(_sc, reg)		\
99    bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg))
100#define	aintc_write_4(_sc, reg, val)		\
101    bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val))
102
103/* List of compatible strings for FDT tree */
104static struct ofw_compat_data compat_data[] = {
105	{"ti,am33xx-intc",	1},
106	{"ti,omap2-intc",	1},
107	{NULL,		 	0},
108};
109
110#ifdef INTRNG
111static inline void
112ti_aintc_irq_eoi(struct ti_aintc_softc *sc)
113{
114
115	aintc_write_4(sc, INTC_CONTROL, 1);
116}
117
118static inline void
119ti_aintc_irq_mask(struct ti_aintc_softc *sc, u_int irq)
120{
121
122	aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F)));
123}
124
125static inline void
126ti_aintc_irq_unmask(struct ti_aintc_softc *sc, u_int irq)
127{
128
129	aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F)));
130}
131
132static int
133ti_aintc_intr(void *arg)
134{
135	uint32_t irq;
136	struct ti_aintc_softc *sc = arg;
137
138	/* Get active interrupt */
139	irq = aintc_read_4(sc, INTC_SIR_IRQ);
140	if ((irq & INTC_SIR_SPURIOUS_MASK) != 0) {
141		device_printf(sc->sc_dev,
142		    "Spurious interrupt detected (0x%08x)\n", irq);
143		ti_aintc_irq_eoi(sc);
144		return (FILTER_HANDLED);
145	}
146
147	/* Only level-sensitive interrupts detection is supported. */
148	irq &= INTC_SIR_ACTIVE_MASK;
149	if (intr_isrc_dispatch(&sc->aintc_isrcs[irq].tai_isrc,
150	    curthread->td_intr_frame) != 0) {
151		ti_aintc_irq_mask(sc, irq);
152		ti_aintc_irq_eoi(sc);
153		device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq);
154	}
155
156	arm_irq_memory_barrier(irq); /* XXX */
157	return (FILTER_HANDLED);
158}
159
160static void
161ti_aintc_enable_intr(device_t dev, struct intr_irqsrc *isrc)
162{
163	u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq;
164	struct ti_aintc_softc *sc = device_get_softc(dev);
165
166	arm_irq_memory_barrier(irq);
167	ti_aintc_irq_unmask(sc, irq);
168}
169
170static void
171ti_aintc_disable_intr(device_t dev, struct intr_irqsrc *isrc)
172{
173	u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq;
174	struct ti_aintc_softc *sc = device_get_softc(dev);
175
176	ti_aintc_irq_mask(sc, irq);
177}
178
179static int
180ti_aintc_map_intr(device_t dev, struct intr_map_data *data,
181    struct intr_irqsrc **isrcp)
182{
183	struct intr_map_data_fdt *daf;
184	struct ti_aintc_softc *sc;
185
186	if (data->type != INTR_MAP_DATA_FDT)
187		return (ENOTSUP);
188
189	daf = (struct intr_map_data_fdt *)data;
190	if (daf->ncells != 1 || daf->cells[0] >= INTC_NIRQS)
191		return (EINVAL);
192
193	sc = device_get_softc(dev);
194	*isrcp = &sc->aintc_isrcs[daf->cells[0]].tai_isrc;
195	return (0);
196}
197
198static void
199ti_aintc_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
200{
201	u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq;
202	struct ti_aintc_softc *sc = device_get_softc(dev);
203
204	ti_aintc_irq_mask(sc, irq);
205	ti_aintc_irq_eoi(sc);
206}
207
208static void
209ti_aintc_post_ithread(device_t dev, struct intr_irqsrc *isrc)
210{
211
212	ti_aintc_enable_intr(dev, isrc);
213}
214
215static void
216ti_aintc_post_filter(device_t dev, struct intr_irqsrc *isrc)
217{
218
219	ti_aintc_irq_eoi(device_get_softc(dev));
220}
221
222static int
223ti_aintc_pic_attach(struct ti_aintc_softc *sc)
224{
225	struct intr_pic *pic;
226	int error;
227	uint32_t irq;
228	const char *name;
229	intptr_t xref;
230
231	name = device_get_nameunit(sc->sc_dev);
232	for (irq = 0; irq < INTC_NIRQS; irq++) {
233		sc->aintc_isrcs[irq].tai_irq = irq;
234
235		error = intr_isrc_register(&sc->aintc_isrcs[irq].tai_isrc,
236		    sc->sc_dev, 0, "%s,%u", name, irq);
237		if (error != 0)
238			return (error);
239	}
240
241	xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev));
242	pic = intr_pic_register(sc->sc_dev, xref);
243	if (pic == NULL)
244		return (ENXIO);
245
246	return (intr_pic_claim_root(sc->sc_dev, xref, ti_aintc_intr, sc, 0));
247}
248
249#else
250static void
251aintc_post_filter(void *arg)
252{
253
254	arm_irq_memory_barrier(0);
255	aintc_write_4(ti_aintc_sc, INTC_CONTROL, 1); /* EOI */
256}
257#endif
258
259static int
260ti_aintc_probe(device_t dev)
261{
262	if (!ofw_bus_status_okay(dev))
263		return (ENXIO);
264
265	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
266		return (ENXIO);
267
268	device_set_desc(dev, "TI AINTC Interrupt Controller");
269	return (BUS_PROBE_DEFAULT);
270}
271
272static int
273ti_aintc_attach(device_t dev)
274{
275	struct		ti_aintc_softc *sc = device_get_softc(dev);
276	uint32_t x;
277
278	sc->sc_dev = dev;
279
280	if (ti_aintc_sc)
281		return (ENXIO);
282
283	if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) {
284		device_printf(dev, "could not allocate resources\n");
285		return (ENXIO);
286	}
287
288	sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]);
289	sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]);
290
291	ti_aintc_sc = sc;
292
293	x = aintc_read_4(sc, INTC_REVISION);
294	device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF);
295
296	/* SoftReset */
297	aintc_write_4(sc, INTC_SYSCONFIG, 2);
298
299	/* Wait for reset to complete */
300	while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1));
301
302	/*Set Priority Threshold */
303	aintc_write_4(sc, INTC_THRESHOLD, 0xFF);
304
305#ifndef INTRNG
306	arm_post_filter = aintc_post_filter;
307#else
308	if (ti_aintc_pic_attach(sc) != 0) {
309		device_printf(dev, "could not attach PIC\n");
310		return (ENXIO);
311	}
312#endif
313	return (0);
314}
315
316static device_method_t ti_aintc_methods[] = {
317	DEVMETHOD(device_probe,		ti_aintc_probe),
318	DEVMETHOD(device_attach,	ti_aintc_attach),
319
320#ifdef INTRNG
321	DEVMETHOD(pic_disable_intr,	ti_aintc_disable_intr),
322	DEVMETHOD(pic_enable_intr,	ti_aintc_enable_intr),
323	DEVMETHOD(pic_map_intr,		ti_aintc_map_intr),
324	DEVMETHOD(pic_post_filter,	ti_aintc_post_filter),
325	DEVMETHOD(pic_post_ithread,	ti_aintc_post_ithread),
326	DEVMETHOD(pic_pre_ithread,	ti_aintc_pre_ithread),
327#endif
328
329	{ 0, 0 }
330};
331
332static driver_t ti_aintc_driver = {
333	"aintc",
334	ti_aintc_methods,
335	sizeof(struct ti_aintc_softc),
336};
337
338static devclass_t ti_aintc_devclass;
339
340EARLY_DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass,
341    0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
342SIMPLEBUS_PNP_INFO(compat_data);
343
344#ifndef INTRNG
345int
346arm_get_next_irq(int last_irq)
347{
348	struct ti_aintc_softc *sc = ti_aintc_sc;
349	uint32_t active_irq;
350
351	/* Get the next active interrupt */
352	active_irq = aintc_read_4(sc, INTC_SIR_IRQ);
353
354	/* Check for spurious interrupt */
355	if ((active_irq & 0xffffff80)) {
356		device_printf(sc->sc_dev,
357		    "Spurious interrupt detected (0x%08x)\n", active_irq);
358		aintc_write_4(sc, INTC_SIR_IRQ, 0);
359		return -1;
360	}
361
362	if (active_irq != last_irq)
363		return active_irq;
364	else
365		return -1;
366}
367
368void
369arm_mask_irq(uintptr_t nb)
370{
371	struct ti_aintc_softc *sc = ti_aintc_sc;
372
373	aintc_write_4(sc, INTC_MIR_SET(nb >> 5), (1UL << (nb & 0x1F)));
374	aintc_write_4(sc, INTC_CONTROL, 1); /* EOI */
375}
376
377void
378arm_unmask_irq(uintptr_t nb)
379{
380	struct ti_aintc_softc *sc = ti_aintc_sc;
381
382	arm_irq_memory_barrier(nb);
383	aintc_write_4(sc, INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F)));
384}
385#endif
386