at91dci.h revision 330897 
1/* $FreeBSD: stable/11/sys/dev/usb/controller/at91dci.h 330897 2018-03-14 03:19:51Z eadler $ */
2/*-
3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 *
5 * Copyright (c) 2006 ATMEL
6 * Copyright (c) 2007 Hans Petter Selasky <hselasky@FreeBSD.org>
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31/*
32 * USB Device Port (UDP) register definition, based on "AT91RM9200.h" provided
33 * by ATMEL.
34 */
35
36#ifndef _AT9100_DCI_H_
37#define	_AT9100_DCI_H_
38
39#define	AT91_MAX_DEVICES (USB_MIN_DEVICES + 1)
40
41#define	AT91_UDP_FRM 	0x00		/* Frame number register */
42#define	AT91_UDP_FRM_MASK     (0x7FF <<  0)	/* Frame Number as Defined in
43						 * the Packet Field Formats */
44#define	AT91_UDP_FRM_ERR      (0x1 << 16)	/* Frame Error */
45#define	AT91_UDP_FRM_OK       (0x1 << 17)	/* Frame OK */
46
47#define	AT91_UDP_GSTATE 0x04		/* Global state register */
48#define	AT91_UDP_GSTATE_ADDR  (0x1 <<  0)	/* Addressed state */
49#define	AT91_UDP_GSTATE_CONFG (0x1 <<  1)	/* Configured */
50#define	AT91_UDP_GSTATE_ESR   (0x1 <<  2)	/* Enable Send Resume */
51#define	AT91_UDP_GSTATE_RSM   (0x1 <<  3)	/* A Resume Has Been Sent to
52						 * the Host */
53#define	AT91_UDP_GSTATE_RMW   (0x1 <<  4)	/* Remote Wake Up Enable */
54
55#define	AT91_UDP_FADDR	0x08		/* Function Address Register */
56#define	AT91_UDP_FADDR_MASK  (0x7F << 0)/* Function Address Mask */
57#define	AT91_UDP_FADDR_EN    (0x1 <<  8)/* Function Enable */
58
59#define	AT91_UDP_RES0	0x0C		/* Reserved 0 */
60
61#define	AT91_UDP_IER	0x10		/* Interrupt Enable Register */
62#define	AT91_UDP_IDR	0x14		/* Interrupt Disable Register */
63#define	AT91_UDP_IMR	0x18		/* Interrupt Mask Register */
64#define	AT91_UDP_ISR	0x1C		/* Interrupt Status Register */
65#define	AT91_UDP_ICR	0x20		/* Interrupt Clear Register */
66#define	AT91_UDP_INT_EP(n)   (0x1 <<(n))/* Endpoint "n" Interrupt */
67#define	AT91_UDP_INT_RXSUSP  (0x1 <<  8)/* USB Suspend Interrupt */
68#define	AT91_UDP_INT_RXRSM   (0x1 <<  9)/* USB Resume Interrupt */
69#define	AT91_UDP_INT_EXTRSM  (0x1 << 10)/* USB External Resume Interrupt */
70#define	AT91_UDP_INT_SOFINT  (0x1 << 11)/* USB Start Of frame Interrupt */
71#define	AT91_UDP_INT_END_BR  (0x1 << 12)/* USB End Of Bus Reset Interrupt */
72#define	AT91_UDP_INT_WAKEUP  (0x1 << 13)/* USB Resume Interrupt */
73
74#define	AT91_UDP_INT_BUS \
75  (AT91_UDP_INT_RXSUSP|AT91_UDP_INT_RXRSM| \
76   AT91_UDP_INT_END_BR)
77
78#define	AT91_UDP_INT_EPS \
79  (AT91_UDP_INT_EP(0)|AT91_UDP_INT_EP(1)| \
80   AT91_UDP_INT_EP(2)|AT91_UDP_INT_EP(3)| \
81   AT91_UDP_INT_EP(4)|AT91_UDP_INT_EP(5))
82
83#define	AT91_UDP_INT_DEFAULT \
84  (AT91_UDP_INT_EPS|AT91_UDP_INT_BUS)
85
86#define	AT91_UDP_RES1	0x24		/* Reserved 1 */
87#define	AT91_UDP_RST	0x28		/* Reset Endpoint Register */
88#define	AT91_UDP_RST_EP(n) (0x1 <<  (n))/* Reset Endpoint "n" */
89
90#define	AT91_UDP_RES2	0x2C		/* Reserved 2 */
91
92#define	AT91_UDP_CSR(n) (0x30 + (4*(n)))/* Endpoint Control and Status
93					 * Register */
94#define	AT91_UDP_CSR_TXCOMP (0x1 <<  0)	/* Generates an IN packet with data
95					 * previously written in the DPR */
96#define	AT91_UDP_CSR_RX_DATA_BK0 (0x1 <<  1)	/* Receive Data Bank 0 */
97#define	AT91_UDP_CSR_RXSETUP     (0x1 <<  2)	/* Sends STALL to the Host
98						 * (Control endpoints) */
99#define	AT91_UDP_CSR_ISOERROR    (0x1 <<  3)	/* Isochronous error
100						 * (Isochronous endpoints) */
101#define	AT91_UDP_CSR_STALLSENT   (0x1 <<  3)	/* Stall sent (Control, bulk,
102						 * interrupt endpoints) */
103#define	AT91_UDP_CSR_TXPKTRDY    (0x1 <<  4)	/* Transmit Packet Ready */
104#define	AT91_UDP_CSR_FORCESTALL  (0x1 <<  5)	/* Force Stall (used by
105						 * Control, Bulk and
106						 * Isochronous endpoints). */
107#define	AT91_UDP_CSR_RX_DATA_BK1 (0x1 <<  6)	/* Receive Data Bank 1 (only
108						 * used by endpoints with
109						 * ping-pong attributes). */
110#define	AT91_UDP_CSR_DIR         (0x1 <<  7)	/* Transfer Direction */
111#define	AT91_UDP_CSR_ET_MASK     (0x7 <<  8)	/* Endpoint transfer type mask */
112#define	AT91_UDP_CSR_ET_CTRL     (0x0 <<  8)	/* Control IN+OUT */
113#define	AT91_UDP_CSR_ET_ISO      (0x1 <<  8)	/* Isochronous */
114#define	AT91_UDP_CSR_ET_BULK     (0x2 <<  8)	/* Bulk */
115#define	AT91_UDP_CSR_ET_INT      (0x3 <<  8)	/* Interrupt */
116#define	AT91_UDP_CSR_ET_DIR_OUT  (0x0 <<  8)	/* OUT tokens */
117#define	AT91_UDP_CSR_ET_DIR_IN   (0x4 <<  8)	/* IN tokens */
118#define	AT91_UDP_CSR_DTGLE       (0x1 << 11)	/* Data Toggle */
119#define	AT91_UDP_CSR_EPEDS       (0x1 << 15)	/* Endpoint Enable Disable */
120#define	AT91_UDP_CSR_RXBYTECNT   (0x7FF << 16)	/* Number Of Bytes Available
121						 * in the FIFO */
122
123#define	AT91_UDP_FDR(n) (0x50 + (4*(n)))/* Endpoint FIFO Data Register */
124#define	AT91_UDP_RES3	0x70		/* Reserved 3 */
125#define	AT91_UDP_TXVC	0x74		/* Transceiver Control Register */
126#define	AT91_UDP_TXVC_DIS      (0x1 <<  8)
127
128#define	AT91_UDP_EP_MAX 6		/* maximum number of endpoints
129					 * supported */
130
131#define	AT91_UDP_READ_4(sc, reg) \
132  bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
133
134#define	AT91_UDP_WRITE_4(sc, reg, data)	\
135  bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
136
137struct at91dci_td;
138struct at91dci_softc;
139
140typedef uint8_t (at91dci_cmd_t)(struct at91dci_softc *sc, struct at91dci_td *td);
141
142struct at91dci_td {
143	struct at91dci_td *obj_next;
144	at91dci_cmd_t *func;
145	struct usb_page_cache *pc;
146	uint32_t offset;
147	uint32_t remainder;
148	uint16_t max_packet_size;
149	uint8_t	status_reg;
150	uint8_t	fifo_reg;
151	uint8_t	fifo_bank:1;
152	uint8_t	error:1;
153	uint8_t	alt_next:1;
154	uint8_t	short_pkt:1;
155	uint8_t	support_multi_buffer:1;
156	uint8_t	did_stall:1;
157};
158
159struct at91dci_std_temp {
160	at91dci_cmd_t *func;
161	struct usb_page_cache *pc;
162	struct at91dci_td *td;
163	struct at91dci_td *td_next;
164	uint32_t len;
165	uint32_t offset;
166	uint16_t max_frame_size;
167	uint8_t	short_pkt;
168	/*
169         * short_pkt = 0: transfer should be short terminated
170         * short_pkt = 1: transfer should not be short terminated
171         */
172	uint8_t	setup_alt_next;
173	uint8_t did_stall;
174};
175
176struct at91dci_config_desc {
177	struct usb_config_descriptor confd;
178	struct usb_interface_descriptor ifcd;
179	struct usb_endpoint_descriptor endpd;
180} __packed;
181
182union at91dci_hub_temp {
183	uWord	wValue;
184	struct usb_port_status ps;
185};
186
187struct at91dci_ep_flags {
188	uint8_t	fifo_bank:1;		/* hardware specific */
189};
190
191struct at91dci_flags {
192	uint8_t	change_connect:1;
193	uint8_t	change_suspend:1;
194	uint8_t	status_suspend:1;	/* set if suspended */
195	uint8_t	status_vbus:1;		/* set if present */
196	uint8_t	status_bus_reset:1;	/* set if reset complete */
197	uint8_t	remote_wakeup:1;
198	uint8_t	self_powered:1;
199	uint8_t	clocks_off:1;
200	uint8_t	port_powered:1;
201	uint8_t	port_enabled:1;
202	uint8_t	d_pulled_up:1;
203};
204
205struct at91dci_softc {
206	struct usb_bus sc_bus;
207	union at91dci_hub_temp sc_hub_temp;
208
209	struct usb_device *sc_devices[AT91_MAX_DEVICES];
210	struct resource *sc_io_res;
211	struct resource *sc_irq_res;
212	void   *sc_intr_hdl;
213	bus_size_t sc_io_size;
214	bus_space_tag_t sc_io_tag;
215	bus_space_handle_t sc_io_hdl;
216
217	void    (*sc_clocks_on) (void *arg);
218	void    (*sc_clocks_off) (void *arg);
219	void   *sc_clocks_arg;
220
221	void    (*sc_pull_up) (void *arg);
222	void    (*sc_pull_down) (void *arg);
223	void   *sc_pull_arg;
224
225	uint32_t sc_xfer_complete;
226
227	uint8_t	sc_rt_addr;		/* root HUB address */
228	uint8_t	sc_dv_addr;		/* device address */
229	uint8_t	sc_conf;		/* root HUB config */
230
231	uint8_t	sc_hub_idata[1];
232
233	struct at91dci_flags sc_flags;
234	struct at91dci_ep_flags sc_ep_flags[AT91_UDP_EP_MAX];
235};
236
237/* prototypes */
238
239usb_error_t at91dci_init(struct at91dci_softc *sc);
240void	at91dci_uninit(struct at91dci_softc *sc);
241driver_filter_t at91dci_filter_interrupt;
242driver_intr_t at91dci_interrupt;
243void	at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on);
244
245#endif					/* _AT9100_DCI_H_ */
246