atiixp.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: stable/11/sys/dev/sound/pci/atiixp.h 330897 2018-03-14 03:19:51Z eadler $
29 */
30
31#ifndef _ATIIXP_H_
32#define _ATIIXP_H_
33
34/*
35 * Constants, pretty much FreeBSD specific.
36 */
37
38/* Number of playback / recording channel */
39#define ATI_IXP_NPCHAN		1
40#define ATI_IXP_NRCHAN		1
41#define ATI_IXP_NCHANS		(ATI_IXP_NPCHAN + ATI_IXP_NRCHAN)
42
43/*
44 * Maximum segments/descriptors is 256, but 2 for
45 * each channel should be more than enough for us.
46 */
47#define ATI_IXP_DMA_CHSEGS	2
48#define ATI_IXP_DMA_CHSEGS_MIN	2
49#define ATI_IXP_DMA_CHSEGS_MAX	256
50
51#define ATI_VENDOR_ID		0x1002	/* ATI Technologies */
52
53#define ATI_IXP_200_ID		0x4341
54#define ATI_IXP_300_ID		0x4361
55#define ATI_IXP_400_ID		0x4370
56#define ATI_IXP_SB600_ID	0x4382
57
58#define ATI_IXP_BASE_RATE	48000
59
60/*
61 * Register definitions for ATI IXP
62 *
63 * References: ALSA snd-atiixp.c , OpenBSD/NetBSD auixp-*.h
64 */
65
66#define ATI_IXP_CODECS 3
67
68#define ATI_REG_ISR			0x00		/* interrupt source */
69#define  ATI_REG_ISR_IN_XRUN		(1U<<0)
70#define  ATI_REG_ISR_IN_STATUS		(1U<<1)
71#define  ATI_REG_ISR_OUT_XRUN		(1U<<2)
72#define  ATI_REG_ISR_OUT_STATUS		(1U<<3)
73#define  ATI_REG_ISR_SPDF_XRUN		(1U<<4)
74#define  ATI_REG_ISR_SPDF_STATUS	(1U<<5)
75#define  ATI_REG_ISR_PHYS_INTR		(1U<<8)
76#define  ATI_REG_ISR_PHYS_MISMATCH	(1U<<9)
77#define  ATI_REG_ISR_CODEC0_NOT_READY	(1U<<10)
78#define  ATI_REG_ISR_CODEC1_NOT_READY	(1U<<11)
79#define  ATI_REG_ISR_CODEC2_NOT_READY	(1U<<12)
80#define  ATI_REG_ISR_NEW_FRAME		(1U<<13)
81
82#define ATI_REG_IER			0x04		/* interrupt enable */
83#define  ATI_REG_IER_IN_XRUN_EN		(1U<<0)
84#define  ATI_REG_IER_IO_STATUS_EN	(1U<<1)
85#define  ATI_REG_IER_OUT_XRUN_EN	(1U<<2)
86#define  ATI_REG_IER_OUT_XRUN_COND	(1U<<3)
87#define  ATI_REG_IER_SPDF_XRUN_EN	(1U<<4)
88#define  ATI_REG_IER_SPDF_STATUS_EN	(1U<<5)
89#define  ATI_REG_IER_PHYS_INTR_EN	(1U<<8)
90#define  ATI_REG_IER_PHYS_MISMATCH_EN	(1U<<9)
91#define  ATI_REG_IER_CODEC0_INTR_EN	(1U<<10)
92#define  ATI_REG_IER_CODEC1_INTR_EN	(1U<<11)
93#define  ATI_REG_IER_CODEC2_INTR_EN	(1U<<12)
94#define  ATI_REG_IER_NEW_FRAME_EN	(1U<<13)	/* (RO) */
95#define  ATI_REG_IER_SET_BUS_BUSY	(1U<<14)	/* (WO) audio is running */
96
97#define ATI_REG_CMD			0x08		/* command */
98#define  ATI_REG_CMD_POWERDOWN		(1U<<0)
99#define  ATI_REG_CMD_RECEIVE_EN		(1U<<1)
100#define  ATI_REG_CMD_SEND_EN		(1U<<2)
101#define  ATI_REG_CMD_STATUS_MEM		(1U<<3)
102#define  ATI_REG_CMD_SPDF_OUT_EN	(1U<<4)
103#define  ATI_REG_CMD_SPDF_STATUS_MEM	(1U<<5)
104#define  ATI_REG_CMD_SPDF_THRESHOLD	(3U<<6)
105#define  ATI_REG_CMD_SPDF_THRESHOLD_SHIFT	6
106#define  ATI_REG_CMD_IN_DMA_EN		(1U<<8)
107#define  ATI_REG_CMD_OUT_DMA_EN		(1U<<9)
108#define  ATI_REG_CMD_SPDF_DMA_EN	(1U<<10)
109#define  ATI_REG_CMD_SPDF_OUT_STOPPED	(1U<<11)
110#define  ATI_REG_CMD_SPDF_CONFIG_MASK	(7U<<12)
111#define   ATI_REG_CMD_SPDF_CONFIG_34	(1U<<12)
112#define   ATI_REG_CMD_SPDF_CONFIG_78	(2U<<12)
113#define   ATI_REG_CMD_SPDF_CONFIG_69	(3U<<12)
114#define   ATI_REG_CMD_SPDF_CONFIG_01	(4U<<12)
115#define  ATI_REG_CMD_INTERLEAVE_SPDF	(1U<<16)
116#define  ATI_REG_CMD_AUDIO_PRESENT	(1U<<20)
117#define  ATI_REG_CMD_INTERLEAVE_IN	(1U<<21)
118#define  ATI_REG_CMD_INTERLEAVE_OUT	(1U<<22)
119#define  ATI_REG_CMD_LOOPBACK_EN	(1U<<23)
120#define  ATI_REG_CMD_PACKED_DIS		(1U<<24)
121#define  ATI_REG_CMD_BURST_EN		(1U<<25)
122#define  ATI_REG_CMD_PANIC_EN		(1U<<26)
123#define  ATI_REG_CMD_MODEM_PRESENT	(1U<<27)
124#define  ATI_REG_CMD_ACLINK_ACTIVE	(1U<<28)
125#define  ATI_REG_CMD_AC_SOFT_RESET	(1U<<29)
126#define  ATI_REG_CMD_AC_SYNC		(1U<<30)
127#define  ATI_REG_CMD_AC_RESET		(1U<<31)
128
129#define ATI_REG_PHYS_OUT_ADDR		0x0c
130#define  ATI_REG_PHYS_OUT_CODEC_MASK	(3U<<0)
131#define  ATI_REG_PHYS_OUT_RW		(1U<<2)
132#define  ATI_REG_PHYS_OUT_ADDR_EN	(1U<<8)
133#define  ATI_REG_PHYS_OUT_ADDR_SHIFT	9
134#define  ATI_REG_PHYS_OUT_DATA_SHIFT	16
135
136#define ATI_REG_PHYS_IN_ADDR		0x10
137#define  ATI_REG_PHYS_IN_READ_FLAG	(1U<<8)
138#define  ATI_REG_PHYS_IN_ADDR_SHIFT	9
139#define  ATI_REG_PHYS_IN_DATA_SHIFT	16
140
141#define ATI_REG_SLOTREQ			0x14
142
143#define ATI_REG_COUNTER			0x18
144#define  ATI_REG_COUNTER_SLOT		(3U<<0)		/* slot # */
145#define  ATI_REG_COUNTER_BITCLOCK	(31U<<8)
146
147#define ATI_REG_IN_FIFO_THRESHOLD	0x1c
148
149#define ATI_REG_IN_DMA_LINKPTR		0x20
150#define ATI_REG_IN_DMA_DT_START		0x24		/* RO */
151#define ATI_REG_IN_DMA_DT_NEXT		0x28		/* RO */
152#define ATI_REG_IN_DMA_DT_CUR		0x2c		/* RO */
153#define ATI_REG_IN_DMA_DT_SIZE		0x30
154
155#define ATI_REG_OUT_DMA_SLOT		0x34
156#define  ATI_REG_OUT_DMA_SLOT_BIT(x)	(1U << ((x) - 3))
157#define  ATI_REG_OUT_DMA_SLOT_MASK	0x1ff
158#define  ATI_REG_OUT_DMA_THRESHOLD_MASK	0xf800
159#define  ATI_REG_OUT_DMA_THRESHOLD_SHIFT	11
160
161#define ATI_REG_OUT_DMA_LINKPTR		0x38
162#define ATI_REG_OUT_DMA_DT_START	0x3c		/* RO */
163#define ATI_REG_OUT_DMA_DT_NEXT		0x40		/* RO */
164#define ATI_REG_OUT_DMA_DT_CUR		0x44		/* RO */
165#define ATI_REG_OUT_DMA_DT_SIZE		0x48
166
167#define ATI_REG_SPDF_CMD		0x4c
168#define  ATI_REG_SPDF_CMD_LFSR		(1U<<4)
169#define  ATI_REG_SPDF_CMD_SINGLE_CH	(1U<<5)
170#define  ATI_REG_SPDF_CMD_LFSR_ACC	(0xff<<8)	/* RO */
171
172#define ATI_REG_SPDF_DMA_LINKPTR	0x50
173#define ATI_REG_SPDF_DMA_DT_START	0x54		/* RO */
174#define ATI_REG_SPDF_DMA_DT_NEXT	0x58		/* RO */
175#define ATI_REG_SPDF_DMA_DT_CUR		0x5c		/* RO */
176#define ATI_REG_SPDF_DMA_DT_SIZE	0x60
177
178#define ATI_REG_MODEM_MIRROR		0x7c
179#define ATI_REG_AUDIO_MIRROR		0x80
180
181#define ATI_REG_6CH_REORDER		0x84		/* reorder slots for 6ch */
182#define  ATI_REG_6CH_REORDER_EN		(1U<<0)		/* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
183
184#define ATI_REG_FIFO_FLUSH		0x88
185#define  ATI_REG_FIFO_OUT_FLUSH		(1U<<0)
186#define  ATI_REG_FIFO_IN_FLUSH		(1U<<1)
187
188/* LINKPTR */
189#define  ATI_REG_LINKPTR_EN		(1U<<0)
190
191/* [INT|OUT|SPDIF]_DMA_DT_SIZE */
192#define  ATI_REG_DMA_DT_SIZE		(0xffffU<<0)
193#define  ATI_REG_DMA_FIFO_USED		(0x1fU<<16)
194#define  ATI_REG_DMA_FIFO_FREE		(0x1fU<<21)
195#define  ATI_REG_DMA_STATE		(7U<<26)
196
197#define ATI_MAX_DESCRIPTORS	256	/* max number of descriptor packets */
198
199/* codec detection constant indicating the interrupt flags */
200#define ALL_CODECS_NOT_READY \
201    (ATI_REG_ISR_CODEC0_NOT_READY | ATI_REG_ISR_CODEC1_NOT_READY |\
202     ATI_REG_ISR_CODEC2_NOT_READY)
203#define CODEC_CHECK_BITS (ALL_CODECS_NOT_READY|ATI_REG_ISR_NEW_FRAME)
204
205#endif
206