nvme_ctrlr.c revision 331722
1/*- 2 * Copyright (C) 2012-2016 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/dev/nvme/nvme_ctrlr.c 331722 2018-03-29 02:50:57Z eadler $"); 29 30#include "opt_cam.h" 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/buf.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/ioccom.h> 38#include <sys/proc.h> 39#include <sys/smp.h> 40#include <sys/uio.h> 41 42#include <dev/pci/pcireg.h> 43#include <dev/pci/pcivar.h> 44 45#include "nvme_private.h" 46 47#define B4_CHK_RDY_DELAY_MS 2300 /* work arond controller bug */ 48 49static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 50 struct nvme_async_event_request *aer); 51static void nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr); 52 53static int 54nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) 55{ 56 57 ctrlr->resource_id = PCIR_BAR(0); 58 59 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 60 &ctrlr->resource_id, RF_ACTIVE); 61 62 if(ctrlr->resource == NULL) { 63 nvme_printf(ctrlr, "unable to allocate pci resource\n"); 64 return (ENOMEM); 65 } 66 67 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); 68 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); 69 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; 70 71 /* 72 * The NVMe spec allows for the MSI-X table to be placed behind 73 * BAR 4/5, separate from the control/doorbell registers. Always 74 * try to map this bar, because it must be mapped prior to calling 75 * pci_alloc_msix(). If the table isn't behind BAR 4/5, 76 * bus_alloc_resource() will just return NULL which is OK. 77 */ 78 ctrlr->bar4_resource_id = PCIR_BAR(4); 79 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 80 &ctrlr->bar4_resource_id, RF_ACTIVE); 81 82 return (0); 83} 84 85static int 86nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr) 87{ 88 struct nvme_qpair *qpair; 89 uint32_t num_entries; 90 int error; 91 92 qpair = &ctrlr->adminq; 93 94 num_entries = NVME_ADMIN_ENTRIES; 95 TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries); 96 /* 97 * If admin_entries was overridden to an invalid value, revert it 98 * back to our default value. 99 */ 100 if (num_entries < NVME_MIN_ADMIN_ENTRIES || 101 num_entries > NVME_MAX_ADMIN_ENTRIES) { 102 nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d " 103 "specified\n", num_entries); 104 num_entries = NVME_ADMIN_ENTRIES; 105 } 106 107 /* 108 * The admin queue's max xfer size is treated differently than the 109 * max I/O xfer size. 16KB is sufficient here - maybe even less? 110 */ 111 error = nvme_qpair_construct(qpair, 112 0, /* qpair ID */ 113 0, /* vector */ 114 num_entries, 115 NVME_ADMIN_TRACKERS, 116 ctrlr); 117 return (error); 118} 119 120static int 121nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr) 122{ 123 struct nvme_qpair *qpair; 124 union cap_lo_register cap_lo; 125 int i, error, num_entries, num_trackers; 126 127 num_entries = NVME_IO_ENTRIES; 128 TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries); 129 130 /* 131 * NVMe spec sets a hard limit of 64K max entries, but 132 * devices may specify a smaller limit, so we need to check 133 * the MQES field in the capabilities register. 134 */ 135 cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo); 136 num_entries = min(num_entries, cap_lo.bits.mqes+1); 137 138 num_trackers = NVME_IO_TRACKERS; 139 TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers); 140 141 num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS); 142 num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS); 143 /* 144 * No need to have more trackers than entries in the submit queue. 145 * Note also that for a queue size of N, we can only have (N-1) 146 * commands outstanding, hence the "-1" here. 147 */ 148 num_trackers = min(num_trackers, (num_entries-1)); 149 150 /* 151 * Our best estimate for the maximum number of I/Os that we should 152 * noramlly have in flight at one time. This should be viewed as a hint, 153 * not a hard limit and will need to be revisitted when the upper layers 154 * of the storage system grows multi-queue support. 155 */ 156 ctrlr->max_hw_pend_io = num_trackers * ctrlr->num_io_queues * 3 / 4; 157 158 /* 159 * This was calculated previously when setting up interrupts, but 160 * a controller could theoretically support fewer I/O queues than 161 * MSI-X vectors. So calculate again here just to be safe. 162 */ 163 ctrlr->num_cpus_per_ioq = howmany(mp_ncpus, ctrlr->num_io_queues); 164 165 ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair), 166 M_NVME, M_ZERO | M_WAITOK); 167 168 for (i = 0; i < ctrlr->num_io_queues; i++) { 169 qpair = &ctrlr->ioq[i]; 170 171 /* 172 * Admin queue has ID=0. IO queues start at ID=1 - 173 * hence the 'i+1' here. 174 * 175 * For I/O queues, use the controller-wide max_xfer_size 176 * calculated in nvme_attach(). 177 */ 178 error = nvme_qpair_construct(qpair, 179 i+1, /* qpair ID */ 180 ctrlr->msix_enabled ? i+1 : 0, /* vector */ 181 num_entries, 182 num_trackers, 183 ctrlr); 184 if (error) 185 return (error); 186 187 /* 188 * Do not bother binding interrupts if we only have one I/O 189 * interrupt thread for this controller. 190 */ 191 if (ctrlr->num_io_queues > 1) 192 bus_bind_intr(ctrlr->dev, qpair->res, 193 i * ctrlr->num_cpus_per_ioq); 194 } 195 196 return (0); 197} 198 199static void 200nvme_ctrlr_fail(struct nvme_controller *ctrlr) 201{ 202 int i; 203 204 ctrlr->is_failed = TRUE; 205 nvme_qpair_fail(&ctrlr->adminq); 206 if (ctrlr->ioq != NULL) { 207 for (i = 0; i < ctrlr->num_io_queues; i++) 208 nvme_qpair_fail(&ctrlr->ioq[i]); 209 } 210 nvme_notify_fail_consumers(ctrlr); 211} 212 213void 214nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 215 struct nvme_request *req) 216{ 217 218 mtx_lock(&ctrlr->lock); 219 STAILQ_INSERT_TAIL(&ctrlr->fail_req, req, stailq); 220 mtx_unlock(&ctrlr->lock); 221 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->fail_req_task); 222} 223 224static void 225nvme_ctrlr_fail_req_task(void *arg, int pending) 226{ 227 struct nvme_controller *ctrlr = arg; 228 struct nvme_request *req; 229 230 mtx_lock(&ctrlr->lock); 231 while (!STAILQ_EMPTY(&ctrlr->fail_req)) { 232 req = STAILQ_FIRST(&ctrlr->fail_req); 233 STAILQ_REMOVE_HEAD(&ctrlr->fail_req, stailq); 234 nvme_qpair_manual_complete_request(req->qpair, req, 235 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, TRUE); 236 } 237 mtx_unlock(&ctrlr->lock); 238} 239 240static int 241nvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr, int desired_val) 242{ 243 int ms_waited; 244 union csts_register csts; 245 246 csts.raw = nvme_mmio_read_4(ctrlr, csts); 247 248 ms_waited = 0; 249 while (csts.bits.rdy != desired_val) { 250 if (ms_waited++ > ctrlr->ready_timeout_in_ms) { 251 nvme_printf(ctrlr, "controller ready did not become %d " 252 "within %d ms\n", desired_val, ctrlr->ready_timeout_in_ms); 253 return (ENXIO); 254 } 255 DELAY(1000); 256 csts.raw = nvme_mmio_read_4(ctrlr, csts); 257 } 258 259 return (0); 260} 261 262static int 263nvme_ctrlr_disable(struct nvme_controller *ctrlr) 264{ 265 union cc_register cc; 266 union csts_register csts; 267 int err; 268 269 cc.raw = nvme_mmio_read_4(ctrlr, cc); 270 csts.raw = nvme_mmio_read_4(ctrlr, csts); 271 272 /* 273 * Per 3.1.5 in NVME 1.3 spec, transitioning CC.EN from 0 to 1 274 * when CSTS.RDY is 1 or transitioning CC.EN from 1 to 0 when 275 * CSTS.RDY is 0 "has undefined results" So make sure that CSTS.RDY 276 * isn't the desired value. Short circuit if we're already disabled. 277 */ 278 if (cc.bits.en == 1) { 279 if (csts.bits.rdy == 0) { 280 /* EN == 1, wait for RDY == 1 or fail */ 281 err = nvme_ctrlr_wait_for_ready(ctrlr, 1); 282 if (err != 0) 283 return (err); 284 } 285 } else { 286 /* EN == 0 already wait for RDY == 0 */ 287 if (csts.bits.rdy == 0) 288 return (0); 289 else 290 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 291 } 292 293 cc.bits.en = 0; 294 nvme_mmio_write_4(ctrlr, cc, cc.raw); 295 /* 296 * Some drives have issues with accessing the mmio after we 297 * disable, so delay for a bit after we write the bit to 298 * cope with these issues. 299 */ 300 if (ctrlr->quirks & QUIRK_DELAY_B4_CHK_RDY) 301 pause("nvmeR", B4_CHK_RDY_DELAY_MS * hz / 1000); 302 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 303} 304 305static int 306nvme_ctrlr_enable(struct nvme_controller *ctrlr) 307{ 308 union cc_register cc; 309 union csts_register csts; 310 union aqa_register aqa; 311 int err; 312 313 cc.raw = nvme_mmio_read_4(ctrlr, cc); 314 csts.raw = nvme_mmio_read_4(ctrlr, csts); 315 316 /* 317 * See note in nvme_ctrlr_disable. Short circuit if we're already enabled. 318 */ 319 if (cc.bits.en == 1) { 320 if (csts.bits.rdy == 1) 321 return (0); 322 else 323 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 324 } else { 325 /* EN == 0 already wait for RDY == 0 or fail */ 326 err = nvme_ctrlr_wait_for_ready(ctrlr, 0); 327 if (err != 0) 328 return (err); 329 } 330 331 nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr); 332 DELAY(5000); 333 nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr); 334 DELAY(5000); 335 336 aqa.raw = 0; 337 /* acqs and asqs are 0-based. */ 338 aqa.bits.acqs = ctrlr->adminq.num_entries-1; 339 aqa.bits.asqs = ctrlr->adminq.num_entries-1; 340 nvme_mmio_write_4(ctrlr, aqa, aqa.raw); 341 DELAY(5000); 342 343 cc.bits.en = 1; 344 cc.bits.css = 0; 345 cc.bits.ams = 0; 346 cc.bits.shn = 0; 347 cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */ 348 cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */ 349 350 /* This evaluates to 0, which is according to spec. */ 351 cc.bits.mps = (PAGE_SIZE >> 13); 352 353 nvme_mmio_write_4(ctrlr, cc, cc.raw); 354 355 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 356} 357 358int 359nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr) 360{ 361 int i, err; 362 363 nvme_admin_qpair_disable(&ctrlr->adminq); 364 /* 365 * I/O queues are not allocated before the initial HW 366 * reset, so do not try to disable them. Use is_initialized 367 * to determine if this is the initial HW reset. 368 */ 369 if (ctrlr->is_initialized) { 370 for (i = 0; i < ctrlr->num_io_queues; i++) 371 nvme_io_qpair_disable(&ctrlr->ioq[i]); 372 } 373 374 DELAY(100*1000); 375 376 err = nvme_ctrlr_disable(ctrlr); 377 if (err != 0) 378 return err; 379 return (nvme_ctrlr_enable(ctrlr)); 380} 381 382void 383nvme_ctrlr_reset(struct nvme_controller *ctrlr) 384{ 385 int cmpset; 386 387 cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1); 388 389 if (cmpset == 0 || ctrlr->is_failed) 390 /* 391 * Controller is already resetting or has failed. Return 392 * immediately since there is no need to kick off another 393 * reset in these cases. 394 */ 395 return; 396 397 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task); 398} 399 400static int 401nvme_ctrlr_identify(struct nvme_controller *ctrlr) 402{ 403 struct nvme_completion_poll_status status; 404 405 status.done = 0; 406 nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata, 407 nvme_completion_poll_cb, &status); 408 while (!atomic_load_acq_int(&status.done)) 409 pause("nvme", 1); 410 if (nvme_completion_is_error(&status.cpl)) { 411 nvme_printf(ctrlr, "nvme_identify_controller failed!\n"); 412 return (ENXIO); 413 } 414 415 /* 416 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the 417 * controller supports. 418 */ 419 if (ctrlr->cdata.mdts > 0) 420 ctrlr->max_xfer_size = min(ctrlr->max_xfer_size, 421 ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts))); 422 423 return (0); 424} 425 426static int 427nvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr) 428{ 429 struct nvme_completion_poll_status status; 430 int cq_allocated, sq_allocated; 431 432 status.done = 0; 433 nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues, 434 nvme_completion_poll_cb, &status); 435 while (!atomic_load_acq_int(&status.done)) 436 pause("nvme", 1); 437 if (nvme_completion_is_error(&status.cpl)) { 438 nvme_printf(ctrlr, "nvme_ctrlr_set_num_qpairs failed!\n"); 439 return (ENXIO); 440 } 441 442 /* 443 * Data in cdw0 is 0-based. 444 * Lower 16-bits indicate number of submission queues allocated. 445 * Upper 16-bits indicate number of completion queues allocated. 446 */ 447 sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1; 448 cq_allocated = (status.cpl.cdw0 >> 16) + 1; 449 450 /* 451 * Controller may allocate more queues than we requested, 452 * so use the minimum of the number requested and what was 453 * actually allocated. 454 */ 455 ctrlr->num_io_queues = min(ctrlr->num_io_queues, sq_allocated); 456 ctrlr->num_io_queues = min(ctrlr->num_io_queues, cq_allocated); 457 458 return (0); 459} 460 461static int 462nvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr) 463{ 464 struct nvme_completion_poll_status status; 465 struct nvme_qpair *qpair; 466 int i; 467 468 for (i = 0; i < ctrlr->num_io_queues; i++) { 469 qpair = &ctrlr->ioq[i]; 470 471 status.done = 0; 472 nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair, qpair->vector, 473 nvme_completion_poll_cb, &status); 474 while (!atomic_load_acq_int(&status.done)) 475 pause("nvme", 1); 476 if (nvme_completion_is_error(&status.cpl)) { 477 nvme_printf(ctrlr, "nvme_create_io_cq failed!\n"); 478 return (ENXIO); 479 } 480 481 status.done = 0; 482 nvme_ctrlr_cmd_create_io_sq(qpair->ctrlr, qpair, 483 nvme_completion_poll_cb, &status); 484 while (!atomic_load_acq_int(&status.done)) 485 pause("nvme", 1); 486 if (nvme_completion_is_error(&status.cpl)) { 487 nvme_printf(ctrlr, "nvme_create_io_sq failed!\n"); 488 return (ENXIO); 489 } 490 } 491 492 return (0); 493} 494 495static int 496nvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr) 497{ 498 struct nvme_namespace *ns; 499 uint32_t i; 500 501 for (i = 0; i < min(ctrlr->cdata.nn, NVME_MAX_NAMESPACES); i++) { 502 ns = &ctrlr->ns[i]; 503 nvme_ns_construct(ns, i+1, ctrlr); 504 } 505 506 return (0); 507} 508 509static boolean_t 510is_log_page_id_valid(uint8_t page_id) 511{ 512 513 switch (page_id) { 514 case NVME_LOG_ERROR: 515 case NVME_LOG_HEALTH_INFORMATION: 516 case NVME_LOG_FIRMWARE_SLOT: 517 return (TRUE); 518 } 519 520 return (FALSE); 521} 522 523static uint32_t 524nvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id) 525{ 526 uint32_t log_page_size; 527 528 switch (page_id) { 529 case NVME_LOG_ERROR: 530 log_page_size = min( 531 sizeof(struct nvme_error_information_entry) * 532 ctrlr->cdata.elpe, 533 NVME_MAX_AER_LOG_SIZE); 534 break; 535 case NVME_LOG_HEALTH_INFORMATION: 536 log_page_size = sizeof(struct nvme_health_information_page); 537 break; 538 case NVME_LOG_FIRMWARE_SLOT: 539 log_page_size = sizeof(struct nvme_firmware_page); 540 break; 541 default: 542 log_page_size = 0; 543 break; 544 } 545 546 return (log_page_size); 547} 548 549static void 550nvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr, 551 union nvme_critical_warning_state state) 552{ 553 554 if (state.bits.available_spare == 1) 555 nvme_printf(ctrlr, "available spare space below threshold\n"); 556 557 if (state.bits.temperature == 1) 558 nvme_printf(ctrlr, "temperature above threshold\n"); 559 560 if (state.bits.device_reliability == 1) 561 nvme_printf(ctrlr, "device reliability degraded\n"); 562 563 if (state.bits.read_only == 1) 564 nvme_printf(ctrlr, "media placed in read only mode\n"); 565 566 if (state.bits.volatile_memory_backup == 1) 567 nvme_printf(ctrlr, "volatile memory backup device failed\n"); 568 569 if (state.bits.reserved != 0) 570 nvme_printf(ctrlr, 571 "unknown critical warning(s): state = 0x%02x\n", state.raw); 572} 573 574static void 575nvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl) 576{ 577 struct nvme_async_event_request *aer = arg; 578 struct nvme_health_information_page *health_info; 579 580 /* 581 * If the log page fetch for some reason completed with an error, 582 * don't pass log page data to the consumers. In practice, this case 583 * should never happen. 584 */ 585 if (nvme_completion_is_error(cpl)) 586 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 587 aer->log_page_id, NULL, 0); 588 else { 589 if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) { 590 health_info = (struct nvme_health_information_page *) 591 aer->log_page_buffer; 592 nvme_ctrlr_log_critical_warnings(aer->ctrlr, 593 health_info->critical_warning); 594 /* 595 * Critical warnings reported through the 596 * SMART/health log page are persistent, so 597 * clear the associated bits in the async event 598 * config so that we do not receive repeated 599 * notifications for the same event. 600 */ 601 aer->ctrlr->async_event_config.raw &= 602 ~health_info->critical_warning.raw; 603 nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr, 604 aer->ctrlr->async_event_config, NULL, NULL); 605 } 606 607 608 /* 609 * Pass the cpl data from the original async event completion, 610 * not the log page fetch. 611 */ 612 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 613 aer->log_page_id, aer->log_page_buffer, aer->log_page_size); 614 } 615 616 /* 617 * Repost another asynchronous event request to replace the one 618 * that just completed. 619 */ 620 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 621} 622 623static void 624nvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl) 625{ 626 struct nvme_async_event_request *aer = arg; 627 628 if (nvme_completion_is_error(cpl)) { 629 /* 630 * Do not retry failed async event requests. This avoids 631 * infinite loops where a new async event request is submitted 632 * to replace the one just failed, only to fail again and 633 * perpetuate the loop. 634 */ 635 return; 636 } 637 638 /* Associated log page is in bits 23:16 of completion entry dw0. */ 639 aer->log_page_id = (cpl->cdw0 & 0xFF0000) >> 16; 640 641 nvme_printf(aer->ctrlr, "async event occurred (log page id=0x%x)\n", 642 aer->log_page_id); 643 644 if (is_log_page_id_valid(aer->log_page_id)) { 645 aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr, 646 aer->log_page_id); 647 memcpy(&aer->cpl, cpl, sizeof(*cpl)); 648 nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id, 649 NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer, 650 aer->log_page_size, nvme_ctrlr_async_event_log_page_cb, 651 aer); 652 /* Wait to notify consumers until after log page is fetched. */ 653 } else { 654 nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id, 655 NULL, 0); 656 657 /* 658 * Repost another asynchronous event request to replace the one 659 * that just completed. 660 */ 661 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 662 } 663} 664 665static void 666nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 667 struct nvme_async_event_request *aer) 668{ 669 struct nvme_request *req; 670 671 aer->ctrlr = ctrlr; 672 req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer); 673 aer->req = req; 674 675 /* 676 * Disable timeout here, since asynchronous event requests should by 677 * nature never be timed out. 678 */ 679 req->timeout = FALSE; 680 req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST; 681 nvme_ctrlr_submit_admin_request(ctrlr, req); 682} 683 684static void 685nvme_ctrlr_configure_aer(struct nvme_controller *ctrlr) 686{ 687 struct nvme_completion_poll_status status; 688 struct nvme_async_event_request *aer; 689 uint32_t i; 690 691 ctrlr->async_event_config.raw = 0xFF; 692 ctrlr->async_event_config.bits.reserved = 0; 693 694 status.done = 0; 695 nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD, 696 0, NULL, 0, nvme_completion_poll_cb, &status); 697 while (!atomic_load_acq_int(&status.done)) 698 pause("nvme", 1); 699 if (nvme_completion_is_error(&status.cpl) || 700 (status.cpl.cdw0 & 0xFFFF) == 0xFFFF || 701 (status.cpl.cdw0 & 0xFFFF) == 0x0000) { 702 nvme_printf(ctrlr, "temperature threshold not supported\n"); 703 ctrlr->async_event_config.bits.temperature = 0; 704 } 705 706 nvme_ctrlr_cmd_set_async_event_config(ctrlr, 707 ctrlr->async_event_config, NULL, NULL); 708 709 /* aerl is a zero-based value, so we need to add 1 here. */ 710 ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1)); 711 712 for (i = 0; i < ctrlr->num_aers; i++) { 713 aer = &ctrlr->aer[i]; 714 nvme_ctrlr_construct_and_submit_aer(ctrlr, aer); 715 } 716} 717 718static void 719nvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr) 720{ 721 722 ctrlr->int_coal_time = 0; 723 TUNABLE_INT_FETCH("hw.nvme.int_coal_time", 724 &ctrlr->int_coal_time); 725 726 ctrlr->int_coal_threshold = 0; 727 TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold", 728 &ctrlr->int_coal_threshold); 729 730 nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time, 731 ctrlr->int_coal_threshold, NULL, NULL); 732} 733 734static void 735nvme_ctrlr_start(void *ctrlr_arg) 736{ 737 struct nvme_controller *ctrlr = ctrlr_arg; 738 uint32_t old_num_io_queues; 739 int i; 740 741 /* 742 * Only reset adminq here when we are restarting the 743 * controller after a reset. During initialization, 744 * we have already submitted admin commands to get 745 * the number of I/O queues supported, so cannot reset 746 * the adminq again here. 747 */ 748 if (ctrlr->is_resetting) { 749 nvme_qpair_reset(&ctrlr->adminq); 750 } 751 752 for (i = 0; i < ctrlr->num_io_queues; i++) 753 nvme_qpair_reset(&ctrlr->ioq[i]); 754 755 nvme_admin_qpair_enable(&ctrlr->adminq); 756 757 if (nvme_ctrlr_identify(ctrlr) != 0) { 758 nvme_ctrlr_fail(ctrlr); 759 return; 760 } 761 762 /* 763 * The number of qpairs are determined during controller initialization, 764 * including using NVMe SET_FEATURES/NUMBER_OF_QUEUES to determine the 765 * HW limit. We call SET_FEATURES again here so that it gets called 766 * after any reset for controllers that depend on the driver to 767 * explicit specify how many queues it will use. This value should 768 * never change between resets, so panic if somehow that does happen. 769 */ 770 if (ctrlr->is_resetting) { 771 old_num_io_queues = ctrlr->num_io_queues; 772 if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) { 773 nvme_ctrlr_fail(ctrlr); 774 return; 775 } 776 777 if (old_num_io_queues != ctrlr->num_io_queues) { 778 panic("num_io_queues changed from %u to %u", 779 old_num_io_queues, ctrlr->num_io_queues); 780 } 781 } 782 783 if (nvme_ctrlr_create_qpairs(ctrlr) != 0) { 784 nvme_ctrlr_fail(ctrlr); 785 return; 786 } 787 788 if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) { 789 nvme_ctrlr_fail(ctrlr); 790 return; 791 } 792 793 nvme_ctrlr_configure_aer(ctrlr); 794 nvme_ctrlr_configure_int_coalescing(ctrlr); 795 796 for (i = 0; i < ctrlr->num_io_queues; i++) 797 nvme_io_qpair_enable(&ctrlr->ioq[i]); 798} 799 800void 801nvme_ctrlr_start_config_hook(void *arg) 802{ 803 struct nvme_controller *ctrlr = arg; 804 805 nvme_qpair_reset(&ctrlr->adminq); 806 nvme_admin_qpair_enable(&ctrlr->adminq); 807 808 if (nvme_ctrlr_set_num_qpairs(ctrlr) == 0 && 809 nvme_ctrlr_construct_io_qpairs(ctrlr) == 0) 810 nvme_ctrlr_start(ctrlr); 811 else 812 nvme_ctrlr_fail(ctrlr); 813 814 nvme_sysctl_initialize_ctrlr(ctrlr); 815 config_intrhook_disestablish(&ctrlr->config_hook); 816 817 ctrlr->is_initialized = 1; 818 nvme_notify_new_controller(ctrlr); 819} 820 821static void 822nvme_ctrlr_reset_task(void *arg, int pending) 823{ 824 struct nvme_controller *ctrlr = arg; 825 int status; 826 827 nvme_printf(ctrlr, "resetting controller\n"); 828 status = nvme_ctrlr_hw_reset(ctrlr); 829 /* 830 * Use pause instead of DELAY, so that we yield to any nvme interrupt 831 * handlers on this CPU that were blocked on a qpair lock. We want 832 * all nvme interrupts completed before proceeding with restarting the 833 * controller. 834 * 835 * XXX - any way to guarantee the interrupt handlers have quiesced? 836 */ 837 pause("nvmereset", hz / 10); 838 if (status == 0) 839 nvme_ctrlr_start(ctrlr); 840 else 841 nvme_ctrlr_fail(ctrlr); 842 843 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 844} 845 846/* 847 * Poll all the queues enabled on the device for completion. 848 */ 849void 850nvme_ctrlr_poll(struct nvme_controller *ctrlr) 851{ 852 int i; 853 854 nvme_qpair_process_completions(&ctrlr->adminq); 855 856 for (i = 0; i < ctrlr->num_io_queues; i++) 857 if (ctrlr->ioq && ctrlr->ioq[i].cpl) 858 nvme_qpair_process_completions(&ctrlr->ioq[i]); 859} 860 861/* 862 * Poll the single-vector intertrupt case: num_io_queues will be 1 and 863 * there's only a single vector. While we're polling, we mask further 864 * interrupts in the controller. 865 */ 866void 867nvme_ctrlr_intx_handler(void *arg) 868{ 869 struct nvme_controller *ctrlr = arg; 870 871 nvme_mmio_write_4(ctrlr, intms, 1); 872 nvme_ctrlr_poll(ctrlr); 873 nvme_mmio_write_4(ctrlr, intmc, 1); 874} 875 876static int 877nvme_ctrlr_configure_intx(struct nvme_controller *ctrlr) 878{ 879 880 ctrlr->msix_enabled = 0; 881 ctrlr->num_io_queues = 1; 882 ctrlr->num_cpus_per_ioq = mp_ncpus; 883 ctrlr->rid = 0; 884 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 885 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); 886 887 if (ctrlr->res == NULL) { 888 nvme_printf(ctrlr, "unable to allocate shared IRQ\n"); 889 return (ENOMEM); 890 } 891 892 bus_setup_intr(ctrlr->dev, ctrlr->res, 893 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler, 894 ctrlr, &ctrlr->tag); 895 896 if (ctrlr->tag == NULL) { 897 nvme_printf(ctrlr, "unable to setup intx handler\n"); 898 return (ENOMEM); 899 } 900 901 return (0); 902} 903 904static void 905nvme_pt_done(void *arg, const struct nvme_completion *cpl) 906{ 907 struct nvme_pt_command *pt = arg; 908 909 bzero(&pt->cpl, sizeof(pt->cpl)); 910 pt->cpl.cdw0 = cpl->cdw0; 911 pt->cpl.status = cpl->status; 912 pt->cpl.status.p = 0; 913 914 mtx_lock(pt->driver_lock); 915 wakeup(pt); 916 mtx_unlock(pt->driver_lock); 917} 918 919int 920nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 921 struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer, 922 int is_admin_cmd) 923{ 924 struct nvme_request *req; 925 struct mtx *mtx; 926 struct buf *buf = NULL; 927 int ret = 0; 928 vm_offset_t addr, end; 929 930 if (pt->len > 0) { 931 /* 932 * vmapbuf calls vm_fault_quick_hold_pages which only maps full 933 * pages. Ensure this request has fewer than MAXPHYS bytes when 934 * extended to full pages. 935 */ 936 addr = (vm_offset_t)pt->buf; 937 end = round_page(addr + pt->len); 938 addr = trunc_page(addr); 939 if (end - addr > MAXPHYS) 940 return EIO; 941 942 if (pt->len > ctrlr->max_xfer_size) { 943 nvme_printf(ctrlr, "pt->len (%d) " 944 "exceeds max_xfer_size (%d)\n", pt->len, 945 ctrlr->max_xfer_size); 946 return EIO; 947 } 948 if (is_user_buffer) { 949 /* 950 * Ensure the user buffer is wired for the duration of 951 * this passthrough command. 952 */ 953 PHOLD(curproc); 954 buf = getpbuf(NULL); 955 buf->b_data = pt->buf; 956 buf->b_bufsize = pt->len; 957 buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE; 958#ifdef NVME_UNMAPPED_BIO_SUPPORT 959 if (vmapbuf(buf, 1) < 0) { 960#else 961 if (vmapbuf(buf) < 0) { 962#endif 963 ret = EFAULT; 964 goto err; 965 } 966 req = nvme_allocate_request_vaddr(buf->b_data, pt->len, 967 nvme_pt_done, pt); 968 } else 969 req = nvme_allocate_request_vaddr(pt->buf, pt->len, 970 nvme_pt_done, pt); 971 } else 972 req = nvme_allocate_request_null(nvme_pt_done, pt); 973 974 req->cmd.opc = pt->cmd.opc; 975 req->cmd.cdw10 = pt->cmd.cdw10; 976 req->cmd.cdw11 = pt->cmd.cdw11; 977 req->cmd.cdw12 = pt->cmd.cdw12; 978 req->cmd.cdw13 = pt->cmd.cdw13; 979 req->cmd.cdw14 = pt->cmd.cdw14; 980 req->cmd.cdw15 = pt->cmd.cdw15; 981 982 req->cmd.nsid = nsid; 983 984 if (is_admin_cmd) 985 mtx = &ctrlr->lock; 986 else 987 mtx = &ctrlr->ns[nsid-1].lock; 988 989 mtx_lock(mtx); 990 pt->driver_lock = mtx; 991 992 if (is_admin_cmd) 993 nvme_ctrlr_submit_admin_request(ctrlr, req); 994 else 995 nvme_ctrlr_submit_io_request(ctrlr, req); 996 997 mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0); 998 mtx_unlock(mtx); 999 1000 pt->driver_lock = NULL; 1001 1002err: 1003 if (buf != NULL) { 1004 relpbuf(buf, NULL); 1005 PRELE(curproc); 1006 } 1007 1008 return (ret); 1009} 1010 1011static int 1012nvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag, 1013 struct thread *td) 1014{ 1015 struct nvme_controller *ctrlr; 1016 struct nvme_pt_command *pt; 1017 1018 ctrlr = cdev->si_drv1; 1019 1020 switch (cmd) { 1021 case NVME_RESET_CONTROLLER: 1022 nvme_ctrlr_reset(ctrlr); 1023 break; 1024 case NVME_PASSTHROUGH_CMD: 1025 pt = (struct nvme_pt_command *)arg; 1026 return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, pt->cmd.nsid, 1027 1 /* is_user_buffer */, 1 /* is_admin_cmd */)); 1028 default: 1029 return (ENOTTY); 1030 } 1031 1032 return (0); 1033} 1034 1035static struct cdevsw nvme_ctrlr_cdevsw = { 1036 .d_version = D_VERSION, 1037 .d_flags = 0, 1038 .d_ioctl = nvme_ctrlr_ioctl 1039}; 1040 1041static void 1042nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr) 1043{ 1044 device_t dev; 1045 int per_cpu_io_queues; 1046 int min_cpus_per_ioq; 1047 int num_vectors_requested, num_vectors_allocated; 1048 int num_vectors_available; 1049 1050 dev = ctrlr->dev; 1051 min_cpus_per_ioq = 1; 1052 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq); 1053 1054 if (min_cpus_per_ioq < 1) { 1055 min_cpus_per_ioq = 1; 1056 } else if (min_cpus_per_ioq > mp_ncpus) { 1057 min_cpus_per_ioq = mp_ncpus; 1058 } 1059 1060 per_cpu_io_queues = 1; 1061 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); 1062 1063 if (per_cpu_io_queues == 0) { 1064 min_cpus_per_ioq = mp_ncpus; 1065 } 1066 1067 ctrlr->force_intx = 0; 1068 TUNABLE_INT_FETCH("hw.nvme.force_intx", &ctrlr->force_intx); 1069 1070 /* 1071 * FreeBSD currently cannot allocate more than about 190 vectors at 1072 * boot, meaning that systems with high core count and many devices 1073 * requesting per-CPU interrupt vectors will not get their full 1074 * allotment. So first, try to allocate as many as we may need to 1075 * understand what is available, then immediately release them. 1076 * Then figure out how many of those we will actually use, based on 1077 * assigning an equal number of cores to each I/O queue. 1078 */ 1079 1080 /* One vector for per core I/O queue, plus one vector for admin queue. */ 1081 num_vectors_available = min(pci_msix_count(dev), mp_ncpus + 1); 1082 if (pci_alloc_msix(dev, &num_vectors_available) != 0) { 1083 num_vectors_available = 0; 1084 } 1085 pci_release_msi(dev); 1086 1087 if (ctrlr->force_intx || num_vectors_available < 2) { 1088 nvme_ctrlr_configure_intx(ctrlr); 1089 return; 1090 } 1091 1092 /* 1093 * Do not use all vectors for I/O queues - one must be saved for the 1094 * admin queue. 1095 */ 1096 ctrlr->num_cpus_per_ioq = max(min_cpus_per_ioq, 1097 howmany(mp_ncpus, num_vectors_available - 1)); 1098 1099 ctrlr->num_io_queues = howmany(mp_ncpus, ctrlr->num_cpus_per_ioq); 1100 num_vectors_requested = ctrlr->num_io_queues + 1; 1101 num_vectors_allocated = num_vectors_requested; 1102 1103 /* 1104 * Now just allocate the number of vectors we need. This should 1105 * succeed, since we previously called pci_alloc_msix() 1106 * successfully returning at least this many vectors, but just to 1107 * be safe, if something goes wrong just revert to INTx. 1108 */ 1109 if (pci_alloc_msix(dev, &num_vectors_allocated) != 0) { 1110 nvme_ctrlr_configure_intx(ctrlr); 1111 return; 1112 } 1113 1114 if (num_vectors_allocated < num_vectors_requested) { 1115 pci_release_msi(dev); 1116 nvme_ctrlr_configure_intx(ctrlr); 1117 return; 1118 } 1119 1120 ctrlr->msix_enabled = 1; 1121} 1122 1123int 1124nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev) 1125{ 1126 union cap_lo_register cap_lo; 1127 union cap_hi_register cap_hi; 1128 int status, timeout_period; 1129 1130 ctrlr->dev = dev; 1131 1132 mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF); 1133 1134 status = nvme_ctrlr_allocate_bar(ctrlr); 1135 1136 if (status != 0) 1137 return (status); 1138 1139 /* 1140 * Software emulators may set the doorbell stride to something 1141 * other than zero, but this driver is not set up to handle that. 1142 */ 1143 cap_hi.raw = nvme_mmio_read_4(ctrlr, cap_hi); 1144 if (cap_hi.bits.dstrd != 0) 1145 return (ENXIO); 1146 1147 ctrlr->min_page_size = 1 << (12 + cap_hi.bits.mpsmin); 1148 1149 /* Get ready timeout value from controller, in units of 500ms. */ 1150 cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo); 1151 ctrlr->ready_timeout_in_ms = cap_lo.bits.to * 500; 1152 1153 timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD; 1154 TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period); 1155 timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD); 1156 timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD); 1157 ctrlr->timeout_period = timeout_period; 1158 1159 nvme_retry_count = NVME_DEFAULT_RETRY_COUNT; 1160 TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count); 1161 1162 ctrlr->enable_aborts = 0; 1163 TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts); 1164 1165 nvme_ctrlr_setup_interrupts(ctrlr); 1166 1167 ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE; 1168 if (nvme_ctrlr_construct_admin_qpair(ctrlr) != 0) 1169 return (ENXIO); 1170 1171 ctrlr->cdev = make_dev(&nvme_ctrlr_cdevsw, device_get_unit(dev), 1172 UID_ROOT, GID_WHEEL, 0600, "nvme%d", device_get_unit(dev)); 1173 1174 if (ctrlr->cdev == NULL) 1175 return (ENXIO); 1176 1177 ctrlr->cdev->si_drv1 = (void *)ctrlr; 1178 1179 ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK, 1180 taskqueue_thread_enqueue, &ctrlr->taskqueue); 1181 taskqueue_start_threads(&ctrlr->taskqueue, 1, PI_DISK, "nvme taskq"); 1182 1183 ctrlr->is_resetting = 0; 1184 ctrlr->is_initialized = 0; 1185 ctrlr->notification_sent = 0; 1186 TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr); 1187 1188 TASK_INIT(&ctrlr->fail_req_task, 0, nvme_ctrlr_fail_req_task, ctrlr); 1189 STAILQ_INIT(&ctrlr->fail_req); 1190 ctrlr->is_failed = FALSE; 1191 1192 return (0); 1193} 1194 1195void 1196nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev) 1197{ 1198 int i; 1199 1200 /* 1201 * Notify the controller of a shutdown, even though this is due to 1202 * a driver unload, not a system shutdown (this path is not invoked 1203 * during shutdown). This ensures the controller receives a 1204 * shutdown notification in case the system is shutdown before 1205 * reloading the driver. 1206 */ 1207 nvme_ctrlr_shutdown(ctrlr); 1208 1209 nvme_ctrlr_disable(ctrlr); 1210 taskqueue_free(ctrlr->taskqueue); 1211 1212 for (i = 0; i < NVME_MAX_NAMESPACES; i++) 1213 nvme_ns_destruct(&ctrlr->ns[i]); 1214 1215 if (ctrlr->cdev) 1216 destroy_dev(ctrlr->cdev); 1217 1218 for (i = 0; i < ctrlr->num_io_queues; i++) { 1219 nvme_io_qpair_destroy(&ctrlr->ioq[i]); 1220 } 1221 1222 free(ctrlr->ioq, M_NVME); 1223 1224 nvme_admin_qpair_destroy(&ctrlr->adminq); 1225 1226 if (ctrlr->resource != NULL) { 1227 bus_release_resource(dev, SYS_RES_MEMORY, 1228 ctrlr->resource_id, ctrlr->resource); 1229 } 1230 1231 if (ctrlr->bar4_resource != NULL) { 1232 bus_release_resource(dev, SYS_RES_MEMORY, 1233 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 1234 } 1235 1236 if (ctrlr->tag) 1237 bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag); 1238 1239 if (ctrlr->res) 1240 bus_release_resource(ctrlr->dev, SYS_RES_IRQ, 1241 rman_get_rid(ctrlr->res), ctrlr->res); 1242 1243 if (ctrlr->msix_enabled) 1244 pci_release_msi(dev); 1245} 1246 1247void 1248nvme_ctrlr_shutdown(struct nvme_controller *ctrlr) 1249{ 1250 union cc_register cc; 1251 union csts_register csts; 1252 int ticks = 0; 1253 1254 cc.raw = nvme_mmio_read_4(ctrlr, cc); 1255 cc.bits.shn = NVME_SHN_NORMAL; 1256 nvme_mmio_write_4(ctrlr, cc, cc.raw); 1257 csts.raw = nvme_mmio_read_4(ctrlr, csts); 1258 while ((csts.bits.shst != NVME_SHST_COMPLETE) && (ticks++ < 5*hz)) { 1259 pause("nvme shn", 1); 1260 csts.raw = nvme_mmio_read_4(ctrlr, csts); 1261 } 1262 if (csts.bits.shst != NVME_SHST_COMPLETE) 1263 nvme_printf(ctrlr, "did not complete shutdown within 5 seconds " 1264 "of notification\n"); 1265} 1266 1267void 1268nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 1269 struct nvme_request *req) 1270{ 1271 1272 nvme_qpair_submit_request(&ctrlr->adminq, req); 1273} 1274 1275void 1276nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 1277 struct nvme_request *req) 1278{ 1279 struct nvme_qpair *qpair; 1280 1281 qpair = &ctrlr->ioq[curcpu / ctrlr->num_cpus_per_ioq]; 1282 nvme_qpair_submit_request(qpair, req); 1283} 1284 1285device_t 1286nvme_ctrlr_get_device(struct nvme_controller *ctrlr) 1287{ 1288 1289 return (ctrlr->dev); 1290} 1291 1292const struct nvme_controller_data * 1293nvme_ctrlr_get_data(struct nvme_controller *ctrlr) 1294{ 1295 1296 return (&ctrlr->cdata); 1297} 1298