t4_msg.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/11/sys/dev/cxgbe/common/t4_msg.h 330897 2018-03-14 03:19:51Z eadler $ 29 * 30 */ 31 32#ifndef T4_MSG_H 33#define T4_MSG_H 34 35enum { 36 CPL_PASS_OPEN_REQ = 0x1, 37 CPL_PASS_ACCEPT_RPL = 0x2, 38 CPL_ACT_OPEN_REQ = 0x3, 39 CPL_SET_TCB = 0x4, 40 CPL_SET_TCB_FIELD = 0x5, 41 CPL_GET_TCB = 0x6, 42 CPL_CLOSE_CON_REQ = 0x8, 43 CPL_CLOSE_LISTSRV_REQ = 0x9, 44 CPL_ABORT_REQ = 0xA, 45 CPL_ABORT_RPL = 0xB, 46 CPL_TX_DATA = 0xC, 47 CPL_RX_DATA_ACK = 0xD, 48 CPL_TX_PKT = 0xE, 49 CPL_RTE_DELETE_REQ = 0xF, 50 CPL_RTE_WRITE_REQ = 0x10, 51 CPL_RTE_READ_REQ = 0x11, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_L2T_READ_REQ = 0x13, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TAG_WRITE_REQ = 0x16, 57 CPL_BARRIER = 0x18, 58 CPL_TID_RELEASE = 0x1A, 59 CPL_TAG_READ_REQ = 0x1B, 60 CPL_SRQ_TABLE_REQ = 0x1C, 61 CPL_TX_PKT_FSO = 0x1E, 62 CPL_TX_DATA_ISO = 0x1F, 63 64 CPL_CLOSE_LISTSRV_RPL = 0x20, 65 CPL_ERROR = 0x21, 66 CPL_GET_TCB_RPL = 0x22, 67 CPL_L2T_WRITE_RPL = 0x23, 68 CPL_PASS_OPEN_RPL = 0x24, 69 CPL_ACT_OPEN_RPL = 0x25, 70 CPL_PEER_CLOSE = 0x26, 71 CPL_RTE_DELETE_RPL = 0x27, 72 CPL_RTE_WRITE_RPL = 0x28, 73 CPL_RX_URG_PKT = 0x29, 74 CPL_TAG_WRITE_RPL = 0x2A, 75 CPL_ABORT_REQ_RSS = 0x2B, 76 CPL_RX_URG_NOTIFY = 0x2C, 77 CPL_ABORT_RPL_RSS = 0x2D, 78 CPL_SMT_WRITE_RPL = 0x2E, 79 CPL_TX_DATA_ACK = 0x2F, 80 81 CPL_RX_PHYS_ADDR = 0x30, 82 CPL_PCMD_READ_RPL = 0x31, 83 CPL_CLOSE_CON_RPL = 0x32, 84 CPL_ISCSI_HDR = 0x33, 85 CPL_L2T_READ_RPL = 0x34, 86 CPL_RDMA_CQE = 0x35, 87 CPL_RDMA_CQE_READ_RSP = 0x36, 88 CPL_RDMA_CQE_ERR = 0x37, 89 CPL_RTE_READ_RPL = 0x38, 90 CPL_RX_DATA = 0x39, 91 CPL_SET_TCB_RPL = 0x3A, 92 CPL_RX_PKT = 0x3B, 93 CPL_TAG_READ_RPL = 0x3C, 94 CPL_HIT_NOTIFY = 0x3D, 95 CPL_PKT_NOTIFY = 0x3E, 96 CPL_RX_DDP_COMPLETE = 0x3F, 97 98 CPL_ACT_ESTABLISH = 0x40, 99 CPL_PASS_ESTABLISH = 0x41, 100 CPL_RX_DATA_DDP = 0x42, 101 CPL_SMT_READ_RPL = 0x43, 102 CPL_PASS_ACCEPT_REQ = 0x44, 103 CPL_RX_ISCSI_CMP = 0x45, 104 CPL_RX_FCOE_DDP = 0x46, 105 CPL_FCOE_HDR = 0x47, 106 CPL_T5_TRACE_PKT = 0x48, 107 CPL_RX_ISCSI_DDP = 0x49, 108 CPL_RX_FCOE_DIF = 0x4A, 109 CPL_RX_DATA_DIF = 0x4B, 110 CPL_ERR_NOTIFY = 0x4D, 111 CPL_RX_TLS_CMP = 0x4E, 112 113 CPL_RDMA_READ_REQ = 0x60, 114 CPL_RX_ISCSI_DIF = 0x60, 115 116 CPL_SET_LE_REQ = 0x80, 117 CPL_PASS_OPEN_REQ6 = 0x81, 118 CPL_ACT_OPEN_REQ6 = 0x83, 119 CPL_TX_TLS_PDU = 0x88, 120 CPL_TX_TLS_SFO = 0x89, 121 122 CPL_TX_SEC_PDU = 0x8A, 123 CPL_TX_TLS_ACK = 0x8B, 124 125 CPL_RDMA_TERMINATE = 0xA2, 126 CPL_RDMA_WRITE = 0xA4, 127 CPL_SGE_EGR_UPDATE = 0xA5, 128 CPL_SET_LE_RPL = 0xA6, 129 CPL_FW2_MSG = 0xA7, 130 CPL_FW2_PLD = 0xA8, 131 CPL_T5_RDMA_READ_REQ = 0xA9, 132 CPL_RDMA_ATOMIC_REQ = 0xAA, 133 CPL_RDMA_ATOMIC_RPL = 0xAB, 134 CPL_RDMA_IMM_DATA = 0xAC, 135 CPL_RDMA_IMM_DATA_SE = 0xAD, 136 CPL_RX_MPS_PKT = 0xAF, 137 138 CPL_TRACE_PKT = 0xB0, 139 CPL_RX2TX_DATA = 0xB1, 140 CPL_TLS_DATA = 0xB1, 141 CPL_ISCSI_DATA = 0xB2, 142 CPL_FCOE_DATA = 0xB3, 143 144 CPL_FW4_MSG = 0xC0, 145 CPL_FW4_PLD = 0xC1, 146 CPL_FW4_ACK = 0xC3, 147 CPL_SRQ_TABLE_RPL = 0xCC, 148 CPL_RX_PHYS_DSGL = 0xD0, 149 150 CPL_FW6_MSG = 0xE0, 151 CPL_FW6_PLD = 0xE1, 152 CPL_TX_TNL_LSO = 0xEC, 153 CPL_TX_PKT_LSO = 0xED, 154 CPL_TX_PKT_XT = 0xEE, 155 156 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 157}; 158 159enum CPL_error { 160 CPL_ERR_NONE = 0, 161 CPL_ERR_TCAM_PARITY = 1, 162 CPL_ERR_TCAM_MISS = 2, 163 CPL_ERR_TCAM_FULL = 3, 164 CPL_ERR_BAD_LENGTH = 15, 165 CPL_ERR_BAD_ROUTE = 18, 166 CPL_ERR_CONN_RESET = 20, 167 CPL_ERR_CONN_EXIST_SYNRECV = 21, 168 CPL_ERR_CONN_EXIST = 22, 169 CPL_ERR_ARP_MISS = 23, 170 CPL_ERR_BAD_SYN = 24, 171 CPL_ERR_CONN_TIMEDOUT = 30, 172 CPL_ERR_XMIT_TIMEDOUT = 31, 173 CPL_ERR_PERSIST_TIMEDOUT = 32, 174 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 175 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 176 CPL_ERR_RTX_NEG_ADVICE = 35, 177 CPL_ERR_PERSIST_NEG_ADVICE = 36, 178 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 179 CPL_ERR_WAIT_ARP_RPL = 41, 180 CPL_ERR_ABORT_FAILED = 42, 181 CPL_ERR_IWARP_FLM = 50, 182 CPL_CONTAINS_READ_RPL = 60, 183 CPL_CONTAINS_WRITE_RPL = 61, 184}; 185 186/* 187 * Some of the error codes above implicitly indicate that there is no TID 188 * allocated with the result of an ACT_OPEN. We use this predicate to make 189 * that explicit. 190 */ 191static inline int act_open_has_tid(int status) 192{ 193 return (status != CPL_ERR_TCAM_PARITY && 194 status != CPL_ERR_TCAM_MISS && 195 status != CPL_ERR_TCAM_FULL && 196 status != CPL_ERR_CONN_EXIST_SYNRECV && 197 status != CPL_ERR_CONN_EXIST); 198} 199 200enum { 201 CPL_CONN_POLICY_AUTO = 0, 202 CPL_CONN_POLICY_ASK = 1, 203 CPL_CONN_POLICY_FILTER = 2, 204 CPL_CONN_POLICY_DENY = 3 205}; 206 207enum { 208 ULP_MODE_NONE = 0, 209 ULP_MODE_ISCSI = 2, 210 ULP_MODE_RDMA = 4, 211 ULP_MODE_TCPDDP = 5, 212 ULP_MODE_FCOE = 6, 213 ULP_MODE_TLS = 8, 214}; 215 216enum { 217 ULP_CRC_HEADER = 1 << 0, 218 ULP_CRC_DATA = 1 << 1 219}; 220 221enum { 222 CPL_PASS_OPEN_ACCEPT, 223 CPL_PASS_OPEN_REJECT, 224 CPL_PASS_OPEN_ACCEPT_TNL 225}; 226 227enum { 228 CPL_ABORT_SEND_RST = 0, 229 CPL_ABORT_NO_RST, 230}; 231 232enum { /* TX_PKT_XT checksum types */ 233 TX_CSUM_TCP = 0, 234 TX_CSUM_UDP = 1, 235 TX_CSUM_CRC16 = 4, 236 TX_CSUM_CRC32 = 5, 237 TX_CSUM_CRC32C = 6, 238 TX_CSUM_FCOE = 7, 239 TX_CSUM_TCPIP = 8, 240 TX_CSUM_UDPIP = 9, 241 TX_CSUM_TCPIP6 = 10, 242 TX_CSUM_UDPIP6 = 11, 243 TX_CSUM_IP = 12, 244}; 245 246enum { /* packet type in CPL_RX_PKT */ 247 PKTYPE_XACT_UCAST = 0, 248 PKTYPE_HASH_UCAST = 1, 249 PKTYPE_XACT_MCAST = 2, 250 PKTYPE_HASH_MCAST = 3, 251 PKTYPE_PROMISC = 4, 252 PKTYPE_HPROMISC = 5, 253 PKTYPE_BCAST = 6 254}; 255 256enum { /* DMAC type in CPL_RX_PKT */ 257 DATYPE_UCAST, 258 DATYPE_MCAST, 259 DATYPE_BCAST 260}; 261 262enum { /* TCP congestion control algorithms */ 263 CONG_ALG_RENO, 264 CONG_ALG_TAHOE, 265 CONG_ALG_NEWRENO, 266 CONG_ALG_HIGHSPEED 267}; 268 269enum { /* RSS hash type */ 270 RSS_HASH_NONE = 0, /* no hash computed */ 271 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 272 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 273 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 274}; 275 276enum { /* LE commands */ 277 LE_CMD_READ = 0x4, 278 LE_CMD_WRITE = 0xb 279}; 280 281enum { /* LE request size */ 282 LE_SZ_NONE = 0, 283 LE_SZ_33 = 1, 284 LE_SZ_66 = 2, 285 LE_SZ_132 = 3, 286 LE_SZ_264 = 4, 287 LE_SZ_528 = 5 288}; 289 290union opcode_tid { 291 __be32 opcode_tid; 292 __u8 opcode; 293}; 294 295#define S_CPL_OPCODE 24 296#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 297#define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 298#define G_TID(x) ((x) & 0xFFFFFF) 299 300/* tid is assumed to be 24-bits */ 301#define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 302 303#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 304 305/* extract the TID from a CPL command */ 306#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 307#define GET_OPCODE(cmd) ((cmd)->ot.opcode) 308 309/* partitioning of TID fields that also carry a queue id */ 310#define S_TID_TID 0 311#define M_TID_TID 0x3fff 312#define V_TID_TID(x) ((x) << S_TID_TID) 313#define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 314 315#define S_TID_QID 14 316#define M_TID_QID 0x3ff 317#define V_TID_QID(x) ((x) << S_TID_QID) 318#define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 319 320union opcode_info { 321 __be64 opcode_info; 322 __u8 opcode; 323}; 324 325struct tcp_options { 326 __be16 mss; 327 __u8 wsf; 328#if defined(__LITTLE_ENDIAN_BITFIELD) 329 __u8 :4; 330 __u8 unknown:1; 331 __u8 ecn:1; 332 __u8 sack:1; 333 __u8 tstamp:1; 334#else 335 __u8 tstamp:1; 336 __u8 sack:1; 337 __u8 ecn:1; 338 __u8 unknown:1; 339 __u8 :4; 340#endif 341}; 342 343struct rss_header { 344 __u8 opcode; 345#if defined(__LITTLE_ENDIAN_BITFIELD) 346 __u8 channel:2; 347 __u8 filter_hit:1; 348 __u8 filter_tid:1; 349 __u8 hash_type:2; 350 __u8 ipv6:1; 351 __u8 send2fw:1; 352#else 353 __u8 send2fw:1; 354 __u8 ipv6:1; 355 __u8 hash_type:2; 356 __u8 filter_tid:1; 357 __u8 filter_hit:1; 358 __u8 channel:2; 359#endif 360 __be16 qid; 361 __be32 hash_val; 362}; 363 364#define S_HASHTYPE 20 365#define M_HASHTYPE 0x3 366#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 367 368#define S_QNUM 0 369#define M_QNUM 0xFFFF 370#define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 371 372#if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 373# define RSS_HDR struct rss_header rss_hdr; 374#else 375# define RSS_HDR 376#endif 377 378#ifndef CHELSIO_FW 379struct work_request_hdr { 380 __be32 wr_hi; 381 __be32 wr_mid; 382 __be64 wr_lo; 383}; 384 385/* wr_mid fields */ 386#define S_WR_LEN16 0 387#define M_WR_LEN16 0xFF 388#define V_WR_LEN16(x) ((x) << S_WR_LEN16) 389#define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 390 391/* wr_hi fields */ 392#define S_WR_OP 24 393#define M_WR_OP 0xFF 394#define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 395#define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 396 397# define WR_HDR struct work_request_hdr wr 398# define WR_HDR_SIZE sizeof(struct work_request_hdr) 399#else 400# define WR_HDR 401# define WR_HDR_SIZE 0 402#endif 403 404/* option 0 fields */ 405#define S_ACCEPT_MODE 0 406#define M_ACCEPT_MODE 0x3 407#define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 408#define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 409 410#define S_TX_CHAN 2 411#define M_TX_CHAN 0x3 412#define V_TX_CHAN(x) ((x) << S_TX_CHAN) 413#define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 414 415#define S_NO_CONG 4 416#define V_NO_CONG(x) ((x) << S_NO_CONG) 417#define F_NO_CONG V_NO_CONG(1U) 418 419#define S_DELACK 5 420#define V_DELACK(x) ((x) << S_DELACK) 421#define F_DELACK V_DELACK(1U) 422 423#define S_INJECT_TIMER 6 424#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 425#define F_INJECT_TIMER V_INJECT_TIMER(1U) 426 427#define S_NON_OFFLOAD 7 428#define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 429#define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 430 431#define S_ULP_MODE 8 432#define M_ULP_MODE 0xF 433#define V_ULP_MODE(x) ((x) << S_ULP_MODE) 434#define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 435 436#define S_RCV_BUFSIZ 12 437#define M_RCV_BUFSIZ 0x3FFU 438#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 439#define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 440 441#define S_DSCP 22 442#define M_DSCP 0x3F 443#define V_DSCP(x) ((x) << S_DSCP) 444#define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 445 446#define S_SMAC_SEL 28 447#define M_SMAC_SEL 0xFF 448#define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 449#define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 450 451#define S_L2T_IDX 36 452#define M_L2T_IDX 0xFFF 453#define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 454#define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 455 456#define S_TCAM_BYPASS 48 457#define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 458#define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 459 460#define S_NAGLE 49 461#define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 462#define F_NAGLE V_NAGLE(1ULL) 463 464#define S_WND_SCALE 50 465#define M_WND_SCALE 0xF 466#define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 467#define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 468 469#define S_KEEP_ALIVE 54 470#define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 471#define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 472 473#define S_MAX_RT 55 474#define M_MAX_RT 0xF 475#define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 476#define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 477 478#define S_MAX_RT_OVERRIDE 59 479#define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 480#define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 481 482#define S_MSS_IDX 60 483#define M_MSS_IDX 0xF 484#define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 485#define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 486 487/* option 1 fields */ 488#define S_SYN_RSS_ENABLE 0 489#define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 490#define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 491 492#define S_SYN_RSS_USE_HASH 1 493#define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 494#define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 495 496#define S_SYN_RSS_QUEUE 2 497#define M_SYN_RSS_QUEUE 0x3FF 498#define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 499#define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 500 501#define S_LISTEN_INTF 12 502#define M_LISTEN_INTF 0xFF 503#define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 504#define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 505 506#define S_LISTEN_FILTER 20 507#define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 508#define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 509 510#define S_SYN_DEFENSE 21 511#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 512#define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 513 514#define S_CONN_POLICY 22 515#define M_CONN_POLICY 0x3 516#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 517#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 518 519#define S_T5_FILT_INFO 24 520#define M_T5_FILT_INFO 0xffffffffffULL 521#define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO) 522#define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO) 523 524#define S_FILT_INFO 28 525#define M_FILT_INFO 0xfffffffffULL 526#define V_FILT_INFO(x) ((x) << S_FILT_INFO) 527#define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 528 529/* option 2 fields */ 530#define S_RSS_QUEUE 0 531#define M_RSS_QUEUE 0x3FF 532#define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 533#define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 534 535#define S_RSS_QUEUE_VALID 10 536#define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 537#define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 538 539#define S_RX_COALESCE_VALID 11 540#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 541#define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 542 543#define S_RX_COALESCE 12 544#define M_RX_COALESCE 0x3 545#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 546#define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 547 548#define S_CONG_CNTRL 14 549#define M_CONG_CNTRL 0x3 550#define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 551#define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 552 553#define S_PACE 16 554#define M_PACE 0x3 555#define V_PACE(x) ((x) << S_PACE) 556#define G_PACE(x) (((x) >> S_PACE) & M_PACE) 557 558#define S_CONG_CNTRL_VALID 18 559#define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 560#define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 561 562#define S_T5_ISS 18 563#define V_T5_ISS(x) ((x) << S_T5_ISS) 564#define F_T5_ISS V_T5_ISS(1U) 565 566#define S_PACE_VALID 19 567#define V_PACE_VALID(x) ((x) << S_PACE_VALID) 568#define F_PACE_VALID V_PACE_VALID(1U) 569 570#define S_RX_FC_DISABLE 20 571#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 572#define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 573 574#define S_RX_FC_DDP 21 575#define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 576#define F_RX_FC_DDP V_RX_FC_DDP(1U) 577 578#define S_RX_FC_VALID 22 579#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 580#define F_RX_FC_VALID V_RX_FC_VALID(1U) 581 582#define S_TX_QUEUE 23 583#define M_TX_QUEUE 0x7 584#define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 585#define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 586 587#define S_RX_CHANNEL 26 588#define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 589#define F_RX_CHANNEL V_RX_CHANNEL(1U) 590 591#define S_CCTRL_ECN 27 592#define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 593#define F_CCTRL_ECN V_CCTRL_ECN(1U) 594 595#define S_WND_SCALE_EN 28 596#define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 597#define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 598 599#define S_TSTAMPS_EN 29 600#define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 601#define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 602 603#define S_SACK_EN 30 604#define V_SACK_EN(x) ((x) << S_SACK_EN) 605#define F_SACK_EN V_SACK_EN(1U) 606 607#define S_T5_OPT_2_VALID 31 608#define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 609#define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 610 611struct cpl_pass_open_req { 612 WR_HDR; 613 union opcode_tid ot; 614 __be16 local_port; 615 __be16 peer_port; 616 __be32 local_ip; 617 __be32 peer_ip; 618 __be64 opt0; 619 __be64 opt1; 620}; 621 622struct cpl_pass_open_req6 { 623 WR_HDR; 624 union opcode_tid ot; 625 __be16 local_port; 626 __be16 peer_port; 627 __be64 local_ip_hi; 628 __be64 local_ip_lo; 629 __be64 peer_ip_hi; 630 __be64 peer_ip_lo; 631 __be64 opt0; 632 __be64 opt1; 633}; 634 635struct cpl_pass_open_rpl { 636 RSS_HDR 637 union opcode_tid ot; 638 __u8 rsvd[3]; 639 __u8 status; 640}; 641 642struct cpl_pass_establish { 643 RSS_HDR 644 union opcode_tid ot; 645 __be32 rsvd; 646 __be32 tos_stid; 647 __be16 mac_idx; 648 __be16 tcp_opt; 649 __be32 snd_isn; 650 __be32 rcv_isn; 651}; 652 653/* cpl_pass_establish.tos_stid fields */ 654#define S_PASS_OPEN_TID 0 655#define M_PASS_OPEN_TID 0xFFFFFF 656#define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 657#define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 658 659#define S_PASS_OPEN_TOS 24 660#define M_PASS_OPEN_TOS 0xFF 661#define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 662#define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 663 664/* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 665#define S_TCPOPT_WSCALE_OK 5 666#define M_TCPOPT_WSCALE_OK 0x1 667#define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) 668#define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK) 669 670#define S_TCPOPT_SACK 6 671#define M_TCPOPT_SACK 0x1 672#define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) 673#define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK) 674 675#define S_TCPOPT_TSTAMP 7 676#define M_TCPOPT_TSTAMP 0x1 677#define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) 678#define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP) 679 680#define S_TCPOPT_SND_WSCALE 8 681#define M_TCPOPT_SND_WSCALE 0xF 682#define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) 683#define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE) 684 685#define S_TCPOPT_MSS 12 686#define M_TCPOPT_MSS 0xF 687#define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) 688#define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS) 689 690struct cpl_pass_accept_req { 691 RSS_HDR 692 union opcode_tid ot; 693 __be16 rsvd; 694 __be16 len; 695 __be32 hdr_len; 696 __be16 vlan; 697 __be16 l2info; 698 __be32 tos_stid; 699 struct tcp_options tcpopt; 700}; 701 702/* cpl_pass_accept_req.hdr_len fields */ 703#define S_SYN_RX_CHAN 0 704#define M_SYN_RX_CHAN 0xF 705#define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 706#define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 707 708#define S_TCP_HDR_LEN 10 709#define M_TCP_HDR_LEN 0x3F 710#define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 711#define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 712 713#define S_T6_TCP_HDR_LEN 8 714#define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN) 715#define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN) 716 717#define S_IP_HDR_LEN 16 718#define M_IP_HDR_LEN 0x3FF 719#define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 720#define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 721 722#define S_T6_IP_HDR_LEN 14 723#define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN) 724#define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN) 725 726#define S_ETH_HDR_LEN 26 727#define M_ETH_HDR_LEN 0x3F 728#define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 729#define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 730 731#define S_T6_ETH_HDR_LEN 24 732#define M_T6_ETH_HDR_LEN 0xFF 733#define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN) 734#define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN) 735 736/* cpl_pass_accept_req.l2info fields */ 737#define S_SYN_MAC_IDX 0 738#define M_SYN_MAC_IDX 0x1FF 739#define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 740#define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 741 742#define S_SYN_XACT_MATCH 9 743#define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 744#define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 745 746#define S_SYN_INTF 12 747#define M_SYN_INTF 0xF 748#define V_SYN_INTF(x) ((x) << S_SYN_INTF) 749#define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 750 751struct cpl_pass_accept_rpl { 752 WR_HDR; 753 union opcode_tid ot; 754 __be32 opt2; 755 __be64 opt0; 756}; 757 758struct cpl_t5_pass_accept_rpl { 759 WR_HDR; 760 union opcode_tid ot; 761 __be32 opt2; 762 __be64 opt0; 763 __be32 iss; 764 union { 765 __be32 rsvd; /* T5 */ 766 __be32 opt3; /* T6 */ 767 } u; 768}; 769 770struct cpl_act_open_req { 771 WR_HDR; 772 union opcode_tid ot; 773 __be16 local_port; 774 __be16 peer_port; 775 __be32 local_ip; 776 __be32 peer_ip; 777 __be64 opt0; 778 __be32 params; 779 __be32 opt2; 780}; 781 782#define S_FILTER_TUPLE 24 783#define M_FILTER_TUPLE 0xFFFFFFFFFF 784#define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 785#define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 786struct cpl_t5_act_open_req { 787 WR_HDR; 788 union opcode_tid ot; 789 __be16 local_port; 790 __be16 peer_port; 791 __be32 local_ip; 792 __be32 peer_ip; 793 __be64 opt0; 794 __be32 iss; 795 __be32 opt2; 796 __be64 params; 797}; 798 799struct cpl_t6_act_open_req { 800 WR_HDR; 801 union opcode_tid ot; 802 __be16 local_port; 803 __be16 peer_port; 804 __be32 local_ip; 805 __be32 peer_ip; 806 __be64 opt0; 807 __be32 iss; 808 __be32 opt2; 809 __be64 params; 810 __be32 rsvd2; 811 __be32 opt3; 812}; 813 814/* cpl_{t5,t6}_act_open_req.params field */ 815#define S_AOPEN_FCOEMASK 0 816#define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK) 817#define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U) 818 819struct cpl_act_open_req6 { 820 WR_HDR; 821 union opcode_tid ot; 822 __be16 local_port; 823 __be16 peer_port; 824 __be64 local_ip_hi; 825 __be64 local_ip_lo; 826 __be64 peer_ip_hi; 827 __be64 peer_ip_lo; 828 __be64 opt0; 829 __be32 params; 830 __be32 opt2; 831}; 832 833struct cpl_t5_act_open_req6 { 834 WR_HDR; 835 union opcode_tid ot; 836 __be16 local_port; 837 __be16 peer_port; 838 __be64 local_ip_hi; 839 __be64 local_ip_lo; 840 __be64 peer_ip_hi; 841 __be64 peer_ip_lo; 842 __be64 opt0; 843 __be32 iss; 844 __be32 opt2; 845 __be64 params; 846}; 847 848struct cpl_t6_act_open_req6 { 849 WR_HDR; 850 union opcode_tid ot; 851 __be16 local_port; 852 __be16 peer_port; 853 __be64 local_ip_hi; 854 __be64 local_ip_lo; 855 __be64 peer_ip_hi; 856 __be64 peer_ip_lo; 857 __be64 opt0; 858 __be32 iss; 859 __be32 opt2; 860 __be64 params; 861 __be32 rsvd2; 862 __be32 opt3; 863}; 864 865struct cpl_act_open_rpl { 866 RSS_HDR 867 union opcode_tid ot; 868 __be32 atid_status; 869}; 870 871/* cpl_act_open_rpl.atid_status fields */ 872#define S_AOPEN_STATUS 0 873#define M_AOPEN_STATUS 0xFF 874#define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 875#define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 876 877#define S_AOPEN_ATID 8 878#define M_AOPEN_ATID 0xFFFFFF 879#define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 880#define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 881 882struct cpl_act_establish { 883 RSS_HDR 884 union opcode_tid ot; 885 __be32 rsvd; 886 __be32 tos_atid; 887 __be16 mac_idx; 888 __be16 tcp_opt; 889 __be32 snd_isn; 890 __be32 rcv_isn; 891}; 892 893struct cpl_get_tcb { 894 WR_HDR; 895 union opcode_tid ot; 896 __be16 reply_ctrl; 897 __be16 cookie; 898}; 899 900/* cpl_get_tcb.reply_ctrl fields */ 901#define S_QUEUENO 0 902#define M_QUEUENO 0x3FF 903#define V_QUEUENO(x) ((x) << S_QUEUENO) 904#define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 905 906#define S_REPLY_CHAN 14 907#define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 908#define F_REPLY_CHAN V_REPLY_CHAN(1U) 909 910#define S_NO_REPLY 15 911#define V_NO_REPLY(x) ((x) << S_NO_REPLY) 912#define F_NO_REPLY V_NO_REPLY(1U) 913 914struct cpl_get_tcb_rpl { 915 RSS_HDR 916 union opcode_tid ot; 917 __u8 cookie; 918 __u8 status; 919 __be16 len; 920}; 921 922struct cpl_set_tcb { 923 WR_HDR; 924 union opcode_tid ot; 925 __be16 reply_ctrl; 926 __be16 cookie; 927}; 928 929struct cpl_set_tcb_field { 930 WR_HDR; 931 union opcode_tid ot; 932 __be16 reply_ctrl; 933 __be16 word_cookie; 934 __be64 mask; 935 __be64 val; 936}; 937 938struct cpl_set_tcb_field_core { 939 union opcode_tid ot; 940 __be16 reply_ctrl; 941 __be16 word_cookie; 942 __be64 mask; 943 __be64 val; 944}; 945 946/* cpl_set_tcb_field.word_cookie fields */ 947#define S_WORD 0 948#define M_WORD 0x1F 949#define V_WORD(x) ((x) << S_WORD) 950#define G_WORD(x) (((x) >> S_WORD) & M_WORD) 951 952#define S_COOKIE 5 953#define M_COOKIE 0x7 954#define V_COOKIE(x) ((x) << S_COOKIE) 955#define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 956 957struct cpl_set_tcb_rpl { 958 RSS_HDR 959 union opcode_tid ot; 960 __be16 rsvd; 961 __u8 cookie; 962 __u8 status; 963 __be64 oldval; 964}; 965 966struct cpl_close_con_req { 967 WR_HDR; 968 union opcode_tid ot; 969 __be32 rsvd; 970}; 971 972struct cpl_close_con_rpl { 973 RSS_HDR 974 union opcode_tid ot; 975 __u8 rsvd[3]; 976 __u8 status; 977 __be32 snd_nxt; 978 __be32 rcv_nxt; 979}; 980 981struct cpl_close_listsvr_req { 982 WR_HDR; 983 union opcode_tid ot; 984 __be16 reply_ctrl; 985 __be16 rsvd; 986}; 987 988/* additional cpl_close_listsvr_req.reply_ctrl field */ 989#define S_LISTSVR_IPV6 14 990#define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 991#define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 992 993struct cpl_close_listsvr_rpl { 994 RSS_HDR 995 union opcode_tid ot; 996 __u8 rsvd[3]; 997 __u8 status; 998}; 999 1000struct cpl_abort_req_rss { 1001 RSS_HDR 1002 union opcode_tid ot; 1003 __u8 rsvd[3]; 1004 __u8 status; 1005}; 1006 1007struct cpl_abort_req_rss6 { 1008 RSS_HDR 1009 union opcode_tid ot; 1010 __u32 srqidx_status; 1011}; 1012 1013#define S_ABORT_RSS_STATUS 0 1014#define M_ABORT_RSS_STATUS 0xff 1015#define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) 1016#define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) 1017 1018#define S_ABORT_RSS_SRQIDX 8 1019#define M_ABORT_RSS_SRQIDX 0xffffff 1020#define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) 1021#define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) 1022 1023 1024/* cpl_abort_req status command code in case of T6, 1025 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1) 1026 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ 1027 * bit[2] specifies whether to disable the mmgr (1) or not (0) 1028 */ 1029struct cpl_abort_req { 1030 WR_HDR; 1031 union opcode_tid ot; 1032 __be32 rsvd0; 1033 __u8 rsvd1; 1034 __u8 cmd; 1035 __u8 rsvd2[6]; 1036}; 1037 1038struct cpl_abort_rpl_rss { 1039 RSS_HDR 1040 union opcode_tid ot; 1041 __u8 rsvd[3]; 1042 __u8 status; 1043}; 1044 1045struct cpl_abort_rpl_rss6 { 1046 RSS_HDR 1047 union opcode_tid ot; 1048 __u32 srqidx_status; 1049}; 1050 1051struct cpl_abort_rpl { 1052 WR_HDR; 1053 union opcode_tid ot; 1054 __be32 rsvd0; 1055 __u8 rsvd1; 1056 __u8 cmd; 1057 __u8 rsvd2[6]; 1058}; 1059 1060struct cpl_peer_close { 1061 RSS_HDR 1062 union opcode_tid ot; 1063 __be32 rcv_nxt; 1064}; 1065 1066struct cpl_tid_release { 1067 WR_HDR; 1068 union opcode_tid ot; 1069 __be32 rsvd; 1070}; 1071 1072struct tx_data_wr { 1073 __be32 wr_hi; 1074 __be32 wr_lo; 1075 __be32 len; 1076 __be32 flags; 1077 __be32 sndseq; 1078 __be32 param; 1079}; 1080 1081/* tx_data_wr.flags fields */ 1082#define S_TX_ACK_PAGES 21 1083#define M_TX_ACK_PAGES 0x7 1084#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 1085#define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 1086 1087/* tx_data_wr.param fields */ 1088#define S_TX_PORT 0 1089#define M_TX_PORT 0x7 1090#define V_TX_PORT(x) ((x) << S_TX_PORT) 1091#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 1092 1093#define S_TX_MSS 4 1094#define M_TX_MSS 0xF 1095#define V_TX_MSS(x) ((x) << S_TX_MSS) 1096#define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 1097 1098#define S_TX_QOS 8 1099#define M_TX_QOS 0xFF 1100#define V_TX_QOS(x) ((x) << S_TX_QOS) 1101#define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 1102 1103#define S_TX_SNDBUF 16 1104#define M_TX_SNDBUF 0xFFFF 1105#define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 1106#define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 1107 1108struct cpl_tx_data { 1109 union opcode_tid ot; 1110 __be32 len; 1111 __be32 rsvd; 1112 __be32 flags; 1113}; 1114 1115/* cpl_tx_data.flags fields */ 1116#define S_TX_PROXY 5 1117#define V_TX_PROXY(x) ((x) << S_TX_PROXY) 1118#define F_TX_PROXY V_TX_PROXY(1U) 1119 1120#define S_TX_ULP_SUBMODE 6 1121#define M_TX_ULP_SUBMODE 0xF 1122#define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 1123#define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 1124 1125#define S_TX_ULP_MODE 10 1126#define M_TX_ULP_MODE 0x7 1127#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 1128#define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 1129 1130#define S_TX_FORCE 13 1131#define V_TX_FORCE(x) ((x) << S_TX_FORCE) 1132#define F_TX_FORCE V_TX_FORCE(1U) 1133 1134#define S_TX_SHOVE 14 1135#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 1136#define F_TX_SHOVE V_TX_SHOVE(1U) 1137 1138#define S_TX_MORE 15 1139#define V_TX_MORE(x) ((x) << S_TX_MORE) 1140#define F_TX_MORE V_TX_MORE(1U) 1141 1142#define S_TX_URG 16 1143#define V_TX_URG(x) ((x) << S_TX_URG) 1144#define F_TX_URG V_TX_URG(1U) 1145 1146#define S_TX_FLUSH 17 1147#define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1148#define F_TX_FLUSH V_TX_FLUSH(1U) 1149 1150#define S_TX_SAVE 18 1151#define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1152#define F_TX_SAVE V_TX_SAVE(1U) 1153 1154#define S_TX_TNL 19 1155#define V_TX_TNL(x) ((x) << S_TX_TNL) 1156#define F_TX_TNL V_TX_TNL(1U) 1157 1158#define S_T6_TX_FORCE 20 1159#define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE) 1160#define F_T6_TX_FORCE V_T6_TX_FORCE(1U) 1161 1162/* additional tx_data_wr.flags fields */ 1163#define S_TX_CPU_IDX 0 1164#define M_TX_CPU_IDX 0x3F 1165#define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1166#define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1167 1168#define S_TX_CLOSE 17 1169#define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1170#define F_TX_CLOSE V_TX_CLOSE(1U) 1171 1172#define S_TX_INIT 18 1173#define V_TX_INIT(x) ((x) << S_TX_INIT) 1174#define F_TX_INIT V_TX_INIT(1U) 1175 1176#define S_TX_IMM_ACK 19 1177#define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1178#define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1179 1180#define S_TX_IMM_DMA 20 1181#define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1182#define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1183 1184struct cpl_tx_data_ack { 1185 RSS_HDR 1186 union opcode_tid ot; 1187 __be32 snd_una; 1188}; 1189 1190struct cpl_wr_ack { /* XXX */ 1191 RSS_HDR 1192 union opcode_tid ot; 1193 __be16 credits; 1194 __be16 rsvd; 1195 __be32 snd_nxt; 1196 __be32 snd_una; 1197}; 1198 1199struct cpl_tx_pkt_core { 1200 __be32 ctrl0; 1201 __be16 pack; 1202 __be16 len; 1203 __be64 ctrl1; 1204}; 1205 1206struct cpl_tx_pkt { 1207 WR_HDR; 1208 struct cpl_tx_pkt_core c; 1209}; 1210 1211#define cpl_tx_pkt_xt cpl_tx_pkt 1212 1213/* cpl_tx_pkt_core.ctrl0 fields */ 1214#define S_TXPKT_VF 0 1215#define M_TXPKT_VF 0xFF 1216#define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1217#define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1218 1219#define S_TXPKT_PF 8 1220#define M_TXPKT_PF 0x7 1221#define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1222#define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1223 1224#define S_TXPKT_VF_VLD 11 1225#define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1226#define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1227 1228#define S_TXPKT_OVLAN_IDX 12 1229#define M_TXPKT_OVLAN_IDX 0xF 1230#define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1231#define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1232 1233#define S_TXPKT_T5_OVLAN_IDX 12 1234#define M_TXPKT_T5_OVLAN_IDX 0x7 1235#define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1236#define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1237 M_TXPKT_T5_OVLAN_IDX) 1238 1239#define S_TXPKT_INTF 16 1240#define M_TXPKT_INTF 0xF 1241#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1242#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1243 1244#define S_TXPKT_SPECIAL_STAT 20 1245#define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1246#define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1247 1248#define S_TXPKT_T5_FCS_DIS 21 1249#define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1250#define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1251 1252#define S_TXPKT_INS_OVLAN 21 1253#define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1254#define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1255 1256#define S_TXPKT_T5_INS_OVLAN 15 1257#define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1258#define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1259 1260#define S_TXPKT_STAT_DIS 22 1261#define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1262#define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1263 1264#define S_TXPKT_LOOPBACK 23 1265#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1266#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1267 1268#define S_TXPKT_TSTAMP 23 1269#define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1270#define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1271 1272#define S_TXPKT_OPCODE 24 1273#define M_TXPKT_OPCODE 0xFF 1274#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1275#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1276 1277/* cpl_tx_pkt_core.ctrl1 fields */ 1278#define S_TXPKT_SA_IDX 0 1279#define M_TXPKT_SA_IDX 0xFFF 1280#define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1281#define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1282 1283#define S_TXPKT_CSUM_END 12 1284#define M_TXPKT_CSUM_END 0xFF 1285#define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1286#define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1287 1288#define S_TXPKT_CSUM_START 20 1289#define M_TXPKT_CSUM_START 0x3FF 1290#define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1291#define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1292 1293#define S_TXPKT_IPHDR_LEN 20 1294#define M_TXPKT_IPHDR_LEN 0x3FFF 1295#define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1296#define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1297 1298#define M_T6_TXPKT_IPHDR_LEN 0xFFF 1299#define G_T6_TXPKT_IPHDR_LEN(x) \ 1300 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN) 1301 1302#define S_TXPKT_CSUM_LOC 30 1303#define M_TXPKT_CSUM_LOC 0x3FF 1304#define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1305#define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1306 1307#define S_TXPKT_ETHHDR_LEN 34 1308#define M_TXPKT_ETHHDR_LEN 0x3F 1309#define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1310#define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1311 1312#define S_T6_TXPKT_ETHHDR_LEN 32 1313#define M_T6_TXPKT_ETHHDR_LEN 0xFF 1314#define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 1315#define G_T6_TXPKT_ETHHDR_LEN(x) \ 1316 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 1317 1318#define S_TXPKT_CSUM_TYPE 40 1319#define M_TXPKT_CSUM_TYPE 0xF 1320#define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1321#define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1322 1323#define S_TXPKT_VLAN 44 1324#define M_TXPKT_VLAN 0xFFFF 1325#define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1326#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1327 1328#define S_TXPKT_VLAN_VLD 60 1329#define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1330#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1331 1332#define S_TXPKT_IPSEC 61 1333#define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1334#define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1335 1336#define S_TXPKT_IPCSUM_DIS 62 1337#define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1338#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1339 1340#define S_TXPKT_L4CSUM_DIS 63 1341#define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1342#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1343 1344struct cpl_tx_pkt_lso_core { 1345 __be32 lso_ctrl; 1346 __be16 ipid_ofst; 1347 __be16 mss; 1348 __be32 seqno_offset; 1349 __be32 len; 1350 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1351}; 1352 1353struct cpl_tx_pkt_lso { 1354 WR_HDR; 1355 struct cpl_tx_pkt_lso_core c; 1356 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1357}; 1358 1359struct cpl_tx_pkt_ufo_core { 1360 __be16 ethlen; 1361 __be16 iplen; 1362 __be16 udplen; 1363 __be16 mss; 1364 __be32 len; 1365 __be32 r1; 1366 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1367}; 1368 1369struct cpl_tx_pkt_ufo { 1370 WR_HDR; 1371 struct cpl_tx_pkt_ufo_core c; 1372 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1373}; 1374 1375/* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1376#define S_LSO_TCPHDR_LEN 0 1377#define M_LSO_TCPHDR_LEN 0xF 1378#define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1379#define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1380 1381#define S_LSO_IPHDR_LEN 4 1382#define M_LSO_IPHDR_LEN 0xFFF 1383#define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1384#define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1385 1386#define S_LSO_ETHHDR_LEN 16 1387#define M_LSO_ETHHDR_LEN 0xF 1388#define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1389#define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1390 1391#define S_LSO_IPV6 20 1392#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1393#define F_LSO_IPV6 V_LSO_IPV6(1U) 1394 1395#define S_LSO_OFLD_ENCAP 21 1396#define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1397#define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1398 1399#define S_LSO_LAST_SLICE 22 1400#define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1401#define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1402 1403#define S_LSO_FIRST_SLICE 23 1404#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1405#define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1406 1407#define S_LSO_OPCODE 24 1408#define M_LSO_OPCODE 0xFF 1409#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1410#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1411 1412#define S_LSO_T5_XFER_SIZE 0 1413#define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1414#define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1415#define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1416 1417/* cpl_tx_pkt_lso_core.mss fields */ 1418#define S_LSO_MSS 0 1419#define M_LSO_MSS 0x3FFF 1420#define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1421#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1422 1423#define S_LSO_IPID_SPLIT 15 1424#define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1425#define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1426 1427struct cpl_tx_pkt_fso { 1428 WR_HDR; 1429 __be32 fso_ctrl; 1430 __be16 seqcnt_ofst; 1431 __be16 mtu; 1432 __be32 param_offset; 1433 __be32 len; 1434 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1435}; 1436 1437/* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1438#define S_FSO_XCHG_CLASS 21 1439#define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1440#define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1441 1442#define S_FSO_INITIATOR 20 1443#define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1444#define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1445 1446#define S_FSO_FCHDR_LEN 12 1447#define M_FSO_FCHDR_LEN 0xF 1448#define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1449#define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1450 1451struct cpl_iscsi_hdr_no_rss { 1452 union opcode_tid ot; 1453 __be16 pdu_len_ddp; 1454 __be16 len; 1455 __be32 seq; 1456 __be16 urg; 1457 __u8 rsvd; 1458 __u8 status; 1459}; 1460 1461struct cpl_tx_data_iso { 1462 __be32 op_to_scsi; 1463 __u8 reserved1; 1464 __u8 ahs_len; 1465 __be16 mpdu; 1466 __be32 burst_size; 1467 __be32 len; 1468 __be32 reserved2_seglen_offset; 1469 __be32 datasn_offset; 1470 __be32 buffer_offset; 1471 __be32 reserved3; 1472 1473 /* encapsulated CPL_TX_DATA follows here */ 1474}; 1475 1476/* cpl_tx_data_iso.op_to_scsi fields */ 1477#define S_CPL_TX_DATA_ISO_OP 24 1478#define M_CPL_TX_DATA_ISO_OP 0xff 1479#define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) 1480#define G_CPL_TX_DATA_ISO_OP(x) \ 1481 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP) 1482 1483#define S_CPL_TX_DATA_ISO_FIRST 23 1484#define M_CPL_TX_DATA_ISO_FIRST 0x1 1485#define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST) 1486#define G_CPL_TX_DATA_ISO_FIRST(x) \ 1487 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST) 1488#define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U) 1489 1490#define S_CPL_TX_DATA_ISO_LAST 22 1491#define M_CPL_TX_DATA_ISO_LAST 0x1 1492#define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST) 1493#define G_CPL_TX_DATA_ISO_LAST(x) \ 1494 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST) 1495#define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U) 1496 1497#define S_CPL_TX_DATA_ISO_CPLHDRLEN 21 1498#define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1 1499#define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN) 1500#define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ 1501 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN) 1502#define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U) 1503 1504#define S_CPL_TX_DATA_ISO_HDRCRC 20 1505#define M_CPL_TX_DATA_ISO_HDRCRC 0x1 1506#define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC) 1507#define G_CPL_TX_DATA_ISO_HDRCRC(x) \ 1508 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC) 1509#define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U) 1510 1511#define S_CPL_TX_DATA_ISO_PLDCRC 19 1512#define M_CPL_TX_DATA_ISO_PLDCRC 0x1 1513#define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC) 1514#define G_CPL_TX_DATA_ISO_PLDCRC(x) \ 1515 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC) 1516#define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U) 1517 1518#define S_CPL_TX_DATA_ISO_IMMEDIATE 18 1519#define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1 1520#define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE) 1521#define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ 1522 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE) 1523#define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U) 1524 1525#define S_CPL_TX_DATA_ISO_SCSI 16 1526#define M_CPL_TX_DATA_ISO_SCSI 0x3 1527#define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) 1528#define G_CPL_TX_DATA_ISO_SCSI(x) \ 1529 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI) 1530 1531/* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1532#define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0 1533#define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff 1534#define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1535 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1536#define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1537 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \ 1538 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1539 1540struct cpl_iscsi_hdr { 1541 RSS_HDR 1542 union opcode_tid ot; 1543 __be16 pdu_len_ddp; 1544 __be16 len; 1545 __be32 seq; 1546 __be16 urg; 1547 __u8 rsvd; 1548 __u8 status; 1549}; 1550 1551/* cpl_iscsi_hdr.pdu_len_ddp fields */ 1552#define S_ISCSI_PDU_LEN 0 1553#define M_ISCSI_PDU_LEN 0x7FFF 1554#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1555#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1556 1557#define S_ISCSI_DDP 15 1558#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1559#define F_ISCSI_DDP V_ISCSI_DDP(1U) 1560 1561struct cpl_iscsi_data { 1562 RSS_HDR 1563 union opcode_tid ot; 1564 __u8 rsvd0[2]; 1565 __be16 len; 1566 __be32 seq; 1567 __be16 urg; 1568 __u8 rsvd1; 1569 __u8 status; 1570}; 1571 1572struct cpl_rx_data { 1573 RSS_HDR 1574 union opcode_tid ot; 1575 __be16 rsvd; 1576 __be16 len; 1577 __be32 seq; 1578 __be16 urg; 1579#if defined(__LITTLE_ENDIAN_BITFIELD) 1580 __u8 dack_mode:2; 1581 __u8 psh:1; 1582 __u8 heartbeat:1; 1583 __u8 ddp_off:1; 1584 __u8 :3; 1585#else 1586 __u8 :3; 1587 __u8 ddp_off:1; 1588 __u8 heartbeat:1; 1589 __u8 psh:1; 1590 __u8 dack_mode:2; 1591#endif 1592 __u8 status; 1593}; 1594 1595struct cpl_fcoe_hdr { 1596 RSS_HDR 1597 union opcode_tid ot; 1598 __be16 oxid; 1599 __be16 len; 1600 __be32 rctl_fctl; 1601 __u8 cs_ctl; 1602 __u8 df_ctl; 1603 __u8 sof; 1604 __u8 eof; 1605 __be16 seq_cnt; 1606 __u8 seq_id; 1607 __u8 type; 1608 __be32 param; 1609}; 1610 1611/* cpl_fcoe_hdr.rctl_fctl fields */ 1612#define S_FCOE_FCHDR_RCTL 24 1613#define M_FCOE_FCHDR_RCTL 0xff 1614#define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) 1615#define G_FCOE_FCHDR_RCTL(x) \ 1616 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL) 1617 1618#define S_FCOE_FCHDR_FCTL 0 1619#define M_FCOE_FCHDR_FCTL 0xffffff 1620#define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) 1621#define G_FCOE_FCHDR_FCTL(x) \ 1622 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL) 1623 1624struct cpl_fcoe_data { 1625 RSS_HDR 1626 union opcode_tid ot; 1627 __u8 rsvd0[2]; 1628 __be16 len; 1629 __be32 seq; 1630 __u8 rsvd1[3]; 1631 __u8 status; 1632}; 1633 1634struct cpl_rx_urg_notify { 1635 RSS_HDR 1636 union opcode_tid ot; 1637 __be32 seq; 1638}; 1639 1640struct cpl_rx_urg_pkt { 1641 RSS_HDR 1642 union opcode_tid ot; 1643 __be16 rsvd; 1644 __be16 len; 1645}; 1646 1647struct cpl_rx_data_ack { 1648 WR_HDR; 1649 union opcode_tid ot; 1650 __be32 credit_dack; 1651}; 1652 1653struct cpl_rx_data_ack_core { 1654 union opcode_tid ot; 1655 __be32 credit_dack; 1656}; 1657 1658/* cpl_rx_data_ack.ack_seq fields */ 1659#define S_RX_CREDITS 0 1660#define M_RX_CREDITS 0x3FFFFFF 1661#define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1662#define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1663 1664#define S_RX_MODULATE_TX 26 1665#define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1666#define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1667 1668#define S_RX_MODULATE_RX 27 1669#define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1670#define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1671 1672#define S_RX_FORCE_ACK 28 1673#define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1674#define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1675 1676#define S_RX_DACK_MODE 29 1677#define M_RX_DACK_MODE 0x3 1678#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1679#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1680 1681#define S_RX_DACK_CHANGE 31 1682#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1683#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1684 1685struct cpl_rx_ddp_complete { 1686 RSS_HDR 1687 union opcode_tid ot; 1688 __be32 ddp_report; 1689 __be32 rcv_nxt; 1690 __be32 rsvd; 1691}; 1692 1693struct cpl_rx_data_ddp { 1694 RSS_HDR 1695 union opcode_tid ot; 1696 __be16 urg; 1697 __be16 len; 1698 __be32 seq; 1699 union { 1700 __be32 nxt_seq; 1701 __be32 ddp_report; 1702 } u; 1703 __be32 ulp_crc; 1704 __be32 ddpvld; 1705}; 1706 1707#define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1708 1709struct cpl_rx_fcoe_ddp { 1710 RSS_HDR 1711 union opcode_tid ot; 1712 __be16 rsvd; 1713 __be16 len; 1714 __be32 seq; 1715 __be32 ddp_report; 1716 __be32 ulp_crc; 1717 __be32 ddpvld; 1718}; 1719 1720struct cpl_rx_data_dif { 1721 RSS_HDR 1722 union opcode_tid ot; 1723 __be16 ddp_len; 1724 __be16 msg_len; 1725 __be32 seq; 1726 union { 1727 __be32 nxt_seq; 1728 __be32 ddp_report; 1729 } u; 1730 __be32 err_vec; 1731 __be32 ddpvld; 1732}; 1733 1734struct cpl_rx_iscsi_dif { 1735 RSS_HDR 1736 union opcode_tid ot; 1737 __be16 ddp_len; 1738 __be16 msg_len; 1739 __be32 seq; 1740 union { 1741 __be32 nxt_seq; 1742 __be32 ddp_report; 1743 } u; 1744 __be32 ulp_crc; 1745 __be32 ddpvld; 1746 __u8 rsvd0[8]; 1747 __be32 err_vec; 1748 __u8 rsvd1[4]; 1749}; 1750 1751struct cpl_rx_iscsi_cmp { 1752 RSS_HDR 1753 union opcode_tid ot; 1754 __be16 pdu_len_ddp; 1755 __be16 len; 1756 __be32 seq; 1757 __be16 urg; 1758 __u8 rsvd; 1759 __u8 status; 1760 __be32 ulp_crc; 1761 __be32 ddpvld; 1762}; 1763 1764struct cpl_rx_fcoe_dif { 1765 RSS_HDR 1766 union opcode_tid ot; 1767 __be16 ddp_len; 1768 __be16 msg_len; 1769 __be32 seq; 1770 __be32 ddp_report; 1771 __be32 err_vec; 1772 __be32 ddpvld; 1773}; 1774 1775/* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1776#define S_DDP_VALID 15 1777#define M_DDP_VALID 0x1FFFF 1778#define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1779#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1780 1781#define S_DDP_PPOD_MISMATCH 15 1782#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1783#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1784 1785#define S_DDP_PDU 16 1786#define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1787#define F_DDP_PDU V_DDP_PDU(1U) 1788 1789#define S_DDP_LLIMIT_ERR 17 1790#define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1791#define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1792 1793#define S_DDP_PPOD_PARITY_ERR 18 1794#define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1795#define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1796 1797#define S_DDP_PADDING_ERR 19 1798#define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1799#define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1800 1801#define S_DDP_HDRCRC_ERR 20 1802#define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1803#define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1804 1805#define S_DDP_DATACRC_ERR 21 1806#define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1807#define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1808 1809#define S_DDP_INVALID_TAG 22 1810#define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1811#define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1812 1813#define S_DDP_ULIMIT_ERR 23 1814#define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1815#define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1816 1817#define S_DDP_OFFSET_ERR 24 1818#define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1819#define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1820 1821#define S_DDP_COLOR_ERR 25 1822#define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1823#define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1824 1825#define S_DDP_TID_MISMATCH 26 1826#define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1827#define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1828 1829#define S_DDP_INVALID_PPOD 27 1830#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1831#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1832 1833#define S_DDP_ULP_MODE 28 1834#define M_DDP_ULP_MODE 0xF 1835#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1836#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1837 1838/* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1839#define S_DDP_OFFSET 0 1840#define M_DDP_OFFSET 0xFFFFFF 1841#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1842#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1843 1844#define S_DDP_DACK_MODE 24 1845#define M_DDP_DACK_MODE 0x3 1846#define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1847#define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1848 1849#define S_DDP_BUF_IDX 26 1850#define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1851#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1852 1853#define S_DDP_URG 27 1854#define V_DDP_URG(x) ((x) << S_DDP_URG) 1855#define F_DDP_URG V_DDP_URG(1U) 1856 1857#define S_DDP_PSH 28 1858#define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1859#define F_DDP_PSH V_DDP_PSH(1U) 1860 1861#define S_DDP_BUF_COMPLETE 29 1862#define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1863#define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1864 1865#define S_DDP_BUF_TIMED_OUT 30 1866#define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1867#define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1868 1869#define S_DDP_INV 31 1870#define V_DDP_INV(x) ((x) << S_DDP_INV) 1871#define F_DDP_INV V_DDP_INV(1U) 1872 1873struct cpl_rx_pkt { 1874 RSS_HDR 1875 __u8 opcode; 1876#if defined(__LITTLE_ENDIAN_BITFIELD) 1877 __u8 iff:4; 1878 __u8 csum_calc:1; 1879 __u8 ipmi_pkt:1; 1880 __u8 vlan_ex:1; 1881 __u8 ip_frag:1; 1882#else 1883 __u8 ip_frag:1; 1884 __u8 vlan_ex:1; 1885 __u8 ipmi_pkt:1; 1886 __u8 csum_calc:1; 1887 __u8 iff:4; 1888#endif 1889 __be16 csum; 1890 __be16 vlan; 1891 __be16 len; 1892 __be32 l2info; 1893 __be16 hdr_len; 1894 __be16 err_vec; 1895}; 1896 1897/* rx_pkt.l2info fields */ 1898#define S_RX_ETHHDR_LEN 0 1899#define M_RX_ETHHDR_LEN 0x1F 1900#define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1901#define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1902 1903#define S_RX_T5_ETHHDR_LEN 0 1904#define M_RX_T5_ETHHDR_LEN 0x3F 1905#define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1906#define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1907 1908#define M_RX_T6_ETHHDR_LEN 0xFF 1909#define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN) 1910 1911#define S_RX_PKTYPE 5 1912#define M_RX_PKTYPE 0x7 1913#define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1914#define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1915 1916#define S_RX_T5_DATYPE 6 1917#define M_RX_T5_DATYPE 0x3 1918#define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1919#define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1920 1921#define S_RX_MACIDX 8 1922#define M_RX_MACIDX 0x1FF 1923#define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1924#define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1925 1926#define S_RX_T5_PKTYPE 17 1927#define M_RX_T5_PKTYPE 0x7 1928#define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1929#define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1930 1931#define S_RX_DATYPE 18 1932#define M_RX_DATYPE 0x3 1933#define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1934#define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1935 1936#define S_RXF_PSH 20 1937#define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1938#define F_RXF_PSH V_RXF_PSH(1U) 1939 1940#define S_RXF_SYN 21 1941#define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1942#define F_RXF_SYN V_RXF_SYN(1U) 1943 1944#define S_RXF_UDP 22 1945#define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1946#define F_RXF_UDP V_RXF_UDP(1U) 1947 1948#define S_RXF_TCP 23 1949#define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1950#define F_RXF_TCP V_RXF_TCP(1U) 1951 1952#define S_RXF_IP 24 1953#define V_RXF_IP(x) ((x) << S_RXF_IP) 1954#define F_RXF_IP V_RXF_IP(1U) 1955 1956#define S_RXF_IP6 25 1957#define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1958#define F_RXF_IP6 V_RXF_IP6(1U) 1959 1960#define S_RXF_SYN_COOKIE 26 1961#define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1962#define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1963 1964#define S_RXF_FCOE 26 1965#define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1966#define F_RXF_FCOE V_RXF_FCOE(1U) 1967 1968#define S_RXF_LRO 27 1969#define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1970#define F_RXF_LRO V_RXF_LRO(1U) 1971 1972#define S_RX_CHAN 28 1973#define M_RX_CHAN 0xF 1974#define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1975#define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1976 1977/* rx_pkt.hdr_len fields */ 1978#define S_RX_TCPHDR_LEN 0 1979#define M_RX_TCPHDR_LEN 0x3F 1980#define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1981#define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1982 1983#define S_RX_IPHDR_LEN 6 1984#define M_RX_IPHDR_LEN 0x3FF 1985#define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1986#define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1987 1988/* rx_pkt.err_vec fields */ 1989#define S_RXERR_OR 0 1990#define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1991#define F_RXERR_OR V_RXERR_OR(1U) 1992 1993#define S_RXERR_MAC 1 1994#define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1995#define F_RXERR_MAC V_RXERR_MAC(1U) 1996 1997#define S_RXERR_IPVERS 2 1998#define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1999#define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 2000 2001#define S_RXERR_FRAG 3 2002#define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 2003#define F_RXERR_FRAG V_RXERR_FRAG(1U) 2004 2005#define S_RXERR_ATTACK 4 2006#define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 2007#define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 2008 2009#define S_RXERR_ETHHDR_LEN 5 2010#define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 2011#define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 2012 2013#define S_RXERR_IPHDR_LEN 6 2014#define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 2015#define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 2016 2017#define S_RXERR_TCPHDR_LEN 7 2018#define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 2019#define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 2020 2021#define S_RXERR_PKT_LEN 8 2022#define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 2023#define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 2024 2025#define S_RXERR_TCP_OPT 9 2026#define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 2027#define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 2028 2029#define S_RXERR_IPCSUM 12 2030#define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 2031#define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 2032 2033#define S_RXERR_CSUM 13 2034#define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 2035#define F_RXERR_CSUM V_RXERR_CSUM(1U) 2036 2037#define S_RXERR_PING 14 2038#define V_RXERR_PING(x) ((x) << S_RXERR_PING) 2039#define F_RXERR_PING V_RXERR_PING(1U) 2040 2041/* In T6, rx_pkt.err_vec indicates 2042 * RxError Error vector (16b) or 2043 * Encapsulating header length (8b), 2044 * Outer encapsulation type (2b) and 2045 * compressed error vector (6b) if CRxPktEnc is 2046 * enabled in TP_OUT_CONFIG 2047 */ 2048 2049#define S_T6_COMPR_RXERR_VEC 0 2050#define M_T6_COMPR_RXERR_VEC 0x3F 2051#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 2052#define G_T6_COMPR_RXERR_VEC(x) \ 2053 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 2054 2055#define S_T6_COMPR_RXERR_MAC 0 2056#define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC) 2057#define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U) 2058 2059/* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN 2060 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN 2061 */ 2062#define S_T6_COMPR_RXERR_LEN 1 2063#define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN) 2064#define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U) 2065 2066#define S_T6_COMPR_RXERR_TCP_OPT 2 2067#define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT) 2068#define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U) 2069 2070#define S_T6_COMPR_RXERR_IPV6_EXT 3 2071#define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT) 2072#define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U) 2073 2074/* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 2075#define S_T6_COMPR_RXERR_SUM 4 2076#define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM) 2077#define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U) 2078 2079/* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP, 2080 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION 2081 */ 2082#define S_T6_COMPR_RXERR_MISC 5 2083#define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC) 2084#define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U) 2085 2086#define S_T6_RX_TNL_TYPE 6 2087#define M_T6_RX_TNL_TYPE 0x3 2088#define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE) 2089#define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE) 2090 2091#define RX_PKT_TNL_TYPE_NVGRE 1 2092#define RX_PKT_TNL_TYPE_VXLAN 2 2093#define RX_PKT_TNL_TYPE_GENEVE 3 2094 2095#define S_T6_RX_TNLHDR_LEN 8 2096#define M_T6_RX_TNLHDR_LEN 0xFF 2097#define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN) 2098#define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN) 2099 2100struct cpl_trace_pkt { 2101 RSS_HDR 2102 __u8 opcode; 2103 __u8 intf; 2104#if defined(__LITTLE_ENDIAN_BITFIELD) 2105 __u8 runt:4; 2106 __u8 filter_hit:4; 2107 __u8 :6; 2108 __u8 err:1; 2109 __u8 trunc:1; 2110#else 2111 __u8 filter_hit:4; 2112 __u8 runt:4; 2113 __u8 trunc:1; 2114 __u8 err:1; 2115 __u8 :6; 2116#endif 2117 __be16 rsvd; 2118 __be16 len; 2119 __be64 tstamp; 2120}; 2121 2122struct cpl_t5_trace_pkt { 2123 RSS_HDR 2124 __u8 opcode; 2125 __u8 intf; 2126#if defined(__LITTLE_ENDIAN_BITFIELD) 2127 __u8 runt:4; 2128 __u8 filter_hit:4; 2129 __u8 :6; 2130 __u8 err:1; 2131 __u8 trunc:1; 2132#else 2133 __u8 filter_hit:4; 2134 __u8 runt:4; 2135 __u8 trunc:1; 2136 __u8 err:1; 2137 __u8 :6; 2138#endif 2139 __be16 rsvd; 2140 __be16 len; 2141 __be64 tstamp; 2142 __be64 rsvd1; 2143}; 2144 2145struct cpl_rte_delete_req { 2146 WR_HDR; 2147 union opcode_tid ot; 2148 __be32 params; 2149}; 2150 2151/* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 2152#define S_RTE_REQ_LUT_IX 8 2153#define M_RTE_REQ_LUT_IX 0x7FF 2154#define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 2155#define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 2156 2157#define S_RTE_REQ_LUT_BASE 19 2158#define M_RTE_REQ_LUT_BASE 0x7FF 2159#define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 2160#define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 2161 2162#define S_RTE_READ_REQ_SELECT 31 2163#define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 2164#define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 2165 2166struct cpl_rte_delete_rpl { 2167 RSS_HDR 2168 union opcode_tid ot; 2169 __u8 status; 2170 __u8 rsvd[3]; 2171}; 2172 2173struct cpl_rte_write_req { 2174 WR_HDR; 2175 union opcode_tid ot; 2176 __u32 write_sel; 2177 __be32 lut_params; 2178 __be32 l2t_idx; 2179 __be32 netmask; 2180 __be32 faddr; 2181}; 2182 2183/* cpl_rte_write_req.write_sel fields */ 2184#define S_RTE_WR_L2TIDX 31 2185#define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 2186#define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 2187 2188#define S_RTE_WR_FADDR 30 2189#define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 2190#define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 2191 2192/* cpl_rte_write_req.lut_params fields */ 2193#define S_RTE_WR_LUT_IX 10 2194#define M_RTE_WR_LUT_IX 0x7FF 2195#define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 2196#define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 2197 2198#define S_RTE_WR_LUT_BASE 21 2199#define M_RTE_WR_LUT_BASE 0x7FF 2200#define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 2201#define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 2202 2203struct cpl_rte_write_rpl { 2204 RSS_HDR 2205 union opcode_tid ot; 2206 __u8 status; 2207 __u8 rsvd[3]; 2208}; 2209 2210struct cpl_rte_read_req { 2211 WR_HDR; 2212 union opcode_tid ot; 2213 __be32 params; 2214}; 2215 2216struct cpl_rte_read_rpl { 2217 RSS_HDR 2218 union opcode_tid ot; 2219 __u8 status; 2220 __u8 rsvd; 2221 __be16 l2t_idx; 2222#if defined(__LITTLE_ENDIAN_BITFIELD) 2223 __u32 :30; 2224 __u32 select:1; 2225#else 2226 __u32 select:1; 2227 __u32 :30; 2228#endif 2229 __be32 addr; 2230}; 2231 2232struct cpl_l2t_write_req { 2233 WR_HDR; 2234 union opcode_tid ot; 2235 __be16 params; 2236 __be16 l2t_idx; 2237 __be16 vlan; 2238 __u8 dst_mac[6]; 2239}; 2240 2241/* cpl_l2t_write_req.params fields */ 2242#define S_L2T_W_INFO 2 2243#define M_L2T_W_INFO 0x3F 2244#define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 2245#define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 2246 2247#define S_L2T_W_PORT 8 2248#define M_L2T_W_PORT 0x3 2249#define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 2250#define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 2251 2252#define S_L2T_W_LPBK 10 2253#define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 2254#define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 2255 2256#define S_L2T_W_ARPMISS 11 2257#define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 2258#define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 2259 2260#define S_L2T_W_NOREPLY 15 2261#define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 2262#define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 2263 2264#define CPL_L2T_VLAN_NONE 0xfff 2265 2266struct cpl_l2t_write_rpl { 2267 RSS_HDR 2268 union opcode_tid ot; 2269 __u8 status; 2270 __u8 rsvd[3]; 2271}; 2272 2273struct cpl_l2t_read_req { 2274 WR_HDR; 2275 union opcode_tid ot; 2276 __be32 l2t_idx; 2277}; 2278 2279struct cpl_l2t_read_rpl { 2280 RSS_HDR 2281 union opcode_tid ot; 2282 __u8 status; 2283#if defined(__LITTLE_ENDIAN_BITFIELD) 2284 __u8 :4; 2285 __u8 iff:4; 2286#else 2287 __u8 iff:4; 2288 __u8 :4; 2289#endif 2290 __be16 vlan; 2291 __be16 info; 2292 __u8 dst_mac[6]; 2293}; 2294 2295struct cpl_srq_table_req { 2296 WR_HDR; 2297 union opcode_tid ot; 2298 __u8 status; 2299 __u8 rsvd[2]; 2300 __u8 idx; 2301 __be64 rsvd_pdid; 2302 __be32 qlen_qbase; 2303 __be16 cur_msn; 2304 __be16 max_msn; 2305}; 2306 2307struct cpl_srq_table_rpl { 2308 RSS_HDR 2309 union opcode_tid ot; 2310 __u8 status; 2311 __u8 rsvd[2]; 2312 __u8 idx; 2313 __be64 rsvd_pdid; 2314 __be32 qlen_qbase; 2315 __be16 cur_msn; 2316 __be16 max_msn; 2317}; 2318 2319/* cpl_srq_table_{req,rpl}.params fields */ 2320#define S_SRQT_QLEN 28 2321#define M_SRQT_QLEN 0xF 2322#define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) 2323#define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) 2324 2325#define S_SRQT_QBASE 0 2326#define M_SRQT_QBASE 0x3FFFFFF 2327#define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) 2328#define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) 2329 2330#define S_SRQT_PDID 0 2331#define M_SRQT_PDID 0xFF 2332#define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) 2333#define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) 2334 2335#define S_SRQT_IDX 0 2336#define M_SRQT_IDX 0xF 2337#define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) 2338#define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) 2339 2340struct cpl_smt_write_req { 2341 WR_HDR; 2342 union opcode_tid ot; 2343 __be32 params; 2344 __be16 pfvf1; 2345 __u8 src_mac1[6]; 2346 __be16 pfvf0; 2347 __u8 src_mac0[6]; 2348}; 2349 2350struct cpl_t6_smt_write_req { 2351 WR_HDR; 2352 union opcode_tid ot; 2353 __be32 params; 2354 __be64 tag; 2355 __be16 pfvf0; 2356 __u8 src_mac0[6]; 2357 __be32 local_ip; 2358 __be32 rsvd; 2359}; 2360 2361struct cpl_smt_write_rpl { 2362 RSS_HDR 2363 union opcode_tid ot; 2364 __u8 status; 2365 __u8 rsvd[3]; 2366}; 2367 2368struct cpl_smt_read_req { 2369 WR_HDR; 2370 union opcode_tid ot; 2371 __be32 params; 2372}; 2373 2374struct cpl_smt_read_rpl { 2375 RSS_HDR 2376 union opcode_tid ot; 2377 __u8 status; 2378 __u8 ovlan_idx; 2379 __be16 rsvd; 2380 __be16 pfvf1; 2381 __u8 src_mac1[6]; 2382 __be16 pfvf0; 2383 __u8 src_mac0[6]; 2384}; 2385 2386/* cpl_smt_{read,write}_req.params fields */ 2387#define S_SMTW_OVLAN_IDX 16 2388#define M_SMTW_OVLAN_IDX 0xF 2389#define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2390#define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2391 2392#define S_SMTW_IDX 20 2393#define M_SMTW_IDX 0x7F 2394#define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2395#define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2396 2397#define M_T6_SMTW_IDX 0xFF 2398#define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX) 2399 2400#define S_SMTW_NORPL 31 2401#define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2402#define F_SMTW_NORPL V_SMTW_NORPL(1U) 2403 2404/* cpl_smt_{read,write}_req.pfvf? fields */ 2405#define S_SMTW_VF 0 2406#define M_SMTW_VF 0xFF 2407#define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2408#define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2409 2410#define S_SMTW_PF 8 2411#define M_SMTW_PF 0x7 2412#define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2413#define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2414 2415#define S_SMTW_VF_VLD 11 2416#define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2417#define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2418 2419struct cpl_tag_write_req { 2420 WR_HDR; 2421 union opcode_tid ot; 2422 __be32 params; 2423 __be64 tag_val; 2424}; 2425 2426struct cpl_tag_write_rpl { 2427 RSS_HDR 2428 union opcode_tid ot; 2429 __u8 status; 2430 __u8 rsvd[2]; 2431 __u8 idx; 2432}; 2433 2434struct cpl_tag_read_req { 2435 WR_HDR; 2436 union opcode_tid ot; 2437 __be32 params; 2438}; 2439 2440struct cpl_tag_read_rpl { 2441 RSS_HDR 2442 union opcode_tid ot; 2443 __u8 status; 2444#if defined(__LITTLE_ENDIAN_BITFIELD) 2445 __u8 :4; 2446 __u8 tag_len:1; 2447 __u8 :2; 2448 __u8 ins_enable:1; 2449#else 2450 __u8 ins_enable:1; 2451 __u8 :2; 2452 __u8 tag_len:1; 2453 __u8 :4; 2454#endif 2455 __u8 rsvd; 2456 __u8 tag_idx; 2457 __be64 tag_val; 2458}; 2459 2460/* cpl_tag{read,write}_req.params fields */ 2461#define S_TAGW_IDX 0 2462#define M_TAGW_IDX 0x7F 2463#define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2464#define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2465 2466#define S_TAGW_LEN 20 2467#define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2468#define F_TAGW_LEN V_TAGW_LEN(1U) 2469 2470#define S_TAGW_INS_ENABLE 23 2471#define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2472#define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2473 2474#define S_TAGW_NORPL 31 2475#define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2476#define F_TAGW_NORPL V_TAGW_NORPL(1U) 2477 2478struct cpl_barrier { 2479 WR_HDR; 2480 __u8 opcode; 2481 __u8 chan_map; 2482 __be16 rsvd0; 2483 __be32 rsvd1; 2484}; 2485 2486/* cpl_barrier.chan_map fields */ 2487#define S_CHAN_MAP 4 2488#define M_CHAN_MAP 0xF 2489#define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2490#define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2491 2492struct cpl_error { 2493 RSS_HDR 2494 union opcode_tid ot; 2495 __be32 error; 2496}; 2497 2498struct cpl_hit_notify { 2499 RSS_HDR 2500 union opcode_tid ot; 2501 __be32 rsvd; 2502 __be32 info; 2503 __be32 reason; 2504}; 2505 2506struct cpl_pkt_notify { 2507 RSS_HDR 2508 union opcode_tid ot; 2509 __be16 rsvd; 2510 __be16 len; 2511 __be32 info; 2512 __be32 reason; 2513}; 2514 2515/* cpl_{hit,pkt}_notify.info fields */ 2516#define S_NTFY_MAC_IDX 0 2517#define M_NTFY_MAC_IDX 0x1FF 2518#define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2519#define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2520 2521#define S_NTFY_INTF 10 2522#define M_NTFY_INTF 0xF 2523#define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2524#define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2525 2526#define S_NTFY_TCPHDR_LEN 14 2527#define M_NTFY_TCPHDR_LEN 0xF 2528#define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2529#define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2530 2531#define S_NTFY_IPHDR_LEN 18 2532#define M_NTFY_IPHDR_LEN 0x1FF 2533#define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2534#define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2535 2536#define S_NTFY_ETHHDR_LEN 27 2537#define M_NTFY_ETHHDR_LEN 0x1F 2538#define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2539#define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2540 2541#define S_NTFY_T5_IPHDR_LEN 18 2542#define M_NTFY_T5_IPHDR_LEN 0xFF 2543#define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2544#define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2545 2546#define S_NTFY_T5_ETHHDR_LEN 26 2547#define M_NTFY_T5_ETHHDR_LEN 0x3F 2548#define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2549#define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2550 2551struct cpl_rdma_terminate { 2552 RSS_HDR 2553 union opcode_tid ot; 2554 __be16 rsvd; 2555 __be16 len; 2556}; 2557 2558struct cpl_set_le_req { 2559 WR_HDR; 2560 union opcode_tid ot; 2561 __be16 reply_ctrl; 2562 __be16 params; 2563 __be64 mask_hi; 2564 __be64 mask_lo; 2565 __be64 val_hi; 2566 __be64 val_lo; 2567}; 2568 2569/* cpl_set_le_req.reply_ctrl additional fields */ 2570#define S_LE_REQ_IP6 13 2571#define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2572#define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2573 2574/* cpl_set_le_req.params fields */ 2575#define S_LE_CHAN 0 2576#define M_LE_CHAN 0x3 2577#define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2578#define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2579 2580#define S_LE_OFFSET 5 2581#define M_LE_OFFSET 0x7 2582#define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2583#define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2584 2585#define S_LE_MORE 8 2586#define V_LE_MORE(x) ((x) << S_LE_MORE) 2587#define F_LE_MORE V_LE_MORE(1U) 2588 2589#define S_LE_REQSIZE 9 2590#define M_LE_REQSIZE 0x7 2591#define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2592#define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2593 2594#define S_LE_REQCMD 12 2595#define M_LE_REQCMD 0xF 2596#define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2597#define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2598 2599struct cpl_set_le_rpl { 2600 RSS_HDR 2601 union opcode_tid ot; 2602 __u8 chan; 2603 __u8 info; 2604 __be16 len; 2605}; 2606 2607/* cpl_set_le_rpl.info fields */ 2608#define S_LE_RSPCMD 0 2609#define M_LE_RSPCMD 0xF 2610#define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2611#define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2612 2613#define S_LE_RSPSIZE 4 2614#define M_LE_RSPSIZE 0x7 2615#define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2616#define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2617 2618#define S_LE_RSPTYPE 7 2619#define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2620#define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2621 2622struct cpl_sge_egr_update { 2623 RSS_HDR 2624 __be32 opcode_qid; 2625 __be16 cidx; 2626 __be16 pidx; 2627}; 2628 2629/* cpl_sge_egr_update.ot fields */ 2630#define S_AUTOEQU 22 2631#define M_AUTOEQU 0x1 2632#define V_AUTOEQU(x) ((x) << S_AUTOEQU) 2633#define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) 2634 2635#define S_EGR_QID 0 2636#define M_EGR_QID 0x1FFFF 2637#define V_EGR_QID(x) ((x) << S_EGR_QID) 2638#define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2639 2640/* cpl_fw*.type values */ 2641enum { 2642 FW_TYPE_CMD_RPL = 0, 2643 FW_TYPE_WR_RPL = 1, 2644 FW_TYPE_CQE = 2, 2645 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2646 FW_TYPE_RSSCPL = 4, 2647 FW_TYPE_WRERR_RPL = 5, 2648 FW_TYPE_PI_ERR = 6, 2649 FW_TYPE_TLS_KEY = 7, 2650}; 2651 2652struct cpl_fw2_pld { 2653 RSS_HDR 2654 u8 opcode; 2655 u8 rsvd[5]; 2656 __be16 len; 2657}; 2658 2659struct cpl_fw4_pld { 2660 RSS_HDR 2661 u8 opcode; 2662 u8 rsvd0[3]; 2663 u8 type; 2664 u8 rsvd1; 2665 __be16 len; 2666 __be64 data; 2667 __be64 rsvd2; 2668}; 2669 2670struct cpl_fw6_pld { 2671 RSS_HDR 2672 u8 opcode; 2673 u8 rsvd[5]; 2674 __be16 len; 2675 __be64 data[4]; 2676}; 2677 2678struct cpl_fw2_msg { 2679 RSS_HDR 2680 union opcode_info oi; 2681}; 2682 2683struct cpl_fw4_msg { 2684 RSS_HDR 2685 u8 opcode; 2686 u8 type; 2687 __be16 rsvd0; 2688 __be32 rsvd1; 2689 __be64 data[2]; 2690}; 2691 2692struct cpl_fw4_ack { 2693 RSS_HDR 2694 union opcode_tid ot; 2695 u8 credits; 2696 u8 rsvd0[2]; 2697 u8 flags; 2698 __be32 snd_nxt; 2699 __be32 snd_una; 2700 __be64 rsvd1; 2701}; 2702 2703enum { 2704 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2705 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2706 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2707}; 2708 2709struct cpl_fw6_msg { 2710 RSS_HDR 2711 u8 opcode; 2712 u8 type; 2713 __be16 rsvd0; 2714 __be32 rsvd1; 2715 __be64 data[4]; 2716}; 2717 2718/* cpl_fw6_msg.type values */ 2719enum { 2720 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2721 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2722 FW6_TYPE_CQE = FW_TYPE_CQE, 2723 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2724 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2725 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL, 2726 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR, 2727 NUM_FW6_TYPES 2728}; 2729 2730struct cpl_fw6_msg_ofld_connection_wr_rpl { 2731 __u64 cookie; 2732 __be32 tid; /* or atid in case of active failure */ 2733 __u8 t_state; 2734 __u8 retval; 2735 __u8 rsvd[2]; 2736}; 2737 2738/* ULP_TX opcodes */ 2739enum { 2740 ULP_TX_MEM_READ = 2, 2741 ULP_TX_MEM_WRITE = 3, 2742 ULP_TX_PKT = 4 2743}; 2744 2745enum { 2746 ULP_TX_SC_NOOP = 0x80, 2747 ULP_TX_SC_IMM = 0x81, 2748 ULP_TX_SC_DSGL = 0x82, 2749 ULP_TX_SC_ISGL = 0x83, 2750 ULP_TX_SC_PICTRL = 0x84, 2751 ULP_TX_SC_MEMRD = 0x86 2752}; 2753 2754#define S_ULPTX_CMD 24 2755#define M_ULPTX_CMD 0xFF 2756#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2757 2758#define S_ULPTX_LEN16 0 2759#define M_ULPTX_LEN16 0xFF 2760#define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2761 2762#define S_ULP_TX_SC_MORE 23 2763#define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2764#define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2765 2766struct ulptx_sge_pair { 2767 __be32 len[2]; 2768 __be64 addr[2]; 2769}; 2770 2771struct ulptx_sgl { 2772 __be32 cmd_nsge; 2773 __be32 len0; 2774 __be64 addr0; 2775#if !(defined C99_NOT_SUPPORTED) 2776 struct ulptx_sge_pair sge[0]; 2777#endif 2778}; 2779 2780struct ulptx_isge { 2781 __be32 stag; 2782 __be32 len; 2783 __be64 target_ofst; 2784}; 2785 2786struct ulptx_isgl { 2787 __be32 cmd_nisge; 2788 __be32 rsvd; 2789#if !(defined C99_NOT_SUPPORTED) 2790 struct ulptx_isge sge[0]; 2791#endif 2792}; 2793 2794struct ulptx_idata { 2795 __be32 cmd_more; 2796 __be32 len; 2797}; 2798 2799#define S_ULPTX_NSGE 0 2800#define M_ULPTX_NSGE 0xFFFF 2801#define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2802#define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) 2803 2804struct ulptx_sc_memrd { 2805 __be32 cmd_to_len; 2806 __be32 addr; 2807}; 2808 2809struct ulp_mem_io { 2810 WR_HDR; 2811 __be32 cmd; 2812 __be32 len16; /* command length */ 2813 __be32 dlen; /* data length in 32-byte units */ 2814 __be32 lock_addr; 2815}; 2816 2817/* additional ulp_mem_io.cmd fields */ 2818#define S_ULP_MEMIO_ORDER 23 2819#define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2820#define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2821 2822#define S_T5_ULP_MEMIO_IMM 23 2823#define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2824#define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2825 2826#define S_T5_ULP_MEMIO_ORDER 22 2827#define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2828#define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2829 2830#define S_T5_ULP_MEMIO_FID 4 2831#define M_T5_ULP_MEMIO_FID 0x7ff 2832#define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID) 2833 2834/* ulp_mem_io.lock_addr fields */ 2835#define S_ULP_MEMIO_ADDR 0 2836#define M_ULP_MEMIO_ADDR 0x7FFFFFF 2837#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2838 2839#define S_ULP_MEMIO_LOCK 31 2840#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2841#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2842 2843/* ulp_mem_io.dlen fields */ 2844#define S_ULP_MEMIO_DATA_LEN 0 2845#define M_ULP_MEMIO_DATA_LEN 0x1F 2846#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2847 2848/* ULP_TXPKT field values */ 2849enum { 2850 ULP_TXPKT_DEST_TP = 0, 2851 ULP_TXPKT_DEST_SGE, 2852 ULP_TXPKT_DEST_UP, 2853 ULP_TXPKT_DEST_DEVNULL, 2854}; 2855 2856struct ulp_txpkt { 2857 __be32 cmd_dest; 2858 __be32 len; 2859}; 2860 2861/* ulp_txpkt.cmd_dest fields */ 2862#define S_ULP_TXPKT_DATAMODIFY 23 2863#define M_ULP_TXPKT_DATAMODIFY 0x1 2864#define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY) 2865#define G_ULP_TXPKT_DATAMODIFY(x) \ 2866 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_) 2867#define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U) 2868 2869#define S_ULP_TXPKT_CHANNELID 22 2870#define M_ULP_TXPKT_CHANNELID 0x1 2871#define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID) 2872#define G_ULP_TXPKT_CHANNELID(x) \ 2873 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID) 2874#define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U) 2875 2876/* ulp_txpkt.cmd_dest fields */ 2877#define S_ULP_TXPKT_DEST 16 2878#define M_ULP_TXPKT_DEST 0x3 2879#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2880 2881#define S_ULP_TXPKT_FID 4 2882#define M_ULP_TXPKT_FID 0x7ff 2883#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2884 2885#define S_ULP_TXPKT_RO 3 2886#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2887#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2888 2889enum cpl_tx_tnl_lso_type { 2890 TX_TNL_TYPE_OPAQUE, 2891 TX_TNL_TYPE_NVGRE, 2892 TX_TNL_TYPE_VXLAN, 2893 TX_TNL_TYPE_GENEVE, 2894}; 2895 2896struct cpl_tx_tnl_lso { 2897 __be32 op_to_IpIdSplitOut; 2898 __be16 IpIdOffsetOut; 2899 __be16 UdpLenSetOut_to_TnlHdrLen; 2900 __be64 r1; 2901 __be32 Flow_to_TcpHdrLen; 2902 __be16 IpIdOffset; 2903 __be16 IpIdSplit_to_Mss; 2904 __be32 TCPSeqOffset; 2905 __be32 EthLenOffset_Size; 2906 /* encapsulated CPL (TX_PKT_XT) follows here */ 2907}; 2908 2909#define S_CPL_TX_TNL_LSO_OPCODE 24 2910#define M_CPL_TX_TNL_LSO_OPCODE 0xff 2911#define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) 2912#define G_CPL_TX_TNL_LSO_OPCODE(x) \ 2913 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE) 2914 2915#define S_CPL_TX_TNL_LSO_FIRST 23 2916#define M_CPL_TX_TNL_LSO_FIRST 0x1 2917#define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST) 2918#define G_CPL_TX_TNL_LSO_FIRST(x) \ 2919 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST) 2920#define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U) 2921 2922#define S_CPL_TX_TNL_LSO_LAST 22 2923#define M_CPL_TX_TNL_LSO_LAST 0x1 2924#define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST) 2925#define G_CPL_TX_TNL_LSO_LAST(x) \ 2926 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST) 2927#define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U) 2928 2929#define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21 2930#define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1 2931#define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 2932 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 2933#define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 2934 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 2935#define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U) 2936 2937#define S_CPL_TX_TNL_LSO_IPV6OUT 20 2938#define M_CPL_TX_TNL_LSO_IPV6OUT 0x1 2939#define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT) 2940#define G_CPL_TX_TNL_LSO_IPV6OUT(x) \ 2941 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT) 2942#define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U) 2943 2944#define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16 2945#define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf 2946#define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 2947 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT) 2948#define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 2949 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT) 2950 2951#define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4 2952#define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff 2953#define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) 2954#define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ 2955 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT) 2956 2957#define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3 2958#define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1 2959#define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT) 2960#define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ 2961 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT) 2962#define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U) 2963 2964#define S_CPL_TX_TNL_LSO_IPLENSETOUT 2 2965#define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1 2966#define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT) 2967#define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ 2968 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT) 2969#define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U) 2970 2971#define S_CPL_TX_TNL_LSO_IPIDINCOUT 1 2972#define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1 2973#define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT) 2974#define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ 2975 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT) 2976#define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U) 2977 2978#define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0 2979#define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1 2980#define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 2981 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT) 2982#define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 2983 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT) 2984#define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U) 2985 2986#define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15 2987#define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1 2988#define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 2989 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT) 2990#define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 2991 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT) 2992#define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U) 2993 2994#define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14 2995#define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1 2996#define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 2997 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT) 2998#define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 2999 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3000#define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U) 3001 3002#define S_CPL_TX_TNL_LSO_TNLTYPE 12 3003#define M_CPL_TX_TNL_LSO_TNLTYPE 0x3 3004#define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) 3005#define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ 3006 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE) 3007 3008#define S_CPL_TX_TNL_LSO_TNLHDRLEN 0 3009#define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff 3010#define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) 3011#define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ 3012 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN) 3013 3014#define S_CPL_TX_TNL_LSO_FLOW 21 3015#define M_CPL_TX_TNL_LSO_FLOW 0x1 3016#define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW) 3017#define G_CPL_TX_TNL_LSO_FLOW(x) \ 3018 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW) 3019#define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U) 3020 3021#define S_CPL_TX_TNL_LSO_IPV6 20 3022#define M_CPL_TX_TNL_LSO_IPV6 0x1 3023#define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6) 3024#define G_CPL_TX_TNL_LSO_IPV6(x) \ 3025 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6) 3026#define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U) 3027 3028#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 3029#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 3030#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 3031#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 3032 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 3033 3034#define S_CPL_TX_TNL_LSO_IPHDRLEN 4 3035#define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff 3036#define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) 3037#define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ 3038 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN) 3039 3040#define S_CPL_TX_TNL_LSO_TCPHDRLEN 0 3041#define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf 3042#define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) 3043#define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ 3044 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN) 3045 3046#define S_CPL_TX_TNL_LSO_IPIDSPLIT 15 3047#define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1 3048#define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT) 3049#define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ 3050 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT) 3051#define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U) 3052 3053#define S_CPL_TX_TNL_LSO_ETHHDRLENX 14 3054#define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1 3055#define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX) 3056#define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ 3057 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX) 3058#define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U) 3059 3060#define S_CPL_TX_TNL_LSO_MSS 0 3061#define M_CPL_TX_TNL_LSO_MSS 0x3fff 3062#define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) 3063#define G_CPL_TX_TNL_LSO_MSS(x) \ 3064 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS) 3065 3066#define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28 3067#define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf 3068#define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3069 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET) 3070#define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3071 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET) 3072 3073#define S_CPL_TX_TNL_LSO_SIZE 0 3074#define M_CPL_TX_TNL_LSO_SIZE 0xfffffff 3075#define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) 3076#define G_CPL_TX_TNL_LSO_SIZE(x) \ 3077 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) 3078 3079struct cpl_rx_mps_pkt { 3080 __be32 op_to_r1_hi; 3081 __be32 r1_lo_length; 3082}; 3083 3084#define S_CPL_RX_MPS_PKT_OP 24 3085#define M_CPL_RX_MPS_PKT_OP 0xff 3086#define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) 3087#define G_CPL_RX_MPS_PKT_OP(x) \ 3088 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP) 3089 3090#define S_CPL_RX_MPS_PKT_TYPE 20 3091#define M_CPL_RX_MPS_PKT_TYPE 0xf 3092#define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) 3093#define G_CPL_RX_MPS_PKT_TYPE(x) \ 3094 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE) 3095 3096/* 3097 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field. 3098 */ 3099#define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0) 3100#define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1) 3101#define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2) 3102#define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3) 3103 3104struct cpl_tx_tls_sfo { 3105 __be32 op_to_seg_len; 3106 __be32 pld_len; 3107 __be64 rsvd; 3108 __be32 seqno_numivs; 3109 __be32 ivgen_hdrlen; 3110 __be64 scmd1; 3111}; 3112 3113/* cpl_tx_tls_sfo macros */ 3114#define S_CPL_TX_TLS_SFO_OPCODE 24 3115#define M_CPL_TX_TLS_SFO_OPCODE 0xff 3116#define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) 3117#define G_CPL_TX_TLS_SFO_OPCODE(x) \ 3118 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE) 3119 3120#define S_CPL_TX_TLS_SFO_DATA_TYPE 20 3121#define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf 3122#define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) 3123#define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ 3124 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE) 3125 3126#define S_CPL_TX_TLS_SFO_CPL_LEN 16 3127#define M_CPL_TX_TLS_SFO_CPL_LEN 0xf 3128#define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) 3129#define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ 3130 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN) 3131#define S_CPL_TX_TLS_SFO_SEG_LEN 0 3132#define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff 3133#define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) 3134#define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ 3135 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN) 3136 3137struct cpl_tls_data { 3138 RSS_HDR 3139 __be32 op_tid; 3140 __be32 length_pkd; 3141 __be32 seq; 3142 __be32 r1; 3143}; 3144 3145#define S_CPL_TLS_DATA_OPCODE 24 3146#define M_CPL_TLS_DATA_OPCODE 0xff 3147#define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) 3148#define G_CPL_TLS_DATA_OPCODE(x) \ 3149 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE) 3150 3151#define S_CPL_TLS_DATA_TID 0 3152#define M_CPL_TLS_DATA_TID 0xffffff 3153#define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) 3154#define G_CPL_TLS_DATA_TID(x) \ 3155 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID) 3156 3157#define S_CPL_TLS_DATA_LENGTH 0 3158#define M_CPL_TLS_DATA_LENGTH 0xffff 3159#define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) 3160#define G_CPL_TLS_DATA_LENGTH(x) \ 3161 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH) 3162 3163struct cpl_rx_tls_cmp { 3164 RSS_HDR 3165 __be32 op_tid; 3166 __be32 pdulength_length; 3167 __be32 seq; 3168 __be32 ddp_report; 3169 __be32 r; 3170 __be32 ddp_valid; 3171}; 3172 3173#define S_CPL_RX_TLS_CMP_OPCODE 24 3174#define M_CPL_RX_TLS_CMP_OPCODE 0xff 3175#define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) 3176#define G_CPL_RX_TLS_CMP_OPCODE(x) \ 3177 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE) 3178 3179#define S_CPL_RX_TLS_CMP_TID 0 3180#define M_CPL_RX_TLS_CMP_TID 0xffffff 3181#define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) 3182#define G_CPL_RX_TLS_CMP_TID(x) \ 3183 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID) 3184 3185#define S_CPL_RX_TLS_CMP_PDULENGTH 16 3186#define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff 3187#define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) 3188#define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ 3189 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH) 3190 3191#define S_CPL_RX_TLS_CMP_LENGTH 0 3192#define M_CPL_RX_TLS_CMP_LENGTH 0xffff 3193#define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) 3194#define G_CPL_RX_TLS_CMP_LENGTH(x) \ 3195 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH) 3196 3197#define S_SCMD_SEQ_NO_CTRL 29 3198#define M_SCMD_SEQ_NO_CTRL 0x3 3199#define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL) 3200#define G_SCMD_SEQ_NO_CTRL(x) \ 3201 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL) 3202 3203/* StsFieldPrsnt- Status field at the end of the TLS PDU */ 3204#define S_SCMD_STATUS_PRESENT 28 3205#define M_SCMD_STATUS_PRESENT 0x1 3206#define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT) 3207#define G_SCMD_STATUS_PRESENT(x) \ 3208 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT) 3209#define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U) 3210 3211/* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 3212 * 3-15: Reserved. */ 3213#define S_SCMD_PROTO_VERSION 24 3214#define M_SCMD_PROTO_VERSION 0xf 3215#define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION) 3216#define G_SCMD_PROTO_VERSION(x) \ 3217 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION) 3218 3219/* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 3220#define S_SCMD_ENC_DEC_CTRL 23 3221#define M_SCMD_ENC_DEC_CTRL 0x1 3222#define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL) 3223#define G_SCMD_ENC_DEC_CTRL(x) \ 3224 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL) 3225#define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U) 3226 3227/* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 3228#define S_SCMD_CIPH_AUTH_SEQ_CTRL 22 3229#define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1 3230#define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3231 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL) 3232#define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3233 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL) 3234#define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U) 3235 3236/* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 3237 * 4:Generic-AES, 5-15: Reserved. */ 3238#define S_SCMD_CIPH_MODE 18 3239#define M_SCMD_CIPH_MODE 0xf 3240#define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE) 3241#define G_SCMD_CIPH_MODE(x) \ 3242 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE) 3243 3244/* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 3245 * 4-15: Reserved */ 3246#define S_SCMD_AUTH_MODE 14 3247#define M_SCMD_AUTH_MODE 0xf 3248#define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE) 3249#define G_SCMD_AUTH_MODE(x) \ 3250 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE) 3251 3252/* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 3253 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 3254 */ 3255#define S_SCMD_HMAC_CTRL 11 3256#define M_SCMD_HMAC_CTRL 0x7 3257#define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL) 3258#define G_SCMD_HMAC_CTRL(x) \ 3259 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL) 3260 3261/* IvSize - IV size in units of 2 bytes */ 3262#define S_SCMD_IV_SIZE 7 3263#define M_SCMD_IV_SIZE 0xf 3264#define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE) 3265#define G_SCMD_IV_SIZE(x) \ 3266 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE) 3267 3268/* NumIVs - Number of IVs */ 3269#define S_SCMD_NUM_IVS 0 3270#define M_SCMD_NUM_IVS 0x7f 3271#define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS) 3272#define G_SCMD_NUM_IVS(x) \ 3273 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS) 3274 3275/* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 3276 * (below) are used as Cid (connection id for debug status), these 3277 * bits are padded to zero for forming the 64 bit 3278 * sequence number for TLS 3279 */ 3280#define S_SCMD_ENB_DBGID 31 3281#define M_SCMD_ENB_DBGID 0x1 3282#define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) 3283#define G_SCMD_ENB_DBGID(x) \ 3284 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID) 3285 3286/* IV generation in SW. */ 3287#define S_SCMD_IV_GEN_CTRL 30 3288#define M_SCMD_IV_GEN_CTRL 0x1 3289#define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL) 3290#define G_SCMD_IV_GEN_CTRL(x) \ 3291 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL) 3292#define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U) 3293 3294/* More frags */ 3295#define S_SCMD_MORE_FRAGS 20 3296#define M_SCMD_MORE_FRAGS 0x1 3297#define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS) 3298#define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) 3299 3300/*last frag */ 3301#define S_SCMD_LAST_FRAG 19 3302#define M_SCMD_LAST_FRAG 0x1 3303#define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG) 3304#define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) 3305 3306/* TlsCompPdu */ 3307#define S_SCMD_TLS_COMPPDU 18 3308#define M_SCMD_TLS_COMPPDU 0x1 3309#define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) 3310#define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) 3311 3312/* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 3313#define S_SCMD_KEY_CTX_INLINE 17 3314#define M_SCMD_KEY_CTX_INLINE 0x1 3315#define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE) 3316#define G_SCMD_KEY_CTX_INLINE(x) \ 3317 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE) 3318#define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U) 3319 3320/* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 3321#define S_SCMD_TLS_FRAG_ENABLE 16 3322#define M_SCMD_TLS_FRAG_ENABLE 0x1 3323#define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE) 3324#define G_SCMD_TLS_FRAG_ENABLE(x) \ 3325 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE) 3326#define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U) 3327 3328/* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 3329 * modes, in this case TLS_TX will drop the PDU and only 3330 * send back the MAC bytes. */ 3331#define S_SCMD_MAC_ONLY 15 3332#define M_SCMD_MAC_ONLY 0x1 3333#define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY) 3334#define G_SCMD_MAC_ONLY(x) \ 3335 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY) 3336#define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U) 3337 3338/* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 3339 * which have complex AAD and IV formations Eg:AES-CCM 3340 */ 3341#define S_SCMD_AADIVDROP 14 3342#define M_SCMD_AADIVDROP 0x1 3343#define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP) 3344#define G_SCMD_AADIVDROP(x) \ 3345 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP) 3346#define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U) 3347 3348/* HdrLength - Length of all headers excluding TLS header 3349 * present before start of crypto PDU/payload. */ 3350#define S_SCMD_HDR_LEN 0 3351#define M_SCMD_HDR_LEN 0x3fff 3352#define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN) 3353#define G_SCMD_HDR_LEN(x) \ 3354 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN) 3355 3356struct cpl_tx_sec_pdu { 3357 __be32 op_ivinsrtofst; 3358 __be32 pldlen; 3359 __be32 aadstart_cipherstop_hi; 3360 __be32 cipherstop_lo_authinsert; 3361 __be32 seqno_numivs; 3362 __be32 ivgen_hdrlen; 3363 __be64 scmd1; 3364}; 3365 3366#define S_CPL_TX_SEC_PDU_OPCODE 24 3367#define M_CPL_TX_SEC_PDU_OPCODE 0xff 3368#define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE) 3369#define G_CPL_TX_SEC_PDU_OPCODE(x) \ 3370 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE) 3371 3372/* RX Channel Id */ 3373#define S_CPL_TX_SEC_PDU_RXCHID 22 3374#define M_CPL_TX_SEC_PDU_RXCHID 0x1 3375#define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID) 3376#define G_CPL_TX_SEC_PDU_RXCHID(x) \ 3377(((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID) 3378#define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U) 3379 3380/* Ack Follows */ 3381#define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21 3382#define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1 3383#define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS) 3384#define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ 3385(((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS) 3386#define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U) 3387 3388/* Loopback bit in cpl_tx_sec_pdu */ 3389#define S_CPL_TX_SEC_PDU_ULPTXLPBK 20 3390#define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1 3391#define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK) 3392#define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ 3393(((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK) 3394#define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U) 3395 3396/* Length of cpl header encapsulated */ 3397#define S_CPL_TX_SEC_PDU_CPLLEN 16 3398#define M_CPL_TX_SEC_PDU_CPLLEN 0xf 3399#define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN) 3400#define G_CPL_TX_SEC_PDU_CPLLEN(x) \ 3401 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN) 3402 3403/* PlaceHolder */ 3404#define S_CPL_TX_SEC_PDU_PLACEHOLDER 10 3405#define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1 3406#define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER) 3407#define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ 3408 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \ 3409 M_CPL_TX_SEC_PDU_PLACEHOLDER) 3410 3411/* IvInsrtOffset: Insertion location for IV */ 3412#define S_CPL_TX_SEC_PDU_IVINSRTOFST 0 3413#define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff 3414#define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST) 3415#define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ 3416 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \ 3417 M_CPL_TX_SEC_PDU_IVINSRTOFST) 3418 3419/* AadStartOffset: Offset in bytes for AAD start from 3420 * the first byte following 3421 * the pkt headers (0-255 3422 * bytes) */ 3423#define S_CPL_TX_SEC_PDU_AADSTART 24 3424#define M_CPL_TX_SEC_PDU_AADSTART 0xff 3425#define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART) 3426#define G_CPL_TX_SEC_PDU_AADSTART(x) \ 3427 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \ 3428 M_CPL_TX_SEC_PDU_AADSTART) 3429 3430/* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 3431 * the pkt headers (0-511 bytes) */ 3432#define S_CPL_TX_SEC_PDU_AADSTOP 15 3433#define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff 3434#define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP) 3435#define G_CPL_TX_SEC_PDU_AADSTOP(x) \ 3436 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP) 3437 3438/* CipherStartOffset: offset in bytes for encryption/decryption start from the 3439 * first byte following the pkt headers (0-1023 3440 * bytes) */ 3441#define S_CPL_TX_SEC_PDU_CIPHERSTART 5 3442#define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff 3443#define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART) 3444#define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ 3445 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \ 3446 M_CPL_TX_SEC_PDU_CIPHERSTART) 3447 3448/* CipherStopOffset: offset in bytes for encryption/decryption end 3449 * from end of the payload of this command (0-511 bytes) */ 3450#define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0 3451#define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f 3452#define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3453 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3454#define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3455 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \ 3456 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3457 3458#define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28 3459#define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf 3460#define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3461 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3462#define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3463 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \ 3464 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3465 3466/* AuthStartOffset: offset in bytes for authentication start from 3467 * the first byte following the pkt headers (0-1023) 3468 * */ 3469#define S_CPL_TX_SEC_PDU_AUTHSTART 18 3470#define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff 3471#define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART) 3472#define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ 3473 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \ 3474 M_CPL_TX_SEC_PDU_AUTHSTART) 3475 3476/* AuthStopOffset: offset in bytes for authentication 3477 * end from end of the payload of this command (0-511 Bytes) */ 3478#define S_CPL_TX_SEC_PDU_AUTHSTOP 9 3479#define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff 3480#define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP) 3481#define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ 3482 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \ 3483 M_CPL_TX_SEC_PDU_AUTHSTOP) 3484 3485/* AuthInsrtOffset: offset in bytes for authentication insertion 3486 * from end of the payload of this command (0-511 bytes) */ 3487#define S_CPL_TX_SEC_PDU_AUTHINSERT 0 3488#define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff 3489#define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT) 3490#define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ 3491 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \ 3492 M_CPL_TX_SEC_PDU_AUTHINSERT) 3493 3494struct cpl_rx_phys_dsgl { 3495 __be32 op_to_tid; 3496 __be32 pcirlxorder_to_noofsgentr; 3497 struct rss_header rss_hdr_int; 3498}; 3499 3500#define S_CPL_RX_PHYS_DSGL_OPCODE 24 3501#define M_CPL_RX_PHYS_DSGL_OPCODE 0xff 3502#define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE) 3503#define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ 3504 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE) 3505 3506#define S_CPL_RX_PHYS_DSGL_ISRDMA 23 3507#define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1 3508#define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA) 3509#define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ 3510 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA) 3511#define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U) 3512 3513#define S_CPL_RX_PHYS_DSGL_RSVD1 20 3514#define M_CPL_RX_PHYS_DSGL_RSVD1 0x7 3515#define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1) 3516#define G_CPL_RX_PHYS_DSGL_RSVD1(x) \ 3517 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1) 3518 3519#define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31 3520#define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1 3521#define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3522 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3523#define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3524 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \ 3525 M_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3526#define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U) 3527 3528#define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30 3529#define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1 3530#define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3531 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3532#define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3533 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \ 3534 M_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3535#define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U) 3536 3537#define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29 3538#define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1 3539#define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3540 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3541#define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3542 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \ 3543 M_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3544#define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U) 3545 3546#define S_CPL_RX_PHYS_DSGL_PCITPHNT 27 3547#define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3 3548#define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) 3549#define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ 3550 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \ 3551 M_CPL_RX_PHYS_DSGL_PCITPHNT) 3552 3553#define S_CPL_RX_PHYS_DSGL_DCAID 16 3554#define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff 3555#define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID) 3556#define G_CPL_RX_PHYS_DSGL_DCAID(x) \ 3557 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \ 3558 M_CPL_RX_PHYS_DSGL_DCAID) 3559 3560#define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0 3561#define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff 3562#define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3563 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3564#define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3565 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \ 3566 M_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3567 3568/* CPL_TX_TLS_ACK */ 3569struct cpl_tx_tls_ack { 3570 __be32 op_to_Rsvd2; 3571 __be32 PldLen; 3572 __be64 Rsvd3; 3573}; 3574 3575#define S_CPL_TX_TLS_ACK_OPCODE 24 3576#define M_CPL_TX_TLS_ACK_OPCODE 0xff 3577#define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) 3578#define G_CPL_TX_TLS_ACK_OPCODE(x) \ 3579 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) 3580 3581#define S_CPL_TX_TLS_ACK_RSVD1 23 3582#define M_CPL_TX_TLS_ACK_RSVD1 0x1 3583#define V_CPL_TX_TLS_ACK_RSVD1(x) ((x) << S_CPL_TX_TLS_ACK_RSVD1) 3584#define G_CPL_TX_TLS_ACK_RSVD1(x) \ 3585 (((x) >> S_CPL_TX_TLS_ACK_RSVD1) & M_CPL_TX_TLS_ACK_RSVD1) 3586#define F_CPL_TX_TLS_ACK_RSVD1 V_CPL_TX_TLS_ACK_RSVD1(1U) 3587 3588#define S_CPL_TX_TLS_ACK_RXCHID 22 3589#define M_CPL_TX_TLS_ACK_RXCHID 0x1 3590#define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID) 3591#define G_CPL_TX_TLS_ACK_RXCHID(x) \ 3592 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID) 3593#define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U) 3594 3595#define S_CPL_TX_TLS_ACK_FWMSG 21 3596#define M_CPL_TX_TLS_ACK_FWMSG 0x1 3597#define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG) 3598#define G_CPL_TX_TLS_ACK_FWMSG(x) \ 3599 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG) 3600#define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U) 3601 3602#define S_CPL_TX_TLS_ACK_ULPTXLPBK 20 3603#define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1 3604#define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK) 3605#define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ 3606 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK) 3607#define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U) 3608 3609#define S_CPL_TX_TLS_ACK_CPLLEN 16 3610#define M_CPL_TX_TLS_ACK_CPLLEN 0xf 3611#define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) 3612#define G_CPL_TX_TLS_ACK_CPLLEN(x) \ 3613 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN) 3614 3615#define S_CPL_TX_TLS_ACK_COMPLONERR 15 3616#define M_CPL_TX_TLS_ACK_COMPLONERR 0x1 3617#define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR) 3618#define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ 3619 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR) 3620#define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U) 3621 3622#define S_CPL_TX_TLS_ACK_LCB 14 3623#define M_CPL_TX_TLS_ACK_LCB 0x1 3624#define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB) 3625#define G_CPL_TX_TLS_ACK_LCB(x) \ 3626 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB) 3627#define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U) 3628 3629#define S_CPL_TX_TLS_ACK_PHASH 13 3630#define M_CPL_TX_TLS_ACK_PHASH 0x1 3631#define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH) 3632#define G_CPL_TX_TLS_ACK_PHASH(x) \ 3633 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH) 3634#define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U) 3635 3636#define S_CPL_TX_TLS_ACK_RSVD2 0 3637#define M_CPL_TX_TLS_ACK_RSVD2 0x1fff 3638#define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2) 3639#define G_CPL_TX_TLS_ACK_RSVD2(x) \ 3640 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2) 3641 3642#endif /* T4_MSG_H */ 3643