t4dwave.h revision 331722
1250003Sadrian/*- 2250003Sadrian * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 3250003Sadrian * All rights reserved. 4250003Sadrian * 5250003Sadrian * Redistribution and use in source and binary forms, with or without 6250003Sadrian * modification, are permitted provided that the following conditions 7250003Sadrian * are met: 8250003Sadrian * 1. Redistributions of source code must retain the above copyright 9250003Sadrian * notice, this list of conditions and the following disclaimer. 10250003Sadrian * 2. Redistributions in binary form must reproduce the above copyright 11250003Sadrian * notice, this list of conditions and the following disclaimer in the 12250003Sadrian * documentation and/or other materials provided with the distribution. 13250003Sadrian * 14250003Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15250003Sadrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16250003Sadrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17250003Sadrian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18250003Sadrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19250003Sadrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20250003Sadrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21250003Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22250003Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23250003Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24250003Sadrian * SUCH DAMAGE. 25250003Sadrian * 26250003Sadrian * $FreeBSD: stable/11/sys/dev/sound/pci/t4dwave.h 331722 2018-03-29 02:50:57Z eadler $ 27250003Sadrian */ 28250003Sadrian 29250003Sadrian#ifndef _T4DWAVE_REG_H 30250003Sadrian#define _T4DWAVE_REG_H 31250003Sadrian 32250003Sadrian#define TR_REG_CIR 0xa0 33250003Sadrian#define TR_CIR_MASK 0x0000003f 34250003Sadrian#define TR_CIR_ADDRENA 0x00001000 35250003Sadrian#define TR_CIR_MIDENA 0x00002000 36250003Sadrian#define TR_REG_MISCINT 0xb0 37250003Sadrian#define TR_INT_ADDR 0x00000020 38250003Sadrian#define TR_INT_SB 0x00000004 39250003Sadrian 40250003Sadrian#define TR_REG_DMAR0 0x00 41250003Sadrian#define TR_REG_DMAR4 0x04 42250003Sadrian#define TR_REG_DMAR11 0x0b 43250003Sadrian#define TR_REG_DMAR15 0x0f 44250003Sadrian#define TR_REG_SBR4 0x14 45250003Sadrian#define TR_REG_SBR5 0x15 46250003Sadrian#define TR_SB_INTSTATUS 0x82 47250003Sadrian#define TR_REG_SBR9 0x1e 48250003Sadrian#define TR_REG_SBR10 0x1f 49250003Sadrian#define TR_REG_SBBL 0xc0 50250003Sadrian#define TR_REG_SBCTRL 0xc4 51250003Sadrian#define TR_REG_SBDELTA 0xac 52250003Sadrian 53250003Sadrian#define TR_CDC_DATA 16 54250003Sadrian#define TDX_REG_CODECWR 0x40 55250003Sadrian#define TDX_REG_CODECRD 0x44 56250003Sadrian#define TDX_CDC_RWSTAT 0x00008000 57250003Sadrian#define TDX_REG_CODECST 0x48 58250003Sadrian#define TDX_CDC_SBCTRL 0x40 59250003Sadrian#define TDX_CDC_ACTIVE 0x20 60250008Sadrian#define TDX_CDC_READY 0x10 61250008Sadrian#define TDX_CDC_ADCON 0x08 62250008Sadrian#define TDX_CDC_DACON 0x02 63250008Sadrian#define TDX_CDC_RESET 0x01 64250003Sadrian#define TDX_CDC_ON (TDX_CDC_ADCON|TDX_CDC_DACON) 65250003Sadrian 66250003Sadrian#define SPA_REG_CODECRD 0x44 67250008Sadrian#define SPA_REG_CODECWR 0x40 68250008Sadrian#define SPA_REG_CODECST 0x48 69250003Sadrian#define SPA_RST_OFF 0x0f0000 70250008Sadrian#define SPA_REG_GPIO 0x48 71250003Sadrian#define SPA_CDC_RWSTAT 0x00008000 72250003Sadrian 73250003Sadrian#define TNX_REG_CODECWR 0x44 74250003Sadrian#define TNX_REG_CODEC1RD 0x48 75250008Sadrian#define TNX_REG_CODEC2RD 0x4c 76250008Sadrian#define TNX_CDC_RWSTAT 0x00000c00 77250003Sadrian#define TNX_CDC_SEC 0x00000100 78250003Sadrian#define TNX_REG_CODECST 0x40 79250003Sadrian#define TNX_CDC_READY2 0x40 80250003Sadrian#define TNX_CDC_ADC2ON 0x20 81250003Sadrian#define TNX_CDC_DAC2ON 0x10 82250008Sadrian#define TNX_CDC_READY1 0x08 83250008Sadrian#define TNX_CDC_ADC1ON 0x04 84250003Sadrian#define TNX_CDC_DAC1ON 0x02 85250008Sadrian#define TNX_CDC_RESET 0x01 86250003Sadrian#define TNX_CDC_ON (TNX_CDC_ADC1ON|TNX_CDC_DAC1ON) 87250003Sadrian 88250003Sadrian 89250003Sadrian#define TR_REG_STARTA 0x80 90250008Sadrian#define TR_REG_STOPA 0x84 91250008Sadrian#define TR_REG_CSPF_A 0x90 92250003Sadrian#define TR_REG_ADDRINTA 0x98 93250003Sadrian#define TR_REG_INTENA 0xa4 94250003Sadrian 95250003Sadrian#define TR_REG_STARTB 0xb4 96250003Sadrian#define TR_REG_STOPB 0xb8 97250003Sadrian#define TR_REG_CSPF_B 0xbc 98250003Sadrian#define TR_REG_ADDRINTB 0xd8 99250003Sadrian#define TR_REG_INTENB 0xdc 100250003Sadrian 101250003Sadrian#define TR_REG_CHNBASE 0xe0 102250003Sadrian#define TR_CHN_REGS 5 103250003Sadrian 104250003Sadrian#endif 105250003Sadrian