pmap.c revision 324400
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2003 Peter Wemm 9 * All rights reserved. 10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 11 * All rights reserved. 12 * Copyright (c) 2014 Andrew Turner 13 * All rights reserved. 14 * Copyright (c) 2014-2016 The FreeBSD Foundation 15 * All rights reserved. 16 * 17 * This code is derived from software contributed to Berkeley by 18 * the Systems Programming Group of the University of Utah Computer 19 * Science Department and William Jolitz of UUNET Technologies Inc. 20 * 21 * This software was developed by Andrew Turner under sponsorship from 22 * the FreeBSD Foundation. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by the University of 35 * California, Berkeley and its contributors. 36 * 4. Neither the name of the University nor the names of its contributors 37 * may be used to endorse or promote products derived from this software 38 * without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 * 52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 53 */ 54/*- 55 * Copyright (c) 2003 Networks Associates Technology, Inc. 56 * All rights reserved. 57 * 58 * This software was developed for the FreeBSD Project by Jake Burkholder, 59 * Safeport Network Services, and Network Associates Laboratories, the 60 * Security Research Division of Network Associates, Inc. under 61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 62 * CHATS research program. 63 * 64 * Redistribution and use in source and binary forms, with or without 65 * modification, are permitted provided that the following conditions 66 * are met: 67 * 1. Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * 2. Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in the 71 * documentation and/or other materials provided with the distribution. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 83 * SUCH DAMAGE. 84 */ 85 86#include <sys/cdefs.h> 87__FBSDID("$FreeBSD: stable/11/sys/arm64/arm64/pmap.c 324400 2017-10-07 21:13:54Z alc $"); 88 89/* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is 93 * also stored by the logical address mapping module, 94 * this module may throw away valid virtual-to-physical 95 * mappings at almost any time. However, invalidations 96 * of virtual-to-physical mappings must be done as 97 * requested. 98 * 99 * In order to cope with hardware architectures which 100 * make virtual-to-physical map invalidates expensive, 101 * this module may delay invalidate or reduced protection 102 * operations until such time as they are actually 103 * necessary. This module is given full information as 104 * to which processors are currently using which maps, 105 * and to when physical maps must be made correct. 106 */ 107 108#include <sys/param.h> 109#include <sys/bitstring.h> 110#include <sys/bus.h> 111#include <sys/systm.h> 112#include <sys/kernel.h> 113#include <sys/ktr.h> 114#include <sys/lock.h> 115#include <sys/malloc.h> 116#include <sys/mman.h> 117#include <sys/msgbuf.h> 118#include <sys/mutex.h> 119#include <sys/proc.h> 120#include <sys/rwlock.h> 121#include <sys/sx.h> 122#include <sys/vmem.h> 123#include <sys/vmmeter.h> 124#include <sys/sched.h> 125#include <sys/sysctl.h> 126#include <sys/_unrhdr.h> 127#include <sys/smp.h> 128 129#include <vm/vm.h> 130#include <vm/vm_param.h> 131#include <vm/vm_kern.h> 132#include <vm/vm_page.h> 133#include <vm/vm_map.h> 134#include <vm/vm_object.h> 135#include <vm/vm_extern.h> 136#include <vm/vm_pageout.h> 137#include <vm/vm_pager.h> 138#include <vm/vm_phys.h> 139#include <vm/vm_radix.h> 140#include <vm/vm_reserv.h> 141#include <vm/uma.h> 142 143#include <machine/machdep.h> 144#include <machine/md_var.h> 145#include <machine/pcb.h> 146 147#define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t))) 148#define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t))) 149#define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t))) 150#define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t))) 151 152#define NUL0E L0_ENTRIES 153#define NUL1E (NUL0E * NL1PG) 154#define NUL2E (NUL1E * NL2PG) 155 156#if !defined(DIAGNOSTIC) 157#ifdef __GNUC_GNU_INLINE__ 158#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 159#else 160#define PMAP_INLINE extern inline 161#endif 162#else 163#define PMAP_INLINE 164#endif 165 166/* 167 * These are configured by the mair_el1 register. This is set up in locore.S 168 */ 169#define DEVICE_MEMORY 0 170#define UNCACHED_MEMORY 1 171#define CACHED_MEMORY 2 172 173 174#ifdef PV_STATS 175#define PV_STAT(x) do { x ; } while (0) 176#else 177#define PV_STAT(x) do { } while (0) 178#endif 179 180#define pmap_l2_pindex(v) ((v) >> L2_SHIFT) 181#define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)]) 182 183#define NPV_LIST_LOCKS MAXCPU 184 185#define PHYS_TO_PV_LIST_LOCK(pa) \ 186 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS]) 187 188#define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \ 189 struct rwlock **_lockp = (lockp); \ 190 struct rwlock *_new_lock; \ 191 \ 192 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \ 193 if (_new_lock != *_lockp) { \ 194 if (*_lockp != NULL) \ 195 rw_wunlock(*_lockp); \ 196 *_lockp = _new_lock; \ 197 rw_wlock(*_lockp); \ 198 } \ 199} while (0) 200 201#define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \ 202 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m)) 203 204#define RELEASE_PV_LIST_LOCK(lockp) do { \ 205 struct rwlock **_lockp = (lockp); \ 206 \ 207 if (*_lockp != NULL) { \ 208 rw_wunlock(*_lockp); \ 209 *_lockp = NULL; \ 210 } \ 211} while (0) 212 213#define VM_PAGE_TO_PV_LIST_LOCK(m) \ 214 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m)) 215 216struct pmap kernel_pmap_store; 217 218vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 219vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 220vm_offset_t kernel_vm_end = 0; 221 222struct msgbuf *msgbufp = NULL; 223 224/* 225 * Data for the pv entry allocation mechanism. 226 * Updates to pv_invl_gen are protected by the pv_list_locks[] 227 * elements, but reads are not. 228 */ 229static struct md_page *pv_table; 230static struct md_page pv_dummy; 231 232vm_paddr_t dmap_phys_base; /* The start of the dmap region */ 233vm_paddr_t dmap_phys_max; /* The limit of the dmap region */ 234vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */ 235 236/* This code assumes all L1 DMAP entries will be used */ 237CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS); 238CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS); 239 240#define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT) 241extern pt_entry_t pagetable_dmap[]; 242 243static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 244 245static int superpages_enabled = 0; 246SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled, 247 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0, 248 "Are large page mappings enabled?"); 249 250/* 251 * Data for the pv entry allocation mechanism 252 */ 253static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 254static struct mtx pv_chunks_mutex; 255static struct rwlock pv_list_locks[NPV_LIST_LOCKS]; 256 257static void free_pv_chunk(struct pv_chunk *pc); 258static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 259static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp); 260static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp); 261static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 262static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 263 vm_offset_t va); 264 265static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode); 266static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode); 267static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va); 268static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, 269 vm_offset_t va, struct rwlock **lockp); 270static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va); 271static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 272 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp); 273static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva, 274 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp); 275static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 276 vm_page_t m, struct rwlock **lockp); 277 278static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, 279 struct rwlock **lockp); 280 281static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, 282 struct spglist *free); 283static int pmap_unuse_l3(pmap_t, vm_offset_t, pd_entry_t, struct spglist *); 284 285/* 286 * These load the old table data and store the new value. 287 * They need to be atomic as the System MMU may write to the table at 288 * the same time as the CPU. 289 */ 290#define pmap_load_store(table, entry) atomic_swap_64(table, entry) 291#define pmap_set(table, mask) atomic_set_64(table, mask) 292#define pmap_load_clear(table) atomic_swap_64(table, 0) 293#define pmap_load(table) (*table) 294 295/********************/ 296/* Inline functions */ 297/********************/ 298 299static __inline void 300pagecopy(void *s, void *d) 301{ 302 303 memcpy(d, s, PAGE_SIZE); 304} 305 306#define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK) 307#define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK) 308#define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK) 309#define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK) 310 311static __inline pd_entry_t * 312pmap_l0(pmap_t pmap, vm_offset_t va) 313{ 314 315 return (&pmap->pm_l0[pmap_l0_index(va)]); 316} 317 318static __inline pd_entry_t * 319pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va) 320{ 321 pd_entry_t *l1; 322 323 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK); 324 return (&l1[pmap_l1_index(va)]); 325} 326 327static __inline pd_entry_t * 328pmap_l1(pmap_t pmap, vm_offset_t va) 329{ 330 pd_entry_t *l0; 331 332 l0 = pmap_l0(pmap, va); 333 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE) 334 return (NULL); 335 336 return (pmap_l0_to_l1(l0, va)); 337} 338 339static __inline pd_entry_t * 340pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va) 341{ 342 pd_entry_t *l2; 343 344 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK); 345 return (&l2[pmap_l2_index(va)]); 346} 347 348static __inline pd_entry_t * 349pmap_l2(pmap_t pmap, vm_offset_t va) 350{ 351 pd_entry_t *l1; 352 353 l1 = pmap_l1(pmap, va); 354 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE) 355 return (NULL); 356 357 return (pmap_l1_to_l2(l1, va)); 358} 359 360static __inline pt_entry_t * 361pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va) 362{ 363 pt_entry_t *l3; 364 365 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK); 366 return (&l3[pmap_l3_index(va)]); 367} 368 369/* 370 * Returns the lowest valid pde for a given virtual address. 371 * The next level may or may not point to a valid page or block. 372 */ 373static __inline pd_entry_t * 374pmap_pde(pmap_t pmap, vm_offset_t va, int *level) 375{ 376 pd_entry_t *l0, *l1, *l2, desc; 377 378 l0 = pmap_l0(pmap, va); 379 desc = pmap_load(l0) & ATTR_DESCR_MASK; 380 if (desc != L0_TABLE) { 381 *level = -1; 382 return (NULL); 383 } 384 385 l1 = pmap_l0_to_l1(l0, va); 386 desc = pmap_load(l1) & ATTR_DESCR_MASK; 387 if (desc != L1_TABLE) { 388 *level = 0; 389 return (l0); 390 } 391 392 l2 = pmap_l1_to_l2(l1, va); 393 desc = pmap_load(l2) & ATTR_DESCR_MASK; 394 if (desc != L2_TABLE) { 395 *level = 1; 396 return (l1); 397 } 398 399 *level = 2; 400 return (l2); 401} 402 403/* 404 * Returns the lowest valid pte block or table entry for a given virtual 405 * address. If there are no valid entries return NULL and set the level to 406 * the first invalid level. 407 */ 408static __inline pt_entry_t * 409pmap_pte(pmap_t pmap, vm_offset_t va, int *level) 410{ 411 pd_entry_t *l1, *l2, desc; 412 pt_entry_t *l3; 413 414 l1 = pmap_l1(pmap, va); 415 if (l1 == NULL) { 416 *level = 0; 417 return (NULL); 418 } 419 desc = pmap_load(l1) & ATTR_DESCR_MASK; 420 if (desc == L1_BLOCK) { 421 *level = 1; 422 return (l1); 423 } 424 425 if (desc != L1_TABLE) { 426 *level = 1; 427 return (NULL); 428 } 429 430 l2 = pmap_l1_to_l2(l1, va); 431 desc = pmap_load(l2) & ATTR_DESCR_MASK; 432 if (desc == L2_BLOCK) { 433 *level = 2; 434 return (l2); 435 } 436 437 if (desc != L2_TABLE) { 438 *level = 2; 439 return (NULL); 440 } 441 442 *level = 3; 443 l3 = pmap_l2_to_l3(l2, va); 444 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE) 445 return (NULL); 446 447 return (l3); 448} 449 450static inline bool 451pmap_superpages_enabled(void) 452{ 453 454 return (superpages_enabled != 0); 455} 456 457bool 458pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1, 459 pd_entry_t **l2, pt_entry_t **l3) 460{ 461 pd_entry_t *l0p, *l1p, *l2p; 462 463 if (pmap->pm_l0 == NULL) 464 return (false); 465 466 l0p = pmap_l0(pmap, va); 467 *l0 = l0p; 468 469 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE) 470 return (false); 471 472 l1p = pmap_l0_to_l1(l0p, va); 473 *l1 = l1p; 474 475 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) { 476 *l2 = NULL; 477 *l3 = NULL; 478 return (true); 479 } 480 481 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE) 482 return (false); 483 484 l2p = pmap_l1_to_l2(l1p, va); 485 *l2 = l2p; 486 487 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) { 488 *l3 = NULL; 489 return (true); 490 } 491 492 *l3 = pmap_l2_to_l3(l2p, va); 493 494 return (true); 495} 496 497static __inline int 498pmap_is_current(pmap_t pmap) 499{ 500 501 return ((pmap == pmap_kernel()) || 502 (pmap == curthread->td_proc->p_vmspace->vm_map.pmap)); 503} 504 505static __inline int 506pmap_l3_valid(pt_entry_t l3) 507{ 508 509 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE); 510} 511 512 513/* Is a level 1 or 2entry a valid block and cacheable */ 514CTASSERT(L1_BLOCK == L2_BLOCK); 515static __inline int 516pmap_pte_valid_cacheable(pt_entry_t pte) 517{ 518 519 return (((pte & ATTR_DESCR_MASK) == L1_BLOCK) && 520 ((pte & ATTR_IDX_MASK) == ATTR_IDX(CACHED_MEMORY))); 521} 522 523static __inline int 524pmap_l3_valid_cacheable(pt_entry_t l3) 525{ 526 527 return (((l3 & ATTR_DESCR_MASK) == L3_PAGE) && 528 ((l3 & ATTR_IDX_MASK) == ATTR_IDX(CACHED_MEMORY))); 529} 530 531#define PTE_SYNC(pte) cpu_dcache_wb_range((vm_offset_t)pte, sizeof(*pte)) 532 533/* 534 * Checks if the page is dirty. We currently lack proper tracking of this on 535 * arm64 so for now assume is a page mapped as rw was accessed it is. 536 */ 537static inline int 538pmap_page_dirty(pt_entry_t pte) 539{ 540 541 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) == 542 (ATTR_AF | ATTR_AP(ATTR_AP_RW))); 543} 544 545static __inline void 546pmap_resident_count_inc(pmap_t pmap, int count) 547{ 548 549 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 550 pmap->pm_stats.resident_count += count; 551} 552 553static __inline void 554pmap_resident_count_dec(pmap_t pmap, int count) 555{ 556 557 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 558 KASSERT(pmap->pm_stats.resident_count >= count, 559 ("pmap %p resident count underflow %ld %d", pmap, 560 pmap->pm_stats.resident_count, count)); 561 pmap->pm_stats.resident_count -= count; 562} 563 564static pt_entry_t * 565pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot, 566 u_int *l2_slot) 567{ 568 pt_entry_t *l2; 569 pd_entry_t *l1; 570 571 l1 = (pd_entry_t *)l1pt; 572 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK; 573 574 /* Check locore has used a table L1 map */ 575 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE, 576 ("Invalid bootstrap L1 table")); 577 /* Find the address of the L2 table */ 578 l2 = (pt_entry_t *)init_pt_va; 579 *l2_slot = pmap_l2_index(va); 580 581 return (l2); 582} 583 584static vm_paddr_t 585pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va) 586{ 587 u_int l1_slot, l2_slot; 588 pt_entry_t *l2; 589 590 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot); 591 592 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET)); 593} 594 595static void 596pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa) 597{ 598 vm_offset_t va; 599 vm_paddr_t pa; 600 u_int l1_slot; 601 602 pa = dmap_phys_base = min_pa & ~L1_OFFSET; 603 va = DMAP_MIN_ADDRESS; 604 for (; va < DMAP_MAX_ADDRESS && pa < max_pa; 605 pa += L1_SIZE, va += L1_SIZE, l1_slot++) { 606 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT); 607 608 pmap_load_store(&pagetable_dmap[l1_slot], 609 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN | 610 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK); 611 } 612 613 /* Set the upper limit of the DMAP region */ 614 dmap_phys_max = pa; 615 dmap_max_addr = va; 616 617 cpu_dcache_wb_range((vm_offset_t)pagetable_dmap, 618 PAGE_SIZE * DMAP_TABLES); 619 cpu_tlb_flushID(); 620} 621 622static vm_offset_t 623pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start) 624{ 625 vm_offset_t l2pt; 626 vm_paddr_t pa; 627 pd_entry_t *l1; 628 u_int l1_slot; 629 630 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address")); 631 632 l1 = (pd_entry_t *)l1pt; 633 l1_slot = pmap_l1_index(va); 634 l2pt = l2_start; 635 636 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) { 637 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index")); 638 639 pa = pmap_early_vtophys(l1pt, l2pt); 640 pmap_load_store(&l1[l1_slot], 641 (pa & ~Ln_TABLE_MASK) | L1_TABLE); 642 l2pt += PAGE_SIZE; 643 } 644 645 /* Clean the L2 page table */ 646 memset((void *)l2_start, 0, l2pt - l2_start); 647 cpu_dcache_wb_range(l2_start, l2pt - l2_start); 648 649 /* Flush the l1 table to ram */ 650 cpu_dcache_wb_range((vm_offset_t)l1, PAGE_SIZE); 651 652 return l2pt; 653} 654 655static vm_offset_t 656pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start) 657{ 658 vm_offset_t l2pt, l3pt; 659 vm_paddr_t pa; 660 pd_entry_t *l2; 661 u_int l2_slot; 662 663 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address")); 664 665 l2 = pmap_l2(kernel_pmap, va); 666 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE); 667 l2pt = (vm_offset_t)l2; 668 l2_slot = pmap_l2_index(va); 669 l3pt = l3_start; 670 671 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) { 672 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index")); 673 674 pa = pmap_early_vtophys(l1pt, l3pt); 675 pmap_load_store(&l2[l2_slot], 676 (pa & ~Ln_TABLE_MASK) | L2_TABLE); 677 l3pt += PAGE_SIZE; 678 } 679 680 /* Clean the L2 page table */ 681 memset((void *)l3_start, 0, l3pt - l3_start); 682 cpu_dcache_wb_range(l3_start, l3pt - l3_start); 683 684 cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE); 685 686 return l3pt; 687} 688 689/* 690 * Bootstrap the system enough to run with virtual memory. 691 */ 692void 693pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart, 694 vm_size_t kernlen) 695{ 696 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot; 697 uint64_t kern_delta; 698 pt_entry_t *l2; 699 vm_offset_t va, freemempos; 700 vm_offset_t dpcpu, msgbufpv; 701 vm_paddr_t pa, max_pa, min_pa; 702 int i; 703 704 kern_delta = KERNBASE - kernstart; 705 physmem = 0; 706 707 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen); 708 printf("%lx\n", l1pt); 709 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK); 710 711 /* Set this early so we can use the pagetable walking functions */ 712 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt; 713 PMAP_LOCK_INIT(kernel_pmap); 714 715 /* Assume the address we were loaded to is a valid physical address */ 716 min_pa = max_pa = KERNBASE - kern_delta; 717 718 /* 719 * Find the minimum physical address. physmap is sorted, 720 * but may contain empty ranges. 721 */ 722 for (i = 0; i < (physmap_idx * 2); i += 2) { 723 if (physmap[i] == physmap[i + 1]) 724 continue; 725 if (physmap[i] <= min_pa) 726 min_pa = physmap[i]; 727 if (physmap[i + 1] > max_pa) 728 max_pa = physmap[i + 1]; 729 } 730 731 /* Create a direct map region early so we can use it for pa -> va */ 732 pmap_bootstrap_dmap(l1pt, min_pa, max_pa); 733 734 va = KERNBASE; 735 pa = KERNBASE - kern_delta; 736 737 /* 738 * Start to initialise phys_avail by copying from physmap 739 * up to the physical address KERNBASE points at. 740 */ 741 map_slot = avail_slot = 0; 742 for (; map_slot < (physmap_idx * 2) && 743 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) { 744 if (physmap[map_slot] == physmap[map_slot + 1]) 745 continue; 746 747 if (physmap[map_slot] <= pa && 748 physmap[map_slot + 1] > pa) 749 break; 750 751 phys_avail[avail_slot] = physmap[map_slot]; 752 phys_avail[avail_slot + 1] = physmap[map_slot + 1]; 753 physmem += (phys_avail[avail_slot + 1] - 754 phys_avail[avail_slot]) >> PAGE_SHIFT; 755 avail_slot += 2; 756 } 757 758 /* Add the memory before the kernel */ 759 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) { 760 phys_avail[avail_slot] = physmap[map_slot]; 761 phys_avail[avail_slot + 1] = pa; 762 physmem += (phys_avail[avail_slot + 1] - 763 phys_avail[avail_slot]) >> PAGE_SHIFT; 764 avail_slot += 2; 765 } 766 used_map_slot = map_slot; 767 768 /* 769 * Read the page table to find out what is already mapped. 770 * This assumes we have mapped a block of memory from KERNBASE 771 * using a single L1 entry. 772 */ 773 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot); 774 775 /* Sanity check the index, KERNBASE should be the first VA */ 776 KASSERT(l2_slot == 0, ("The L2 index is non-zero")); 777 778 /* Find how many pages we have mapped */ 779 for (; l2_slot < Ln_ENTRIES; l2_slot++) { 780 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0) 781 break; 782 783 /* Check locore used L2 blocks */ 784 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK, 785 ("Invalid bootstrap L2 table")); 786 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa, 787 ("Incorrect PA in L2 table")); 788 789 va += L2_SIZE; 790 pa += L2_SIZE; 791 } 792 793 va = roundup2(va, L1_SIZE); 794 795 freemempos = KERNBASE + kernlen; 796 freemempos = roundup2(freemempos, PAGE_SIZE); 797 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */ 798 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos); 799 /* And the l3 tables for the early devmap */ 800 freemempos = pmap_bootstrap_l3(l1pt, 801 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos); 802 803 cpu_tlb_flushID(); 804 805#define alloc_pages(var, np) \ 806 (var) = freemempos; \ 807 freemempos += (np * PAGE_SIZE); \ 808 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 809 810 /* Allocate dynamic per-cpu area. */ 811 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 812 dpcpu_init((void *)dpcpu, 0); 813 814 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */ 815 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 816 msgbufp = (void *)msgbufpv; 817 818 virtual_avail = roundup2(freemempos, L1_SIZE); 819 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE; 820 kernel_vm_end = virtual_avail; 821 822 pa = pmap_early_vtophys(l1pt, freemempos); 823 824 /* Finish initialising physmap */ 825 map_slot = used_map_slot; 826 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) && 827 map_slot < (physmap_idx * 2); map_slot += 2) { 828 if (physmap[map_slot] == physmap[map_slot + 1]) 829 continue; 830 831 /* Have we used the current range? */ 832 if (physmap[map_slot + 1] <= pa) 833 continue; 834 835 /* Do we need to split the entry? */ 836 if (physmap[map_slot] < pa) { 837 phys_avail[avail_slot] = pa; 838 phys_avail[avail_slot + 1] = physmap[map_slot + 1]; 839 } else { 840 phys_avail[avail_slot] = physmap[map_slot]; 841 phys_avail[avail_slot + 1] = physmap[map_slot + 1]; 842 } 843 physmem += (phys_avail[avail_slot + 1] - 844 phys_avail[avail_slot]) >> PAGE_SHIFT; 845 846 avail_slot += 2; 847 } 848 phys_avail[avail_slot] = 0; 849 phys_avail[avail_slot + 1] = 0; 850 851 /* 852 * Maxmem isn't the "maximum memory", it's one larger than the 853 * highest page of the physical address space. It should be 854 * called something like "Maxphyspage". 855 */ 856 Maxmem = atop(phys_avail[avail_slot - 1]); 857 858 cpu_tlb_flushID(); 859} 860 861/* 862 * Initialize a vm_page's machine-dependent fields. 863 */ 864void 865pmap_page_init(vm_page_t m) 866{ 867 868 TAILQ_INIT(&m->md.pv_list); 869 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK; 870} 871 872/* 873 * Initialize the pmap module. 874 * Called by vm_init, to initialize any structures that the pmap 875 * system needs to map virtual memory. 876 */ 877void 878pmap_init(void) 879{ 880 vm_size_t s; 881 int i, pv_npg; 882 883 /* 884 * Are large page mappings enabled? 885 */ 886 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled); 887 888 /* 889 * Initialize the pv chunk list mutex. 890 */ 891 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF); 892 893 /* 894 * Initialize the pool of pv list locks. 895 */ 896 for (i = 0; i < NPV_LIST_LOCKS; i++) 897 rw_init(&pv_list_locks[i], "pmap pv list"); 898 899 /* 900 * Calculate the size of the pv head table for superpages. 901 */ 902 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE); 903 904 /* 905 * Allocate memory for the pv head table for superpages. 906 */ 907 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 908 s = round_page(s); 909 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s, 910 M_WAITOK | M_ZERO); 911 for (i = 0; i < pv_npg; i++) 912 TAILQ_INIT(&pv_table[i].pv_list); 913 TAILQ_INIT(&pv_dummy.pv_list); 914} 915 916static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0, 917 "2MB page mapping counters"); 918 919static u_long pmap_l2_demotions; 920SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD, 921 &pmap_l2_demotions, 0, "2MB page demotions"); 922 923static u_long pmap_l2_p_failures; 924SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD, 925 &pmap_l2_p_failures, 0, "2MB page promotion failures"); 926 927static u_long pmap_l2_promotions; 928SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD, 929 &pmap_l2_promotions, 0, "2MB page promotions"); 930 931/* 932 * Invalidate a single TLB entry. 933 */ 934PMAP_INLINE void 935pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 936{ 937 938 sched_pin(); 939 __asm __volatile( 940 "dsb ishst \n" 941 "tlbi vaae1is, %0 \n" 942 "dsb ish \n" 943 "isb \n" 944 : : "r"(va >> PAGE_SHIFT)); 945 sched_unpin(); 946} 947 948PMAP_INLINE void 949pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 950{ 951 vm_offset_t addr; 952 953 sched_pin(); 954 dsb(ishst); 955 for (addr = sva; addr < eva; addr += PAGE_SIZE) { 956 __asm __volatile( 957 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT)); 958 } 959 __asm __volatile( 960 "dsb ish \n" 961 "isb \n"); 962 sched_unpin(); 963} 964 965PMAP_INLINE void 966pmap_invalidate_all(pmap_t pmap) 967{ 968 969 sched_pin(); 970 __asm __volatile( 971 "dsb ishst \n" 972 "tlbi vmalle1is \n" 973 "dsb ish \n" 974 "isb \n"); 975 sched_unpin(); 976} 977 978/* 979 * Routine: pmap_extract 980 * Function: 981 * Extract the physical page address associated 982 * with the given map/virtual_address pair. 983 */ 984vm_paddr_t 985pmap_extract(pmap_t pmap, vm_offset_t va) 986{ 987 pt_entry_t *pte, tpte; 988 vm_paddr_t pa; 989 int lvl; 990 991 pa = 0; 992 PMAP_LOCK(pmap); 993 /* 994 * Find the block or page map for this virtual address. pmap_pte 995 * will return either a valid block/page entry, or NULL. 996 */ 997 pte = pmap_pte(pmap, va, &lvl); 998 if (pte != NULL) { 999 tpte = pmap_load(pte); 1000 pa = tpte & ~ATTR_MASK; 1001 switch(lvl) { 1002 case 1: 1003 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK, 1004 ("pmap_extract: Invalid L1 pte found: %lx", 1005 tpte & ATTR_DESCR_MASK)); 1006 pa |= (va & L1_OFFSET); 1007 break; 1008 case 2: 1009 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK, 1010 ("pmap_extract: Invalid L2 pte found: %lx", 1011 tpte & ATTR_DESCR_MASK)); 1012 pa |= (va & L2_OFFSET); 1013 break; 1014 case 3: 1015 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE, 1016 ("pmap_extract: Invalid L3 pte found: %lx", 1017 tpte & ATTR_DESCR_MASK)); 1018 pa |= (va & L3_OFFSET); 1019 break; 1020 } 1021 } 1022 PMAP_UNLOCK(pmap); 1023 return (pa); 1024} 1025 1026/* 1027 * Routine: pmap_extract_and_hold 1028 * Function: 1029 * Atomically extract and hold the physical page 1030 * with the given pmap and virtual address pair 1031 * if that mapping permits the given protection. 1032 */ 1033vm_page_t 1034pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1035{ 1036 pt_entry_t *pte, tpte; 1037 vm_offset_t off; 1038 vm_paddr_t pa; 1039 vm_page_t m; 1040 int lvl; 1041 1042 pa = 0; 1043 m = NULL; 1044 PMAP_LOCK(pmap); 1045retry: 1046 pte = pmap_pte(pmap, va, &lvl); 1047 if (pte != NULL) { 1048 tpte = pmap_load(pte); 1049 1050 KASSERT(lvl > 0 && lvl <= 3, 1051 ("pmap_extract_and_hold: Invalid level %d", lvl)); 1052 CTASSERT(L1_BLOCK == L2_BLOCK); 1053 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) || 1054 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK), 1055 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl, 1056 tpte & ATTR_DESCR_MASK)); 1057 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) || 1058 ((prot & VM_PROT_WRITE) == 0)) { 1059 switch(lvl) { 1060 case 1: 1061 off = va & L1_OFFSET; 1062 break; 1063 case 2: 1064 off = va & L2_OFFSET; 1065 break; 1066 case 3: 1067 default: 1068 off = 0; 1069 } 1070 if (vm_page_pa_tryrelock(pmap, 1071 (tpte & ~ATTR_MASK) | off, &pa)) 1072 goto retry; 1073 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off); 1074 vm_page_hold(m); 1075 } 1076 } 1077 PA_UNLOCK_COND(pa); 1078 PMAP_UNLOCK(pmap); 1079 return (m); 1080} 1081 1082vm_paddr_t 1083pmap_kextract(vm_offset_t va) 1084{ 1085 pt_entry_t *pte, tpte; 1086 vm_paddr_t pa; 1087 int lvl; 1088 1089 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) { 1090 pa = DMAP_TO_PHYS(va); 1091 } else { 1092 pa = 0; 1093 pte = pmap_pte(kernel_pmap, va, &lvl); 1094 if (pte != NULL) { 1095 tpte = pmap_load(pte); 1096 pa = tpte & ~ATTR_MASK; 1097 switch(lvl) { 1098 case 1: 1099 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK, 1100 ("pmap_kextract: Invalid L1 pte found: %lx", 1101 tpte & ATTR_DESCR_MASK)); 1102 pa |= (va & L1_OFFSET); 1103 break; 1104 case 2: 1105 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK, 1106 ("pmap_kextract: Invalid L2 pte found: %lx", 1107 tpte & ATTR_DESCR_MASK)); 1108 pa |= (va & L2_OFFSET); 1109 break; 1110 case 3: 1111 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE, 1112 ("pmap_kextract: Invalid L3 pte found: %lx", 1113 tpte & ATTR_DESCR_MASK)); 1114 pa |= (va & L3_OFFSET); 1115 break; 1116 } 1117 } 1118 } 1119 return (pa); 1120} 1121 1122/*************************************************** 1123 * Low level mapping routines..... 1124 ***************************************************/ 1125 1126static void 1127pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode) 1128{ 1129 pd_entry_t *pde; 1130 pt_entry_t *pte, attr; 1131 vm_offset_t va; 1132 int lvl; 1133 1134 KASSERT((pa & L3_OFFSET) == 0, 1135 ("pmap_kenter: Invalid physical address")); 1136 KASSERT((sva & L3_OFFSET) == 0, 1137 ("pmap_kenter: Invalid virtual address")); 1138 KASSERT((size & PAGE_MASK) == 0, 1139 ("pmap_kenter: Mapping is not page-sized")); 1140 1141 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE; 1142 if (mode == DEVICE_MEMORY) 1143 attr |= ATTR_XN; 1144 1145 va = sva; 1146 while (size != 0) { 1147 pde = pmap_pde(kernel_pmap, va, &lvl); 1148 KASSERT(pde != NULL, 1149 ("pmap_kenter: Invalid page entry, va: 0x%lx", va)); 1150 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl)); 1151 1152 pte = pmap_l2_to_l3(pde, va); 1153 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr); 1154 PTE_SYNC(pte); 1155 1156 va += PAGE_SIZE; 1157 pa += PAGE_SIZE; 1158 size -= PAGE_SIZE; 1159 } 1160 pmap_invalidate_range(kernel_pmap, sva, va); 1161} 1162 1163void 1164pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa) 1165{ 1166 1167 pmap_kenter(sva, size, pa, DEVICE_MEMORY); 1168} 1169 1170/* 1171 * Remove a page from the kernel pagetables. 1172 */ 1173PMAP_INLINE void 1174pmap_kremove(vm_offset_t va) 1175{ 1176 pt_entry_t *pte; 1177 int lvl; 1178 1179 pte = pmap_pte(kernel_pmap, va, &lvl); 1180 KASSERT(pte != NULL, ("pmap_kremove: Invalid address")); 1181 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl)); 1182 1183 if (pmap_l3_valid_cacheable(pmap_load(pte))) 1184 cpu_dcache_wb_range(va, L3_SIZE); 1185 pmap_load_clear(pte); 1186 PTE_SYNC(pte); 1187 pmap_invalidate_page(kernel_pmap, va); 1188} 1189 1190void 1191pmap_kremove_device(vm_offset_t sva, vm_size_t size) 1192{ 1193 pt_entry_t *pte; 1194 vm_offset_t va; 1195 int lvl; 1196 1197 KASSERT((sva & L3_OFFSET) == 0, 1198 ("pmap_kremove_device: Invalid virtual address")); 1199 KASSERT((size & PAGE_MASK) == 0, 1200 ("pmap_kremove_device: Mapping is not page-sized")); 1201 1202 va = sva; 1203 while (size != 0) { 1204 pte = pmap_pte(kernel_pmap, va, &lvl); 1205 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va)); 1206 KASSERT(lvl == 3, 1207 ("Invalid device pagetable level: %d != 3", lvl)); 1208 pmap_load_clear(pte); 1209 PTE_SYNC(pte); 1210 1211 va += PAGE_SIZE; 1212 size -= PAGE_SIZE; 1213 } 1214 pmap_invalidate_range(kernel_pmap, sva, va); 1215} 1216 1217/* 1218 * Used to map a range of physical addresses into kernel 1219 * virtual address space. 1220 * 1221 * The value passed in '*virt' is a suggested virtual address for 1222 * the mapping. Architectures which can support a direct-mapped 1223 * physical to virtual region can return the appropriate address 1224 * within that region, leaving '*virt' unchanged. Other 1225 * architectures should map the pages starting at '*virt' and 1226 * update '*virt' with the first usable address after the mapped 1227 * region. 1228 */ 1229vm_offset_t 1230pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1231{ 1232 return PHYS_TO_DMAP(start); 1233} 1234 1235 1236/* 1237 * Add a list of wired pages to the kva 1238 * this routine is only used for temporary 1239 * kernel mappings that do not need to have 1240 * page modification or references recorded. 1241 * Note that old mappings are simply written 1242 * over. The page *must* be wired. 1243 * Note: SMP coherent. Uses a ranged shootdown IPI. 1244 */ 1245void 1246pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1247{ 1248 pd_entry_t *pde; 1249 pt_entry_t *pte, pa; 1250 vm_offset_t va; 1251 vm_page_t m; 1252 int i, lvl; 1253 1254 va = sva; 1255 for (i = 0; i < count; i++) { 1256 pde = pmap_pde(kernel_pmap, va, &lvl); 1257 KASSERT(pde != NULL, 1258 ("pmap_qenter: Invalid page entry, va: 0x%lx", va)); 1259 KASSERT(lvl == 2, 1260 ("pmap_qenter: Invalid level %d", lvl)); 1261 1262 m = ma[i]; 1263 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) | 1264 ATTR_IDX(m->md.pv_memattr) | L3_PAGE; 1265 if (m->md.pv_memattr == DEVICE_MEMORY) 1266 pa |= ATTR_XN; 1267 pte = pmap_l2_to_l3(pde, va); 1268 pmap_load_store(pte, pa); 1269 PTE_SYNC(pte); 1270 1271 va += L3_SIZE; 1272 } 1273 pmap_invalidate_range(kernel_pmap, sva, va); 1274} 1275 1276/* 1277 * This routine tears out page mappings from the 1278 * kernel -- it is meant only for temporary mappings. 1279 */ 1280void 1281pmap_qremove(vm_offset_t sva, int count) 1282{ 1283 pt_entry_t *pte; 1284 vm_offset_t va; 1285 int lvl; 1286 1287 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva)); 1288 1289 va = sva; 1290 while (count-- > 0) { 1291 pte = pmap_pte(kernel_pmap, va, &lvl); 1292 KASSERT(lvl == 3, 1293 ("Invalid device pagetable level: %d != 3", lvl)); 1294 if (pte != NULL) { 1295 if (pmap_l3_valid_cacheable(pmap_load(pte))) 1296 cpu_dcache_wb_range(va, L3_SIZE); 1297 pmap_load_clear(pte); 1298 PTE_SYNC(pte); 1299 } 1300 1301 va += PAGE_SIZE; 1302 } 1303 pmap_invalidate_range(kernel_pmap, sva, va); 1304} 1305 1306/*************************************************** 1307 * Page table page management routines..... 1308 ***************************************************/ 1309static __inline void 1310pmap_free_zero_pages(struct spglist *free) 1311{ 1312 vm_page_t m; 1313 1314 while ((m = SLIST_FIRST(free)) != NULL) { 1315 SLIST_REMOVE_HEAD(free, plinks.s.ss); 1316 /* Preserve the page's PG_ZERO setting. */ 1317 vm_page_free_toq(m); 1318 } 1319} 1320 1321/* 1322 * Schedule the specified unused page table page to be freed. Specifically, 1323 * add the page to the specified list of pages that will be released to the 1324 * physical memory manager after the TLB has been updated. 1325 */ 1326static __inline void 1327pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, 1328 boolean_t set_PG_ZERO) 1329{ 1330 1331 if (set_PG_ZERO) 1332 m->flags |= PG_ZERO; 1333 else 1334 m->flags &= ~PG_ZERO; 1335 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 1336} 1337 1338/* 1339 * Decrements a page table page's wire count, which is used to record the 1340 * number of valid page table entries within the page. If the wire count 1341 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1342 * page table page was unmapped and FALSE otherwise. 1343 */ 1344static inline boolean_t 1345pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 1346{ 1347 1348 --m->wire_count; 1349 if (m->wire_count == 0) { 1350 _pmap_unwire_l3(pmap, va, m, free); 1351 return (TRUE); 1352 } else 1353 return (FALSE); 1354} 1355 1356static void 1357_pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 1358{ 1359 1360 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1361 /* 1362 * unmap the page table page 1363 */ 1364 if (m->pindex >= (NUL2E + NUL1E)) { 1365 /* l1 page */ 1366 pd_entry_t *l0; 1367 1368 l0 = pmap_l0(pmap, va); 1369 pmap_load_clear(l0); 1370 PTE_SYNC(l0); 1371 } else if (m->pindex >= NUL2E) { 1372 /* l2 page */ 1373 pd_entry_t *l1; 1374 1375 l1 = pmap_l1(pmap, va); 1376 pmap_load_clear(l1); 1377 PTE_SYNC(l1); 1378 } else { 1379 /* l3 page */ 1380 pd_entry_t *l2; 1381 1382 l2 = pmap_l2(pmap, va); 1383 pmap_load_clear(l2); 1384 PTE_SYNC(l2); 1385 } 1386 pmap_resident_count_dec(pmap, 1); 1387 if (m->pindex < NUL2E) { 1388 /* We just released an l3, unhold the matching l2 */ 1389 pd_entry_t *l1, tl1; 1390 vm_page_t l2pg; 1391 1392 l1 = pmap_l1(pmap, va); 1393 tl1 = pmap_load(l1); 1394 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK); 1395 pmap_unwire_l3(pmap, va, l2pg, free); 1396 } else if (m->pindex < (NUL2E + NUL1E)) { 1397 /* We just released an l2, unhold the matching l1 */ 1398 pd_entry_t *l0, tl0; 1399 vm_page_t l1pg; 1400 1401 l0 = pmap_l0(pmap, va); 1402 tl0 = pmap_load(l0); 1403 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK); 1404 pmap_unwire_l3(pmap, va, l1pg, free); 1405 } 1406 pmap_invalidate_page(pmap, va); 1407 1408 /* 1409 * This is a release store so that the ordinary store unmapping 1410 * the page table page is globally performed before TLB shoot- 1411 * down is begun. 1412 */ 1413 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1); 1414 1415 /* 1416 * Put page on a list so that it is released after 1417 * *ALL* TLB shootdown is done 1418 */ 1419 pmap_add_delayed_free_list(m, free, TRUE); 1420} 1421 1422/* 1423 * After removing an l3 entry, this routine is used to 1424 * conditionally free the page, and manage the hold/wire counts. 1425 */ 1426static int 1427pmap_unuse_l3(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, 1428 struct spglist *free) 1429{ 1430 vm_page_t mpte; 1431 1432 if (va >= VM_MAXUSER_ADDRESS) 1433 return (0); 1434 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0")); 1435 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK); 1436 return (pmap_unwire_l3(pmap, va, mpte, free)); 1437} 1438 1439void 1440pmap_pinit0(pmap_t pmap) 1441{ 1442 1443 PMAP_LOCK_INIT(pmap); 1444 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1445 pmap->pm_l0 = kernel_pmap->pm_l0; 1446 pmap->pm_root.rt_root = 0; 1447} 1448 1449int 1450pmap_pinit(pmap_t pmap) 1451{ 1452 vm_paddr_t l0phys; 1453 vm_page_t l0pt; 1454 1455 /* 1456 * allocate the l0 page 1457 */ 1458 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 1459 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) 1460 VM_WAIT; 1461 1462 l0phys = VM_PAGE_TO_PHYS(l0pt); 1463 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys); 1464 1465 if ((l0pt->flags & PG_ZERO) == 0) 1466 pagezero(pmap->pm_l0); 1467 1468 pmap->pm_root.rt_root = 0; 1469 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1470 1471 return (1); 1472} 1473 1474/* 1475 * This routine is called if the desired page table page does not exist. 1476 * 1477 * If page table page allocation fails, this routine may sleep before 1478 * returning NULL. It sleeps only if a lock pointer was given. 1479 * 1480 * Note: If a page allocation fails at page table level two or three, 1481 * one or two pages may be held during the wait, only to be released 1482 * afterwards. This conservative approach is easily argued to avoid 1483 * race conditions. 1484 */ 1485static vm_page_t 1486_pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp) 1487{ 1488 vm_page_t m, l1pg, l2pg; 1489 1490 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1491 1492 /* 1493 * Allocate a page table page. 1494 */ 1495 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1496 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1497 if (lockp != NULL) { 1498 RELEASE_PV_LIST_LOCK(lockp); 1499 PMAP_UNLOCK(pmap); 1500 VM_WAIT; 1501 PMAP_LOCK(pmap); 1502 } 1503 1504 /* 1505 * Indicate the need to retry. While waiting, the page table 1506 * page may have been allocated. 1507 */ 1508 return (NULL); 1509 } 1510 if ((m->flags & PG_ZERO) == 0) 1511 pmap_zero_page(m); 1512 1513 /* 1514 * Map the pagetable page into the process address space, if 1515 * it isn't already there. 1516 */ 1517 1518 if (ptepindex >= (NUL2E + NUL1E)) { 1519 pd_entry_t *l0; 1520 vm_pindex_t l0index; 1521 1522 l0index = ptepindex - (NUL2E + NUL1E); 1523 l0 = &pmap->pm_l0[l0index]; 1524 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE); 1525 PTE_SYNC(l0); 1526 } else if (ptepindex >= NUL2E) { 1527 vm_pindex_t l0index, l1index; 1528 pd_entry_t *l0, *l1; 1529 pd_entry_t tl0; 1530 1531 l1index = ptepindex - NUL2E; 1532 l0index = l1index >> L0_ENTRIES_SHIFT; 1533 1534 l0 = &pmap->pm_l0[l0index]; 1535 tl0 = pmap_load(l0); 1536 if (tl0 == 0) { 1537 /* recurse for allocating page dir */ 1538 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index, 1539 lockp) == NULL) { 1540 --m->wire_count; 1541 /* XXX: release mem barrier? */ 1542 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1543 vm_page_free_zero(m); 1544 return (NULL); 1545 } 1546 } else { 1547 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK); 1548 l1pg->wire_count++; 1549 } 1550 1551 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK); 1552 l1 = &l1[ptepindex & Ln_ADDR_MASK]; 1553 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE); 1554 PTE_SYNC(l1); 1555 } else { 1556 vm_pindex_t l0index, l1index; 1557 pd_entry_t *l0, *l1, *l2; 1558 pd_entry_t tl0, tl1; 1559 1560 l1index = ptepindex >> Ln_ENTRIES_SHIFT; 1561 l0index = l1index >> L0_ENTRIES_SHIFT; 1562 1563 l0 = &pmap->pm_l0[l0index]; 1564 tl0 = pmap_load(l0); 1565 if (tl0 == 0) { 1566 /* recurse for allocating page dir */ 1567 if (_pmap_alloc_l3(pmap, NUL2E + l1index, 1568 lockp) == NULL) { 1569 --m->wire_count; 1570 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1571 vm_page_free_zero(m); 1572 return (NULL); 1573 } 1574 tl0 = pmap_load(l0); 1575 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK); 1576 l1 = &l1[l1index & Ln_ADDR_MASK]; 1577 } else { 1578 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK); 1579 l1 = &l1[l1index & Ln_ADDR_MASK]; 1580 tl1 = pmap_load(l1); 1581 if (tl1 == 0) { 1582 /* recurse for allocating page dir */ 1583 if (_pmap_alloc_l3(pmap, NUL2E + l1index, 1584 lockp) == NULL) { 1585 --m->wire_count; 1586 /* XXX: release mem barrier? */ 1587 atomic_subtract_int( 1588 &vm_cnt.v_wire_count, 1); 1589 vm_page_free_zero(m); 1590 return (NULL); 1591 } 1592 } else { 1593 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK); 1594 l2pg->wire_count++; 1595 } 1596 } 1597 1598 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK); 1599 l2 = &l2[ptepindex & Ln_ADDR_MASK]; 1600 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE); 1601 PTE_SYNC(l2); 1602 } 1603 1604 pmap_resident_count_inc(pmap, 1); 1605 1606 return (m); 1607} 1608 1609static vm_page_t 1610pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp) 1611{ 1612 vm_pindex_t ptepindex; 1613 pd_entry_t *pde, tpde; 1614#ifdef INVARIANTS 1615 pt_entry_t *pte; 1616#endif 1617 vm_page_t m; 1618 int lvl; 1619 1620 /* 1621 * Calculate pagetable page index 1622 */ 1623 ptepindex = pmap_l2_pindex(va); 1624retry: 1625 /* 1626 * Get the page directory entry 1627 */ 1628 pde = pmap_pde(pmap, va, &lvl); 1629 1630 /* 1631 * If the page table page is mapped, we just increment the hold count, 1632 * and activate it. If we get a level 2 pde it will point to a level 3 1633 * table. 1634 */ 1635 switch (lvl) { 1636 case -1: 1637 break; 1638 case 0: 1639#ifdef INVARIANTS 1640 pte = pmap_l0_to_l1(pde, va); 1641 KASSERT(pmap_load(pte) == 0, 1642 ("pmap_alloc_l3: TODO: l0 superpages")); 1643#endif 1644 break; 1645 case 1: 1646#ifdef INVARIANTS 1647 pte = pmap_l1_to_l2(pde, va); 1648 KASSERT(pmap_load(pte) == 0, 1649 ("pmap_alloc_l3: TODO: l1 superpages")); 1650#endif 1651 break; 1652 case 2: 1653 tpde = pmap_load(pde); 1654 if (tpde != 0) { 1655 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK); 1656 m->wire_count++; 1657 return (m); 1658 } 1659 break; 1660 default: 1661 panic("pmap_alloc_l3: Invalid level %d", lvl); 1662 } 1663 1664 /* 1665 * Here if the pte page isn't mapped, or if it has been deallocated. 1666 */ 1667 m = _pmap_alloc_l3(pmap, ptepindex, lockp); 1668 if (m == NULL && lockp != NULL) 1669 goto retry; 1670 1671 return (m); 1672} 1673 1674 1675/*************************************************** 1676 * Pmap allocation/deallocation routines. 1677 ***************************************************/ 1678 1679/* 1680 * Release any resources held by the given physical map. 1681 * Called when a pmap initialized by pmap_pinit is being released. 1682 * Should only be called if the map contains no valid mappings. 1683 */ 1684void 1685pmap_release(pmap_t pmap) 1686{ 1687 vm_page_t m; 1688 1689 KASSERT(pmap->pm_stats.resident_count == 0, 1690 ("pmap_release: pmap resident count %ld != 0", 1691 pmap->pm_stats.resident_count)); 1692 KASSERT(vm_radix_is_empty(&pmap->pm_root), 1693 ("pmap_release: pmap has reserved page table page(s)")); 1694 1695 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0)); 1696 1697 m->wire_count--; 1698 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1699 vm_page_free_zero(m); 1700} 1701 1702static int 1703kvm_size(SYSCTL_HANDLER_ARGS) 1704{ 1705 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS; 1706 1707 return sysctl_handle_long(oidp, &ksize, 0, req); 1708} 1709SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1710 0, 0, kvm_size, "LU", "Size of KVM"); 1711 1712static int 1713kvm_free(SYSCTL_HANDLER_ARGS) 1714{ 1715 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1716 1717 return sysctl_handle_long(oidp, &kfree, 0, req); 1718} 1719SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1720 0, 0, kvm_free, "LU", "Amount of KVM free"); 1721 1722/* 1723 * grow the number of kernel page table entries, if needed 1724 */ 1725void 1726pmap_growkernel(vm_offset_t addr) 1727{ 1728 vm_paddr_t paddr; 1729 vm_page_t nkpg; 1730 pd_entry_t *l0, *l1, *l2; 1731 1732 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1733 1734 addr = roundup2(addr, L2_SIZE); 1735 if (addr - 1 >= kernel_map->max_offset) 1736 addr = kernel_map->max_offset; 1737 while (kernel_vm_end < addr) { 1738 l0 = pmap_l0(kernel_pmap, kernel_vm_end); 1739 KASSERT(pmap_load(l0) != 0, 1740 ("pmap_growkernel: No level 0 kernel entry")); 1741 1742 l1 = pmap_l0_to_l1(l0, kernel_vm_end); 1743 if (pmap_load(l1) == 0) { 1744 /* We need a new PDP entry */ 1745 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT, 1746 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1747 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1748 if (nkpg == NULL) 1749 panic("pmap_growkernel: no memory to grow kernel"); 1750 if ((nkpg->flags & PG_ZERO) == 0) 1751 pmap_zero_page(nkpg); 1752 paddr = VM_PAGE_TO_PHYS(nkpg); 1753 pmap_load_store(l1, paddr | L1_TABLE); 1754 PTE_SYNC(l1); 1755 continue; /* try again */ 1756 } 1757 l2 = pmap_l1_to_l2(l1, kernel_vm_end); 1758 if ((pmap_load(l2) & ATTR_AF) != 0) { 1759 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET; 1760 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1761 kernel_vm_end = kernel_map->max_offset; 1762 break; 1763 } 1764 continue; 1765 } 1766 1767 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT, 1768 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1769 VM_ALLOC_ZERO); 1770 if (nkpg == NULL) 1771 panic("pmap_growkernel: no memory to grow kernel"); 1772 if ((nkpg->flags & PG_ZERO) == 0) 1773 pmap_zero_page(nkpg); 1774 paddr = VM_PAGE_TO_PHYS(nkpg); 1775 pmap_load_store(l2, paddr | L2_TABLE); 1776 PTE_SYNC(l2); 1777 pmap_invalidate_page(kernel_pmap, kernel_vm_end); 1778 1779 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET; 1780 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1781 kernel_vm_end = kernel_map->max_offset; 1782 break; 1783 } 1784 } 1785} 1786 1787 1788/*************************************************** 1789 * page management routines. 1790 ***************************************************/ 1791 1792CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1793CTASSERT(_NPCM == 3); 1794CTASSERT(_NPCPV == 168); 1795 1796static __inline struct pv_chunk * 1797pv_to_chunk(pv_entry_t pv) 1798{ 1799 1800 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1801} 1802 1803#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1804 1805#define PC_FREE0 0xfffffffffffffffful 1806#define PC_FREE1 0xfffffffffffffffful 1807#define PC_FREE2 0x000000fffffffffful 1808 1809static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 }; 1810 1811#if 0 1812#ifdef PV_STATS 1813static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1814 1815SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1816 "Current number of pv entry chunks"); 1817SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1818 "Current number of pv entry chunks allocated"); 1819SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1820 "Current number of pv entry chunks frees"); 1821SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1822 "Number of times tried to get a chunk page but failed."); 1823 1824static long pv_entry_frees, pv_entry_allocs, pv_entry_count; 1825static int pv_entry_spare; 1826 1827SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1828 "Current number of pv entry frees"); 1829SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1830 "Current number of pv entry allocs"); 1831SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1832 "Current number of pv entries"); 1833SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1834 "Current number of spare pv entries"); 1835#endif 1836#endif /* 0 */ 1837 1838/* 1839 * We are in a serious low memory condition. Resort to 1840 * drastic measures to free some pages so we can allocate 1841 * another pv entry chunk. 1842 * 1843 * Returns NULL if PV entries were reclaimed from the specified pmap. 1844 * 1845 * We do not, however, unmap 2mpages because subsequent accesses will 1846 * allocate per-page pv entries until repromotion occurs, thereby 1847 * exacerbating the shortage of free pv entries. 1848 */ 1849static vm_page_t 1850reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp) 1851{ 1852 struct pch new_tail; 1853 struct pv_chunk *pc; 1854 struct md_page *pvh; 1855 pd_entry_t *pde; 1856 pmap_t pmap; 1857 pt_entry_t *pte, tpte; 1858 pv_entry_t pv; 1859 vm_offset_t va; 1860 vm_page_t m, m_pc; 1861 struct spglist free; 1862 uint64_t inuse; 1863 int bit, field, freed, lvl; 1864 1865 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1866 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL")); 1867 pmap = NULL; 1868 m_pc = NULL; 1869 SLIST_INIT(&free); 1870 TAILQ_INIT(&new_tail); 1871 mtx_lock(&pv_chunks_mutex); 1872 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) { 1873 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1874 mtx_unlock(&pv_chunks_mutex); 1875 if (pmap != pc->pc_pmap) { 1876 if (pmap != NULL && pmap != locked_pmap) 1877 PMAP_UNLOCK(pmap); 1878 pmap = pc->pc_pmap; 1879 /* Avoid deadlock and lock recursion. */ 1880 if (pmap > locked_pmap) { 1881 RELEASE_PV_LIST_LOCK(lockp); 1882 PMAP_LOCK(pmap); 1883 } else if (pmap != locked_pmap && 1884 !PMAP_TRYLOCK(pmap)) { 1885 pmap = NULL; 1886 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru); 1887 mtx_lock(&pv_chunks_mutex); 1888 continue; 1889 } 1890 } 1891 1892 /* 1893 * Destroy every non-wired, 4 KB page mapping in the chunk. 1894 */ 1895 freed = 0; 1896 for (field = 0; field < _NPCM; field++) { 1897 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 1898 inuse != 0; inuse &= ~(1UL << bit)) { 1899 bit = ffsl(inuse) - 1; 1900 pv = &pc->pc_pventry[field * 64 + bit]; 1901 va = pv->pv_va; 1902 pde = pmap_pde(pmap, va, &lvl); 1903 if (lvl != 2) 1904 continue; 1905 pte = pmap_l2_to_l3(pde, va); 1906 tpte = pmap_load(pte); 1907 if ((tpte & ATTR_SW_WIRED) != 0) 1908 continue; 1909 tpte = pmap_load_clear(pte); 1910 PTE_SYNC(pte); 1911 pmap_invalidate_page(pmap, va); 1912 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK); 1913 if (pmap_page_dirty(tpte)) 1914 vm_page_dirty(m); 1915 if ((tpte & ATTR_AF) != 0) 1916 vm_page_aflag_set(m, PGA_REFERENCED); 1917 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 1918 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 1919 m->md.pv_gen++; 1920 if (TAILQ_EMPTY(&m->md.pv_list) && 1921 (m->flags & PG_FICTITIOUS) == 0) { 1922 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 1923 if (TAILQ_EMPTY(&pvh->pv_list)) { 1924 vm_page_aflag_clear(m, 1925 PGA_WRITEABLE); 1926 } 1927 } 1928 pc->pc_map[field] |= 1UL << bit; 1929 pmap_unuse_l3(pmap, va, pmap_load(pde), &free); 1930 freed++; 1931 } 1932 } 1933 if (freed == 0) { 1934 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru); 1935 mtx_lock(&pv_chunks_mutex); 1936 continue; 1937 } 1938 /* Every freed mapping is for a 4 KB page. */ 1939 pmap_resident_count_dec(pmap, freed); 1940 PV_STAT(atomic_add_long(&pv_entry_frees, freed)); 1941 PV_STAT(atomic_add_int(&pv_entry_spare, freed)); 1942 PV_STAT(atomic_subtract_long(&pv_entry_count, freed)); 1943 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1944 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 && 1945 pc->pc_map[2] == PC_FREE2) { 1946 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV)); 1947 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1)); 1948 PV_STAT(atomic_add_int(&pc_chunk_frees, 1)); 1949 /* Entire chunk is free; return it. */ 1950 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 1951 dump_drop_page(m_pc->phys_addr); 1952 mtx_lock(&pv_chunks_mutex); 1953 break; 1954 } 1955 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1956 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru); 1957 mtx_lock(&pv_chunks_mutex); 1958 /* One freed pv entry in locked_pmap is sufficient. */ 1959 if (pmap == locked_pmap) 1960 break; 1961 } 1962 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru); 1963 mtx_unlock(&pv_chunks_mutex); 1964 if (pmap != NULL && pmap != locked_pmap) 1965 PMAP_UNLOCK(pmap); 1966 if (m_pc == NULL && !SLIST_EMPTY(&free)) { 1967 m_pc = SLIST_FIRST(&free); 1968 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 1969 /* Recycle a freed page table page. */ 1970 m_pc->wire_count = 1; 1971 atomic_add_int(&vm_cnt.v_wire_count, 1); 1972 } 1973 pmap_free_zero_pages(&free); 1974 return (m_pc); 1975} 1976 1977/* 1978 * free the pv_entry back to the free list 1979 */ 1980static void 1981free_pv_entry(pmap_t pmap, pv_entry_t pv) 1982{ 1983 struct pv_chunk *pc; 1984 int idx, field, bit; 1985 1986 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1987 PV_STAT(atomic_add_long(&pv_entry_frees, 1)); 1988 PV_STAT(atomic_add_int(&pv_entry_spare, 1)); 1989 PV_STAT(atomic_subtract_long(&pv_entry_count, 1)); 1990 pc = pv_to_chunk(pv); 1991 idx = pv - &pc->pc_pventry[0]; 1992 field = idx / 64; 1993 bit = idx % 64; 1994 pc->pc_map[field] |= 1ul << bit; 1995 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 || 1996 pc->pc_map[2] != PC_FREE2) { 1997 /* 98% of the time, pc is already at the head of the list. */ 1998 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) { 1999 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2000 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2001 } 2002 return; 2003 } 2004 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2005 free_pv_chunk(pc); 2006} 2007 2008static void 2009free_pv_chunk(struct pv_chunk *pc) 2010{ 2011 vm_page_t m; 2012 2013 mtx_lock(&pv_chunks_mutex); 2014 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2015 mtx_unlock(&pv_chunks_mutex); 2016 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV)); 2017 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1)); 2018 PV_STAT(atomic_add_int(&pc_chunk_frees, 1)); 2019 /* entire chunk is free, return it */ 2020 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 2021 dump_drop_page(m->phys_addr); 2022 vm_page_unwire(m, PQ_NONE); 2023 vm_page_free(m); 2024} 2025 2026/* 2027 * Returns a new PV entry, allocating a new PV chunk from the system when 2028 * needed. If this PV chunk allocation fails and a PV list lock pointer was 2029 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is 2030 * returned. 2031 * 2032 * The given PV list lock may be released. 2033 */ 2034static pv_entry_t 2035get_pv_entry(pmap_t pmap, struct rwlock **lockp) 2036{ 2037 int bit, field; 2038 pv_entry_t pv; 2039 struct pv_chunk *pc; 2040 vm_page_t m; 2041 2042 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2043 PV_STAT(atomic_add_long(&pv_entry_allocs, 1)); 2044retry: 2045 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2046 if (pc != NULL) { 2047 for (field = 0; field < _NPCM; field++) { 2048 if (pc->pc_map[field]) { 2049 bit = ffsl(pc->pc_map[field]) - 1; 2050 break; 2051 } 2052 } 2053 if (field < _NPCM) { 2054 pv = &pc->pc_pventry[field * 64 + bit]; 2055 pc->pc_map[field] &= ~(1ul << bit); 2056 /* If this was the last item, move it to tail */ 2057 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && 2058 pc->pc_map[2] == 0) { 2059 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2060 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, 2061 pc_list); 2062 } 2063 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 2064 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1)); 2065 return (pv); 2066 } 2067 } 2068 /* No free items, allocate another chunk */ 2069 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 2070 VM_ALLOC_WIRED); 2071 if (m == NULL) { 2072 if (lockp == NULL) { 2073 PV_STAT(pc_chunk_tryfail++); 2074 return (NULL); 2075 } 2076 m = reclaim_pv_chunk(pmap, lockp); 2077 if (m == NULL) 2078 goto retry; 2079 } 2080 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 2081 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 2082 dump_add_page(m->phys_addr); 2083 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 2084 pc->pc_pmap = pmap; 2085 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */ 2086 pc->pc_map[1] = PC_FREE1; 2087 pc->pc_map[2] = PC_FREE2; 2088 mtx_lock(&pv_chunks_mutex); 2089 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2090 mtx_unlock(&pv_chunks_mutex); 2091 pv = &pc->pc_pventry[0]; 2092 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2093 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 2094 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1)); 2095 return (pv); 2096} 2097 2098/* 2099 * Ensure that the number of spare PV entries in the specified pmap meets or 2100 * exceeds the given count, "needed". 2101 * 2102 * The given PV list lock may be released. 2103 */ 2104static void 2105reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp) 2106{ 2107 struct pch new_tail; 2108 struct pv_chunk *pc; 2109 int avail, free; 2110 vm_page_t m; 2111 2112 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2113 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL")); 2114 2115 /* 2116 * Newly allocated PV chunks must be stored in a private list until 2117 * the required number of PV chunks have been allocated. Otherwise, 2118 * reclaim_pv_chunk() could recycle one of these chunks. In 2119 * contrast, these chunks must be added to the pmap upon allocation. 2120 */ 2121 TAILQ_INIT(&new_tail); 2122retry: 2123 avail = 0; 2124 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) { 2125 bit_count((bitstr_t *)pc->pc_map, 0, 2126 sizeof(pc->pc_map) * NBBY, &free); 2127 if (free == 0) 2128 break; 2129 avail += free; 2130 if (avail >= needed) 2131 break; 2132 } 2133 for (; avail < needed; avail += _NPCPV) { 2134 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 2135 VM_ALLOC_WIRED); 2136 if (m == NULL) { 2137 m = reclaim_pv_chunk(pmap, lockp); 2138 if (m == NULL) 2139 goto retry; 2140 } 2141 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 2142 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 2143 dump_add_page(m->phys_addr); 2144 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 2145 pc->pc_pmap = pmap; 2146 pc->pc_map[0] = PC_FREE0; 2147 pc->pc_map[1] = PC_FREE1; 2148 pc->pc_map[2] = PC_FREE2; 2149 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2150 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru); 2151 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV)); 2152 } 2153 if (!TAILQ_EMPTY(&new_tail)) { 2154 mtx_lock(&pv_chunks_mutex); 2155 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru); 2156 mtx_unlock(&pv_chunks_mutex); 2157 } 2158} 2159 2160/* 2161 * First find and then remove the pv entry for the specified pmap and virtual 2162 * address from the specified pv list. Returns the pv entry if found and NULL 2163 * otherwise. This operation can be performed on pv lists for either 4KB or 2164 * 2MB page mappings. 2165 */ 2166static __inline pv_entry_t 2167pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2168{ 2169 pv_entry_t pv; 2170 2171 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2172 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2173 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2174 pvh->pv_gen++; 2175 break; 2176 } 2177 } 2178 return (pv); 2179} 2180 2181/* 2182 * After demotion from a 2MB page mapping to 512 4KB page mappings, 2183 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv 2184 * entries for each of the 4KB page mappings. 2185 */ 2186static void 2187pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 2188 struct rwlock **lockp) 2189{ 2190 struct md_page *pvh; 2191 struct pv_chunk *pc; 2192 pv_entry_t pv; 2193 vm_offset_t va_last; 2194 vm_page_t m; 2195 int bit, field; 2196 2197 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2198 KASSERT((pa & L2_OFFSET) == 0, 2199 ("pmap_pv_demote_l2: pa is not 2mpage aligned")); 2200 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 2201 2202 /* 2203 * Transfer the 2mpage's pv entry for this mapping to the first 2204 * page's pv list. Once this transfer begins, the pv list lock 2205 * must not be released until the last pv entry is reinstantiated. 2206 */ 2207 pvh = pa_to_pvh(pa); 2208 va = va & ~L2_OFFSET; 2209 pv = pmap_pvh_remove(pvh, pmap, va); 2210 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found")); 2211 m = PHYS_TO_VM_PAGE(pa); 2212 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2213 m->md.pv_gen++; 2214 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */ 2215 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1)); 2216 va_last = va + L2_SIZE - PAGE_SIZE; 2217 for (;;) { 2218 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2219 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 || 2220 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare")); 2221 for (field = 0; field < _NPCM; field++) { 2222 while (pc->pc_map[field]) { 2223 bit = ffsl(pc->pc_map[field]) - 1; 2224 pc->pc_map[field] &= ~(1ul << bit); 2225 pv = &pc->pc_pventry[field * 64 + bit]; 2226 va += PAGE_SIZE; 2227 pv->pv_va = va; 2228 m++; 2229 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2230 ("pmap_pv_demote_l2: page %p is not managed", m)); 2231 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2232 m->md.pv_gen++; 2233 if (va == va_last) 2234 goto out; 2235 } 2236 } 2237 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2238 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2239 } 2240out: 2241 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) { 2242 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2243 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2244 } 2245 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1)); 2246 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1)); 2247} 2248 2249/* 2250 * First find and then destroy the pv entry for the specified pmap and virtual 2251 * address. This operation can be performed on pv lists for either 4KB or 2MB 2252 * page mappings. 2253 */ 2254static void 2255pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2256{ 2257 pv_entry_t pv; 2258 2259 pv = pmap_pvh_remove(pvh, pmap, va); 2260 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2261 free_pv_entry(pmap, pv); 2262} 2263 2264/* 2265 * Conditionally create the PV entry for a 4KB page mapping if the required 2266 * memory can be allocated without resorting to reclamation. 2267 */ 2268static boolean_t 2269pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m, 2270 struct rwlock **lockp) 2271{ 2272 pv_entry_t pv; 2273 2274 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2275 /* Pass NULL instead of the lock pointer to disable reclamation. */ 2276 if ((pv = get_pv_entry(pmap, NULL)) != NULL) { 2277 pv->pv_va = va; 2278 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 2279 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2280 m->md.pv_gen++; 2281 return (TRUE); 2282 } else 2283 return (FALSE); 2284} 2285 2286/* 2287 * pmap_remove_l3: do the things to unmap a page in a process 2288 */ 2289static int 2290pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va, 2291 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp) 2292{ 2293 struct md_page *pvh; 2294 pt_entry_t old_l3; 2295 vm_page_t m; 2296 2297 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2298 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(pmap_load(l3))) 2299 cpu_dcache_wb_range(va, L3_SIZE); 2300 old_l3 = pmap_load_clear(l3); 2301 PTE_SYNC(l3); 2302 pmap_invalidate_page(pmap, va); 2303 if (old_l3 & ATTR_SW_WIRED) 2304 pmap->pm_stats.wired_count -= 1; 2305 pmap_resident_count_dec(pmap, 1); 2306 if (old_l3 & ATTR_SW_MANAGED) { 2307 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK); 2308 if (pmap_page_dirty(old_l3)) 2309 vm_page_dirty(m); 2310 if (old_l3 & ATTR_AF) 2311 vm_page_aflag_set(m, PGA_REFERENCED); 2312 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 2313 pmap_pvh_free(&m->md, pmap, va); 2314 if (TAILQ_EMPTY(&m->md.pv_list) && 2315 (m->flags & PG_FICTITIOUS) == 0) { 2316 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2317 if (TAILQ_EMPTY(&pvh->pv_list)) 2318 vm_page_aflag_clear(m, PGA_WRITEABLE); 2319 } 2320 } 2321 return (pmap_unuse_l3(pmap, va, l2e, free)); 2322} 2323 2324/* 2325 * Remove the given range of addresses from the specified map. 2326 * 2327 * It is assumed that the start and end are properly 2328 * rounded to the page size. 2329 */ 2330void 2331pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2332{ 2333 struct rwlock *lock; 2334 vm_offset_t va, va_next; 2335 pd_entry_t *l0, *l1, *l2; 2336 pt_entry_t l3_paddr, *l3; 2337 struct spglist free; 2338 2339 /* 2340 * Perform an unsynchronized read. This is, however, safe. 2341 */ 2342 if (pmap->pm_stats.resident_count == 0) 2343 return; 2344 2345 SLIST_INIT(&free); 2346 2347 PMAP_LOCK(pmap); 2348 2349 lock = NULL; 2350 for (; sva < eva; sva = va_next) { 2351 2352 if (pmap->pm_stats.resident_count == 0) 2353 break; 2354 2355 l0 = pmap_l0(pmap, sva); 2356 if (pmap_load(l0) == 0) { 2357 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 2358 if (va_next < sva) 2359 va_next = eva; 2360 continue; 2361 } 2362 2363 l1 = pmap_l0_to_l1(l0, sva); 2364 if (pmap_load(l1) == 0) { 2365 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 2366 if (va_next < sva) 2367 va_next = eva; 2368 continue; 2369 } 2370 2371 /* 2372 * Calculate index for next page table. 2373 */ 2374 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 2375 if (va_next < sva) 2376 va_next = eva; 2377 2378 l2 = pmap_l1_to_l2(l1, sva); 2379 if (l2 == NULL) 2380 continue; 2381 2382 l3_paddr = pmap_load(l2); 2383 2384 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) { 2385 /* TODO: Add pmap_remove_l2 */ 2386 if (pmap_demote_l2_locked(pmap, l2, sva & ~L2_OFFSET, 2387 &lock) == NULL) 2388 continue; 2389 l3_paddr = pmap_load(l2); 2390 } 2391 2392 /* 2393 * Weed out invalid mappings. 2394 */ 2395 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE) 2396 continue; 2397 2398 /* 2399 * Limit our scan to either the end of the va represented 2400 * by the current page table page, or to the end of the 2401 * range being removed. 2402 */ 2403 if (va_next > eva) 2404 va_next = eva; 2405 2406 va = va_next; 2407 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++, 2408 sva += L3_SIZE) { 2409 if (l3 == NULL) 2410 panic("l3 == NULL"); 2411 if (pmap_load(l3) == 0) { 2412 if (va != va_next) { 2413 pmap_invalidate_range(pmap, va, sva); 2414 va = va_next; 2415 } 2416 continue; 2417 } 2418 if (va == va_next) 2419 va = sva; 2420 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free, 2421 &lock)) { 2422 sva += L3_SIZE; 2423 break; 2424 } 2425 } 2426 if (va != va_next) 2427 pmap_invalidate_range(pmap, va, sva); 2428 } 2429 if (lock != NULL) 2430 rw_wunlock(lock); 2431 PMAP_UNLOCK(pmap); 2432 pmap_free_zero_pages(&free); 2433} 2434 2435/* 2436 * Routine: pmap_remove_all 2437 * Function: 2438 * Removes this physical page from 2439 * all physical maps in which it resides. 2440 * Reflects back modify bits to the pager. 2441 * 2442 * Notes: 2443 * Original versions of this routine were very 2444 * inefficient because they iteratively called 2445 * pmap_remove (slow...) 2446 */ 2447 2448void 2449pmap_remove_all(vm_page_t m) 2450{ 2451 struct md_page *pvh; 2452 pv_entry_t pv; 2453 pmap_t pmap; 2454 struct rwlock *lock; 2455 pd_entry_t *pde, tpde; 2456 pt_entry_t *pte, tpte; 2457 vm_offset_t va; 2458 struct spglist free; 2459 int lvl, pvh_gen, md_gen; 2460 2461 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2462 ("pmap_remove_all: page %p is not managed", m)); 2463 SLIST_INIT(&free); 2464 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 2465 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : 2466 pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2467retry: 2468 rw_wlock(lock); 2469 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2470 pmap = PV_PMAP(pv); 2471 if (!PMAP_TRYLOCK(pmap)) { 2472 pvh_gen = pvh->pv_gen; 2473 rw_wunlock(lock); 2474 PMAP_LOCK(pmap); 2475 rw_wlock(lock); 2476 if (pvh_gen != pvh->pv_gen) { 2477 rw_wunlock(lock); 2478 PMAP_UNLOCK(pmap); 2479 goto retry; 2480 } 2481 } 2482 va = pv->pv_va; 2483 pte = pmap_pte(pmap, va, &lvl); 2484 KASSERT(pte != NULL, 2485 ("pmap_remove_all: no page table entry found")); 2486 KASSERT(lvl == 2, 2487 ("pmap_remove_all: invalid pte level %d", lvl)); 2488 2489 pmap_demote_l2_locked(pmap, pte, va, &lock); 2490 PMAP_UNLOCK(pmap); 2491 } 2492 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2493 pmap = PV_PMAP(pv); 2494 if (!PMAP_TRYLOCK(pmap)) { 2495 pvh_gen = pvh->pv_gen; 2496 md_gen = m->md.pv_gen; 2497 rw_wunlock(lock); 2498 PMAP_LOCK(pmap); 2499 rw_wlock(lock); 2500 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 2501 rw_wunlock(lock); 2502 PMAP_UNLOCK(pmap); 2503 goto retry; 2504 } 2505 } 2506 pmap_resident_count_dec(pmap, 1); 2507 2508 pde = pmap_pde(pmap, pv->pv_va, &lvl); 2509 KASSERT(pde != NULL, 2510 ("pmap_remove_all: no page directory entry found")); 2511 KASSERT(lvl == 2, 2512 ("pmap_remove_all: invalid pde level %d", lvl)); 2513 tpde = pmap_load(pde); 2514 2515 pte = pmap_l2_to_l3(pde, pv->pv_va); 2516 tpte = pmap_load(pte); 2517 if (pmap_is_current(pmap) && 2518 pmap_l3_valid_cacheable(tpte)) 2519 cpu_dcache_wb_range(pv->pv_va, L3_SIZE); 2520 pmap_load_clear(pte); 2521 PTE_SYNC(pte); 2522 pmap_invalidate_page(pmap, pv->pv_va); 2523 if (tpte & ATTR_SW_WIRED) 2524 pmap->pm_stats.wired_count--; 2525 if ((tpte & ATTR_AF) != 0) 2526 vm_page_aflag_set(m, PGA_REFERENCED); 2527 2528 /* 2529 * Update the vm_page_t clean and reference bits. 2530 */ 2531 if (pmap_page_dirty(tpte)) 2532 vm_page_dirty(m); 2533 pmap_unuse_l3(pmap, pv->pv_va, tpde, &free); 2534 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2535 m->md.pv_gen++; 2536 free_pv_entry(pmap, pv); 2537 PMAP_UNLOCK(pmap); 2538 } 2539 vm_page_aflag_clear(m, PGA_WRITEABLE); 2540 rw_wunlock(lock); 2541 pmap_free_zero_pages(&free); 2542} 2543 2544/* 2545 * Set the physical protection on the 2546 * specified range of this map as requested. 2547 */ 2548void 2549pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2550{ 2551 vm_offset_t va, va_next; 2552 pd_entry_t *l0, *l1, *l2; 2553 pt_entry_t *l3p, l3, nbits; 2554 2555 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot)); 2556 if (prot == VM_PROT_NONE) { 2557 pmap_remove(pmap, sva, eva); 2558 return; 2559 } 2560 2561 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) == 2562 (VM_PROT_WRITE | VM_PROT_EXECUTE)) 2563 return; 2564 2565 PMAP_LOCK(pmap); 2566 for (; sva < eva; sva = va_next) { 2567 2568 l0 = pmap_l0(pmap, sva); 2569 if (pmap_load(l0) == 0) { 2570 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 2571 if (va_next < sva) 2572 va_next = eva; 2573 continue; 2574 } 2575 2576 l1 = pmap_l0_to_l1(l0, sva); 2577 if (pmap_load(l1) == 0) { 2578 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 2579 if (va_next < sva) 2580 va_next = eva; 2581 continue; 2582 } 2583 2584 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 2585 if (va_next < sva) 2586 va_next = eva; 2587 2588 l2 = pmap_l1_to_l2(l1, sva); 2589 if (pmap_load(l2) == 0) 2590 continue; 2591 2592 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) { 2593 l3p = pmap_demote_l2(pmap, l2, sva); 2594 if (l3p == NULL) 2595 continue; 2596 } 2597 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 2598 ("pmap_protect: Invalid L2 entry after demotion")); 2599 2600 if (va_next > eva) 2601 va_next = eva; 2602 2603 va = va_next; 2604 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++, 2605 sva += L3_SIZE) { 2606 l3 = pmap_load(l3p); 2607 if (!pmap_l3_valid(l3)) 2608 continue; 2609 2610 nbits = 0; 2611 if ((prot & VM_PROT_WRITE) == 0) { 2612 if ((l3 & ATTR_SW_MANAGED) && 2613 pmap_page_dirty(l3)) { 2614 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & 2615 ~ATTR_MASK)); 2616 } 2617 nbits |= ATTR_AP(ATTR_AP_RO); 2618 } 2619 if ((prot & VM_PROT_EXECUTE) == 0) 2620 nbits |= ATTR_XN; 2621 2622 pmap_set(l3p, nbits); 2623 PTE_SYNC(l3p); 2624 /* XXX: Use pmap_invalidate_range */ 2625 pmap_invalidate_page(pmap, sva); 2626 } 2627 } 2628 PMAP_UNLOCK(pmap); 2629} 2630 2631/* 2632 * Inserts the specified page table page into the specified pmap's collection 2633 * of idle page table pages. Each of a pmap's page table pages is responsible 2634 * for mapping a distinct range of virtual addresses. The pmap's collection is 2635 * ordered by this virtual address range. 2636 */ 2637static __inline int 2638pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 2639{ 2640 2641 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2642 return (vm_radix_insert(&pmap->pm_root, mpte)); 2643} 2644 2645/* 2646 * Removes the page table page mapping the specified virtual address from the 2647 * specified pmap's collection of idle page table pages, and returns it. 2648 * Otherwise, returns NULL if there is no page table page corresponding to the 2649 * specified virtual address. 2650 */ 2651static __inline vm_page_t 2652pmap_remove_pt_page(pmap_t pmap, vm_offset_t va) 2653{ 2654 2655 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2656 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va))); 2657} 2658 2659/* 2660 * Performs a break-before-make update of a pmap entry. This is needed when 2661 * either promoting or demoting pages to ensure the TLB doesn't get into an 2662 * inconsistent state. 2663 */ 2664static void 2665pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte, 2666 vm_offset_t va, vm_size_t size) 2667{ 2668 register_t intr; 2669 2670 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2671 2672 /* 2673 * Ensure we don't get switched out with the page table in an 2674 * inconsistent state. We also need to ensure no interrupts fire 2675 * as they may make use of an address we are about to invalidate. 2676 */ 2677 intr = intr_disable(); 2678 critical_enter(); 2679 2680 /* Clear the old mapping */ 2681 pmap_load_clear(pte); 2682 PTE_SYNC(pte); 2683 pmap_invalidate_range(pmap, va, va + size); 2684 2685 /* Create the new mapping */ 2686 pmap_load_store(pte, newpte); 2687 PTE_SYNC(pte); 2688 2689 critical_exit(); 2690 intr_restore(intr); 2691} 2692 2693/* 2694 * After promotion from 512 4KB page mappings to a single 2MB page mapping, 2695 * replace the many pv entries for the 4KB page mappings by a single pv entry 2696 * for the 2MB page mapping. 2697 */ 2698static void 2699pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 2700 struct rwlock **lockp) 2701{ 2702 struct md_page *pvh; 2703 pv_entry_t pv; 2704 vm_offset_t va_last; 2705 vm_page_t m; 2706 2707 KASSERT((pa & L2_OFFSET) == 0, 2708 ("pmap_pv_promote_l2: pa is not 2mpage aligned")); 2709 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 2710 2711 /* 2712 * Transfer the first page's pv entry for this mapping to the 2mpage's 2713 * pv list. Aside from avoiding the cost of a call to get_pv_entry(), 2714 * a transfer avoids the possibility that get_pv_entry() calls 2715 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the 2716 * mappings that is being promoted. 2717 */ 2718 m = PHYS_TO_VM_PAGE(pa); 2719 va = va & ~L2_OFFSET; 2720 pv = pmap_pvh_remove(&m->md, pmap, va); 2721 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found")); 2722 pvh = pa_to_pvh(pa); 2723 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2724 pvh->pv_gen++; 2725 /* Free the remaining NPTEPG - 1 pv entries. */ 2726 va_last = va + L2_SIZE - PAGE_SIZE; 2727 do { 2728 m++; 2729 va += PAGE_SIZE; 2730 pmap_pvh_free(&m->md, pmap, va); 2731 } while (va < va_last); 2732} 2733 2734/* 2735 * Tries to promote the 512, contiguous 4KB page mappings that are within a 2736 * single level 2 table entry to a single 2MB page mapping. For promotion 2737 * to occur, two conditions must be met: (1) the 4KB page mappings must map 2738 * aligned, contiguous physical memory and (2) the 4KB page mappings must have 2739 * identical characteristics. 2740 */ 2741static void 2742pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va, 2743 struct rwlock **lockp) 2744{ 2745 pt_entry_t *firstl3, *l3, newl2, oldl3, pa; 2746 vm_page_t mpte; 2747 vm_offset_t sva; 2748 2749 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2750 2751 sva = va & ~L2_OFFSET; 2752 firstl3 = pmap_l2_to_l3(l2, sva); 2753 newl2 = pmap_load(firstl3); 2754 2755 /* Check the alingment is valid */ 2756 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) { 2757 atomic_add_long(&pmap_l2_p_failures, 1); 2758 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx" 2759 " in pmap %p", va, pmap); 2760 return; 2761 } 2762 2763 pa = newl2 + L2_SIZE - PAGE_SIZE; 2764 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) { 2765 oldl3 = pmap_load(l3); 2766 if (oldl3 != pa) { 2767 atomic_add_long(&pmap_l2_p_failures, 1); 2768 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx" 2769 " in pmap %p", va, pmap); 2770 return; 2771 } 2772 pa -= PAGE_SIZE; 2773 } 2774 2775 /* 2776 * Save the page table page in its current state until the L2 2777 * mapping the superpage is demoted by pmap_demote_l2() or 2778 * destroyed by pmap_remove_l3(). 2779 */ 2780 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK); 2781 KASSERT(mpte >= vm_page_array && 2782 mpte < &vm_page_array[vm_page_array_size], 2783 ("pmap_promote_l2: page table page is out of range")); 2784 KASSERT(mpte->pindex == pmap_l2_pindex(va), 2785 ("pmap_promote_l2: page table page's pindex is wrong")); 2786 if (pmap_insert_pt_page(pmap, mpte)) { 2787 atomic_add_long(&pmap_l2_p_failures, 1); 2788 CTR2(KTR_PMAP, 2789 "pmap_promote_l2: failure for va %#lx in pmap %p", va, 2790 pmap); 2791 return; 2792 } 2793 2794 if ((newl2 & ATTR_SW_MANAGED) != 0) 2795 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp); 2796 2797 newl2 &= ~ATTR_DESCR_MASK; 2798 newl2 |= L2_BLOCK; 2799 2800 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE); 2801 2802 atomic_add_long(&pmap_l2_promotions, 1); 2803 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va, 2804 pmap); 2805} 2806 2807/* 2808 * Insert the given physical page (p) at 2809 * the specified virtual address (v) in the 2810 * target physical map with the protection requested. 2811 * 2812 * If specified, the page will be wired down, meaning 2813 * that the related pte can not be reclaimed. 2814 * 2815 * NB: This is the only routine which MAY NOT lazy-evaluate 2816 * or lose information. That is, this routine must actually 2817 * insert this page into the given map NOW. 2818 */ 2819int 2820pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 2821 u_int flags, int8_t psind __unused) 2822{ 2823 struct rwlock *lock; 2824 pd_entry_t *pde; 2825 pt_entry_t new_l3, orig_l3; 2826 pt_entry_t *l2, *l3; 2827 pv_entry_t pv; 2828 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa; 2829 vm_page_t mpte, om, l1_m, l2_m, l3_m; 2830 boolean_t nosleep; 2831 int lvl; 2832 2833 va = trunc_page(va); 2834 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 2835 VM_OBJECT_ASSERT_LOCKED(m->object); 2836 pa = VM_PAGE_TO_PHYS(m); 2837 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) | 2838 L3_PAGE); 2839 if ((prot & VM_PROT_WRITE) == 0) 2840 new_l3 |= ATTR_AP(ATTR_AP_RO); 2841 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY) 2842 new_l3 |= ATTR_XN; 2843 if ((flags & PMAP_ENTER_WIRED) != 0) 2844 new_l3 |= ATTR_SW_WIRED; 2845 if ((va >> 63) == 0) 2846 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN; 2847 2848 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa); 2849 2850 mpte = NULL; 2851 2852 lock = NULL; 2853 PMAP_LOCK(pmap); 2854 2855 pde = pmap_pde(pmap, va, &lvl); 2856 if (pde != NULL && lvl == 1) { 2857 l2 = pmap_l1_to_l2(pde, va); 2858 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK && 2859 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET, 2860 &lock)) != NULL) { 2861 l3 = &l3[pmap_l3_index(va)]; 2862 if (va < VM_MAXUSER_ADDRESS) { 2863 mpte = PHYS_TO_VM_PAGE( 2864 pmap_load(l2) & ~ATTR_MASK); 2865 mpte->wire_count++; 2866 } 2867 goto havel3; 2868 } 2869 } 2870 2871 if (va < VM_MAXUSER_ADDRESS) { 2872 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0; 2873 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock); 2874 if (mpte == NULL && nosleep) { 2875 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL"); 2876 if (lock != NULL) 2877 rw_wunlock(lock); 2878 PMAP_UNLOCK(pmap); 2879 return (KERN_RESOURCE_SHORTAGE); 2880 } 2881 pde = pmap_pde(pmap, va, &lvl); 2882 KASSERT(pde != NULL, 2883 ("pmap_enter: Invalid page entry, va: 0x%lx", va)); 2884 KASSERT(lvl == 2, 2885 ("pmap_enter: Invalid level %d", lvl)); 2886 2887 l3 = pmap_l2_to_l3(pde, va); 2888 } else { 2889 /* 2890 * If we get a level 2 pde it must point to a level 3 entry 2891 * otherwise we will need to create the intermediate tables 2892 */ 2893 if (lvl < 2) { 2894 switch(lvl) { 2895 default: 2896 case -1: 2897 /* Get the l0 pde to update */ 2898 pde = pmap_l0(pmap, va); 2899 KASSERT(pde != NULL, ("...")); 2900 2901 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2902 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2903 VM_ALLOC_ZERO); 2904 if (l1_m == NULL) 2905 panic("pmap_enter: l1 pte_m == NULL"); 2906 if ((l1_m->flags & PG_ZERO) == 0) 2907 pmap_zero_page(l1_m); 2908 2909 l1_pa = VM_PAGE_TO_PHYS(l1_m); 2910 pmap_load_store(pde, l1_pa | L0_TABLE); 2911 PTE_SYNC(pde); 2912 /* FALLTHROUGH */ 2913 case 0: 2914 /* Get the l1 pde to update */ 2915 pde = pmap_l1_to_l2(pde, va); 2916 KASSERT(pde != NULL, ("...")); 2917 2918 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2919 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2920 VM_ALLOC_ZERO); 2921 if (l2_m == NULL) 2922 panic("pmap_enter: l2 pte_m == NULL"); 2923 if ((l2_m->flags & PG_ZERO) == 0) 2924 pmap_zero_page(l2_m); 2925 2926 l2_pa = VM_PAGE_TO_PHYS(l2_m); 2927 pmap_load_store(pde, l2_pa | L1_TABLE); 2928 PTE_SYNC(pde); 2929 /* FALLTHROUGH */ 2930 case 1: 2931 /* Get the l2 pde to update */ 2932 pde = pmap_l1_to_l2(pde, va); 2933 2934 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2935 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2936 VM_ALLOC_ZERO); 2937 if (l3_m == NULL) 2938 panic("pmap_enter: l3 pte_m == NULL"); 2939 if ((l3_m->flags & PG_ZERO) == 0) 2940 pmap_zero_page(l3_m); 2941 2942 l3_pa = VM_PAGE_TO_PHYS(l3_m); 2943 pmap_load_store(pde, l3_pa | L2_TABLE); 2944 PTE_SYNC(pde); 2945 break; 2946 } 2947 } 2948 l3 = pmap_l2_to_l3(pde, va); 2949 pmap_invalidate_page(pmap, va); 2950 } 2951havel3: 2952 2953 om = NULL; 2954 orig_l3 = pmap_load(l3); 2955 opa = orig_l3 & ~ATTR_MASK; 2956 2957 /* 2958 * Is the specified virtual address already mapped? 2959 */ 2960 if (pmap_l3_valid(orig_l3)) { 2961 /* 2962 * Wiring change, just update stats. We don't worry about 2963 * wiring PT pages as they remain resident as long as there 2964 * are valid mappings in them. Hence, if a user page is wired, 2965 * the PT page will be also. 2966 */ 2967 if ((flags & PMAP_ENTER_WIRED) != 0 && 2968 (orig_l3 & ATTR_SW_WIRED) == 0) 2969 pmap->pm_stats.wired_count++; 2970 else if ((flags & PMAP_ENTER_WIRED) == 0 && 2971 (orig_l3 & ATTR_SW_WIRED) != 0) 2972 pmap->pm_stats.wired_count--; 2973 2974 /* 2975 * Remove the extra PT page reference. 2976 */ 2977 if (mpte != NULL) { 2978 mpte->wire_count--; 2979 KASSERT(mpte->wire_count > 0, 2980 ("pmap_enter: missing reference to page table page," 2981 " va: 0x%lx", va)); 2982 } 2983 2984 /* 2985 * Has the physical page changed? 2986 */ 2987 if (opa == pa) { 2988 /* 2989 * No, might be a protection or wiring change. 2990 */ 2991 if ((orig_l3 & ATTR_SW_MANAGED) != 0) { 2992 new_l3 |= ATTR_SW_MANAGED; 2993 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) == 2994 ATTR_AP(ATTR_AP_RW)) { 2995 vm_page_aflag_set(m, PGA_WRITEABLE); 2996 } 2997 } 2998 goto validate; 2999 } 3000 3001 /* Flush the cache, there might be uncommitted data in it */ 3002 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(orig_l3)) 3003 cpu_dcache_wb_range(va, L3_SIZE); 3004 } else { 3005 /* 3006 * Increment the counters. 3007 */ 3008 if ((new_l3 & ATTR_SW_WIRED) != 0) 3009 pmap->pm_stats.wired_count++; 3010 pmap_resident_count_inc(pmap, 1); 3011 } 3012 /* 3013 * Enter on the PV list if part of our managed memory. 3014 */ 3015 if ((m->oflags & VPO_UNMANAGED) == 0) { 3016 new_l3 |= ATTR_SW_MANAGED; 3017 pv = get_pv_entry(pmap, &lock); 3018 pv->pv_va = va; 3019 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa); 3020 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3021 m->md.pv_gen++; 3022 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) 3023 vm_page_aflag_set(m, PGA_WRITEABLE); 3024 } 3025 3026 /* 3027 * Update the L3 entry. 3028 */ 3029 if (orig_l3 != 0) { 3030validate: 3031 orig_l3 = pmap_load(l3); 3032 opa = orig_l3 & ~ATTR_MASK; 3033 3034 if (opa != pa) { 3035 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE); 3036 if ((orig_l3 & ATTR_SW_MANAGED) != 0) { 3037 om = PHYS_TO_VM_PAGE(opa); 3038 if (pmap_page_dirty(orig_l3)) 3039 vm_page_dirty(om); 3040 if ((orig_l3 & ATTR_AF) != 0) 3041 vm_page_aflag_set(om, PGA_REFERENCED); 3042 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa); 3043 pmap_pvh_free(&om->md, pmap, va); 3044 if ((om->aflags & PGA_WRITEABLE) != 0 && 3045 TAILQ_EMPTY(&om->md.pv_list) && 3046 ((om->flags & PG_FICTITIOUS) != 0 || 3047 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) 3048 vm_page_aflag_clear(om, PGA_WRITEABLE); 3049 } 3050 } else { 3051 pmap_load_store(l3, new_l3); 3052 PTE_SYNC(l3); 3053 pmap_invalidate_page(pmap, va); 3054 if (pmap_page_dirty(orig_l3) && 3055 (orig_l3 & ATTR_SW_MANAGED) != 0) 3056 vm_page_dirty(m); 3057 } 3058 } else { 3059 pmap_load_store(l3, new_l3); 3060 } 3061 3062 PTE_SYNC(l3); 3063 pmap_invalidate_page(pmap, va); 3064 3065 if (pmap != pmap_kernel()) { 3066 if (pmap == &curproc->p_vmspace->vm_pmap && 3067 (prot & VM_PROT_EXECUTE) != 0) 3068 cpu_icache_sync_range(va, PAGE_SIZE); 3069 3070 if ((mpte == NULL || mpte->wire_count == NL3PG) && 3071 pmap_superpages_enabled() && 3072 (m->flags & PG_FICTITIOUS) == 0 && 3073 vm_reserv_level_iffullpop(m) == 0) { 3074 pmap_promote_l2(pmap, pde, va, &lock); 3075 } 3076 } 3077 3078 if (lock != NULL) 3079 rw_wunlock(lock); 3080 PMAP_UNLOCK(pmap); 3081 return (KERN_SUCCESS); 3082} 3083 3084/* 3085 * Maps a sequence of resident pages belonging to the same object. 3086 * The sequence begins with the given page m_start. This page is 3087 * mapped at the given virtual address start. Each subsequent page is 3088 * mapped at a virtual address that is offset from start by the same 3089 * amount as the page is offset from m_start within the object. The 3090 * last page in the sequence is the page with the largest offset from 3091 * m_start that can be mapped at a virtual address less than the given 3092 * virtual address end. Not every virtual page between start and end 3093 * is mapped; only those for which a resident page exists with the 3094 * corresponding offset from m_start are mapped. 3095 */ 3096void 3097pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3098 vm_page_t m_start, vm_prot_t prot) 3099{ 3100 struct rwlock *lock; 3101 vm_offset_t va; 3102 vm_page_t m, mpte; 3103 vm_pindex_t diff, psize; 3104 3105 VM_OBJECT_ASSERT_LOCKED(m_start->object); 3106 3107 psize = atop(end - start); 3108 mpte = NULL; 3109 m = m_start; 3110 lock = NULL; 3111 PMAP_LOCK(pmap); 3112 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3113 va = start + ptoa(diff); 3114 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock); 3115 m = TAILQ_NEXT(m, listq); 3116 } 3117 if (lock != NULL) 3118 rw_wunlock(lock); 3119 PMAP_UNLOCK(pmap); 3120} 3121 3122/* 3123 * this code makes some *MAJOR* assumptions: 3124 * 1. Current pmap & pmap exists. 3125 * 2. Not wired. 3126 * 3. Read access. 3127 * 4. No page table pages. 3128 * but is *MUCH* faster than pmap_enter... 3129 */ 3130 3131void 3132pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3133{ 3134 struct rwlock *lock; 3135 3136 lock = NULL; 3137 PMAP_LOCK(pmap); 3138 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock); 3139 if (lock != NULL) 3140 rw_wunlock(lock); 3141 PMAP_UNLOCK(pmap); 3142} 3143 3144static vm_page_t 3145pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3146 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp) 3147{ 3148 struct spglist free; 3149 pd_entry_t *pde; 3150 pt_entry_t *l2, *l3; 3151 vm_paddr_t pa; 3152 int lvl; 3153 3154 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3155 (m->oflags & VPO_UNMANAGED) != 0, 3156 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3157 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3158 3159 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va); 3160 /* 3161 * In the case that a page table page is not 3162 * resident, we are creating it here. 3163 */ 3164 if (va < VM_MAXUSER_ADDRESS) { 3165 vm_pindex_t l2pindex; 3166 3167 /* 3168 * Calculate pagetable page index 3169 */ 3170 l2pindex = pmap_l2_pindex(va); 3171 if (mpte && (mpte->pindex == l2pindex)) { 3172 mpte->wire_count++; 3173 } else { 3174 /* 3175 * Get the l2 entry 3176 */ 3177 pde = pmap_pde(pmap, va, &lvl); 3178 3179 /* 3180 * If the page table page is mapped, we just increment 3181 * the hold count, and activate it. Otherwise, we 3182 * attempt to allocate a page table page. If this 3183 * attempt fails, we don't retry. Instead, we give up. 3184 */ 3185 if (lvl == 1) { 3186 l2 = pmap_l1_to_l2(pde, va); 3187 if ((pmap_load(l2) & ATTR_DESCR_MASK) == 3188 L2_BLOCK) 3189 return (NULL); 3190 } 3191 if (lvl == 2 && pmap_load(pde) != 0) { 3192 mpte = 3193 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK); 3194 mpte->wire_count++; 3195 } else { 3196 /* 3197 * Pass NULL instead of the PV list lock 3198 * pointer, because we don't intend to sleep. 3199 */ 3200 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL); 3201 if (mpte == NULL) 3202 return (mpte); 3203 } 3204 } 3205 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte)); 3206 l3 = &l3[pmap_l3_index(va)]; 3207 } else { 3208 mpte = NULL; 3209 pde = pmap_pde(kernel_pmap, va, &lvl); 3210 KASSERT(pde != NULL, 3211 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx", 3212 va)); 3213 KASSERT(lvl == 2, 3214 ("pmap_enter_quick_locked: Invalid level %d", lvl)); 3215 l3 = pmap_l2_to_l3(pde, va); 3216 } 3217 3218 if (pmap_load(l3) != 0) { 3219 if (mpte != NULL) { 3220 mpte->wire_count--; 3221 mpte = NULL; 3222 } 3223 return (mpte); 3224 } 3225 3226 /* 3227 * Enter on the PV list if part of our managed memory. 3228 */ 3229 if ((m->oflags & VPO_UNMANAGED) == 0 && 3230 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) { 3231 if (mpte != NULL) { 3232 SLIST_INIT(&free); 3233 if (pmap_unwire_l3(pmap, va, mpte, &free)) { 3234 pmap_invalidate_page(pmap, va); 3235 pmap_free_zero_pages(&free); 3236 } 3237 mpte = NULL; 3238 } 3239 return (mpte); 3240 } 3241 3242 /* 3243 * Increment counters 3244 */ 3245 pmap_resident_count_inc(pmap, 1); 3246 3247 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) | 3248 ATTR_AP(ATTR_AP_RO) | L3_PAGE; 3249 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY) 3250 pa |= ATTR_XN; 3251 else if (va < VM_MAXUSER_ADDRESS) 3252 pa |= ATTR_PXN; 3253 3254 /* 3255 * Now validate mapping with RO protection 3256 */ 3257 if ((m->oflags & VPO_UNMANAGED) == 0) 3258 pa |= ATTR_SW_MANAGED; 3259 pmap_load_store(l3, pa); 3260 PTE_SYNC(l3); 3261 pmap_invalidate_page(pmap, va); 3262 return (mpte); 3263} 3264 3265/* 3266 * This code maps large physical mmap regions into the 3267 * processor address space. Note that some shortcuts 3268 * are taken, but the code works. 3269 */ 3270void 3271pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3272 vm_pindex_t pindex, vm_size_t size) 3273{ 3274 3275 VM_OBJECT_ASSERT_WLOCKED(object); 3276 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3277 ("pmap_object_init_pt: non-device object")); 3278} 3279 3280/* 3281 * Clear the wired attribute from the mappings for the specified range of 3282 * addresses in the given pmap. Every valid mapping within that range 3283 * must have the wired attribute set. In contrast, invalid mappings 3284 * cannot have the wired attribute set, so they are ignored. 3285 * 3286 * The wired attribute of the page table entry is not a hardware feature, 3287 * so there is no need to invalidate any TLB entries. 3288 */ 3289void 3290pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3291{ 3292 vm_offset_t va_next; 3293 pd_entry_t *l0, *l1, *l2; 3294 pt_entry_t *l3; 3295 3296 PMAP_LOCK(pmap); 3297 for (; sva < eva; sva = va_next) { 3298 l0 = pmap_l0(pmap, sva); 3299 if (pmap_load(l0) == 0) { 3300 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 3301 if (va_next < sva) 3302 va_next = eva; 3303 continue; 3304 } 3305 3306 l1 = pmap_l0_to_l1(l0, sva); 3307 if (pmap_load(l1) == 0) { 3308 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 3309 if (va_next < sva) 3310 va_next = eva; 3311 continue; 3312 } 3313 3314 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 3315 if (va_next < sva) 3316 va_next = eva; 3317 3318 l2 = pmap_l1_to_l2(l1, sva); 3319 if (pmap_load(l2) == 0) 3320 continue; 3321 3322 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) { 3323 l3 = pmap_demote_l2(pmap, l2, sva); 3324 if (l3 == NULL) 3325 continue; 3326 } 3327 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 3328 ("pmap_unwire: Invalid l2 entry after demotion")); 3329 3330 if (va_next > eva) 3331 va_next = eva; 3332 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++, 3333 sva += L3_SIZE) { 3334 if (pmap_load(l3) == 0) 3335 continue; 3336 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0) 3337 panic("pmap_unwire: l3 %#jx is missing " 3338 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3)); 3339 3340 /* 3341 * PG_W must be cleared atomically. Although the pmap 3342 * lock synchronizes access to PG_W, another processor 3343 * could be setting PG_M and/or PG_A concurrently. 3344 */ 3345 atomic_clear_long(l3, ATTR_SW_WIRED); 3346 pmap->pm_stats.wired_count--; 3347 } 3348 } 3349 PMAP_UNLOCK(pmap); 3350} 3351 3352/* 3353 * Copy the range specified by src_addr/len 3354 * from the source map to the range dst_addr/len 3355 * in the destination map. 3356 * 3357 * This routine is only advisory and need not do anything. 3358 */ 3359 3360void 3361pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3362 vm_offset_t src_addr) 3363{ 3364} 3365 3366/* 3367 * pmap_zero_page zeros the specified hardware page by mapping 3368 * the page into KVM and using bzero to clear its contents. 3369 */ 3370void 3371pmap_zero_page(vm_page_t m) 3372{ 3373 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 3374 3375 pagezero((void *)va); 3376} 3377 3378/* 3379 * pmap_zero_page_area zeros the specified hardware page by mapping 3380 * the page into KVM and using bzero to clear its contents. 3381 * 3382 * off and size may not cover an area beyond a single hardware page. 3383 */ 3384void 3385pmap_zero_page_area(vm_page_t m, int off, int size) 3386{ 3387 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 3388 3389 if (off == 0 && size == PAGE_SIZE) 3390 pagezero((void *)va); 3391 else 3392 bzero((char *)va + off, size); 3393} 3394 3395/* 3396 * pmap_zero_page_idle zeros the specified hardware page by mapping 3397 * the page into KVM and using bzero to clear its contents. This 3398 * is intended to be called from the vm_pagezero process only and 3399 * outside of Giant. 3400 */ 3401void 3402pmap_zero_page_idle(vm_page_t m) 3403{ 3404 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 3405 3406 pagezero((void *)va); 3407} 3408 3409/* 3410 * pmap_copy_page copies the specified (machine independent) 3411 * page by mapping the page into virtual memory and using 3412 * bcopy to copy the page, one machine dependent page at a 3413 * time. 3414 */ 3415void 3416pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 3417{ 3418 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc)); 3419 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst)); 3420 3421 pagecopy((void *)src, (void *)dst); 3422} 3423 3424int unmapped_buf_allowed = 1; 3425 3426void 3427pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 3428 vm_offset_t b_offset, int xfersize) 3429{ 3430 void *a_cp, *b_cp; 3431 vm_page_t m_a, m_b; 3432 vm_paddr_t p_a, p_b; 3433 vm_offset_t a_pg_offset, b_pg_offset; 3434 int cnt; 3435 3436 while (xfersize > 0) { 3437 a_pg_offset = a_offset & PAGE_MASK; 3438 m_a = ma[a_offset >> PAGE_SHIFT]; 3439 p_a = m_a->phys_addr; 3440 b_pg_offset = b_offset & PAGE_MASK; 3441 m_b = mb[b_offset >> PAGE_SHIFT]; 3442 p_b = m_b->phys_addr; 3443 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3444 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3445 if (__predict_false(!PHYS_IN_DMAP(p_a))) { 3446 panic("!DMAP a %lx", p_a); 3447 } else { 3448 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset; 3449 } 3450 if (__predict_false(!PHYS_IN_DMAP(p_b))) { 3451 panic("!DMAP b %lx", p_b); 3452 } else { 3453 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset; 3454 } 3455 bcopy(a_cp, b_cp, cnt); 3456 a_offset += cnt; 3457 b_offset += cnt; 3458 xfersize -= cnt; 3459 } 3460} 3461 3462vm_offset_t 3463pmap_quick_enter_page(vm_page_t m) 3464{ 3465 3466 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m))); 3467} 3468 3469void 3470pmap_quick_remove_page(vm_offset_t addr) 3471{ 3472} 3473 3474/* 3475 * Returns true if the pmap's pv is one of the first 3476 * 16 pvs linked to from this page. This count may 3477 * be changed upwards or downwards in the future; it 3478 * is only necessary that true be returned for a small 3479 * subset of pmaps for proper page aging. 3480 */ 3481boolean_t 3482pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3483{ 3484 struct md_page *pvh; 3485 struct rwlock *lock; 3486 pv_entry_t pv; 3487 int loops = 0; 3488 boolean_t rv; 3489 3490 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3491 ("pmap_page_exists_quick: page %p is not managed", m)); 3492 rv = FALSE; 3493 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3494 rw_rlock(lock); 3495 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3496 if (PV_PMAP(pv) == pmap) { 3497 rv = TRUE; 3498 break; 3499 } 3500 loops++; 3501 if (loops >= 16) 3502 break; 3503 } 3504 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 3505 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3506 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 3507 if (PV_PMAP(pv) == pmap) { 3508 rv = TRUE; 3509 break; 3510 } 3511 loops++; 3512 if (loops >= 16) 3513 break; 3514 } 3515 } 3516 rw_runlock(lock); 3517 return (rv); 3518} 3519 3520/* 3521 * pmap_page_wired_mappings: 3522 * 3523 * Return the number of managed mappings to the given physical page 3524 * that are wired. 3525 */ 3526int 3527pmap_page_wired_mappings(vm_page_t m) 3528{ 3529 struct rwlock *lock; 3530 struct md_page *pvh; 3531 pmap_t pmap; 3532 pt_entry_t *pte; 3533 pv_entry_t pv; 3534 int count, lvl, md_gen, pvh_gen; 3535 3536 if ((m->oflags & VPO_UNMANAGED) != 0) 3537 return (0); 3538 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3539 rw_rlock(lock); 3540restart: 3541 count = 0; 3542 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3543 pmap = PV_PMAP(pv); 3544 if (!PMAP_TRYLOCK(pmap)) { 3545 md_gen = m->md.pv_gen; 3546 rw_runlock(lock); 3547 PMAP_LOCK(pmap); 3548 rw_rlock(lock); 3549 if (md_gen != m->md.pv_gen) { 3550 PMAP_UNLOCK(pmap); 3551 goto restart; 3552 } 3553 } 3554 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3555 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0) 3556 count++; 3557 PMAP_UNLOCK(pmap); 3558 } 3559 if ((m->flags & PG_FICTITIOUS) == 0) { 3560 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3561 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 3562 pmap = PV_PMAP(pv); 3563 if (!PMAP_TRYLOCK(pmap)) { 3564 md_gen = m->md.pv_gen; 3565 pvh_gen = pvh->pv_gen; 3566 rw_runlock(lock); 3567 PMAP_LOCK(pmap); 3568 rw_rlock(lock); 3569 if (md_gen != m->md.pv_gen || 3570 pvh_gen != pvh->pv_gen) { 3571 PMAP_UNLOCK(pmap); 3572 goto restart; 3573 } 3574 } 3575 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3576 if (pte != NULL && 3577 (pmap_load(pte) & ATTR_SW_WIRED) != 0) 3578 count++; 3579 PMAP_UNLOCK(pmap); 3580 } 3581 } 3582 rw_runlock(lock); 3583 return (count); 3584} 3585 3586/* 3587 * Destroy all managed, non-wired mappings in the given user-space 3588 * pmap. This pmap cannot be active on any processor besides the 3589 * caller. 3590 * 3591 * This function cannot be applied to the kernel pmap. Moreover, it 3592 * is not intended for general use. It is only to be used during 3593 * process termination. Consequently, it can be implemented in ways 3594 * that make it faster than pmap_remove(). First, it can more quickly 3595 * destroy mappings by iterating over the pmap's collection of PV 3596 * entries, rather than searching the page table. Second, it doesn't 3597 * have to test and clear the page table entries atomically, because 3598 * no processor is currently accessing the user address space. In 3599 * particular, a page table entry's dirty bit won't change state once 3600 * this function starts. 3601 */ 3602void 3603pmap_remove_pages(pmap_t pmap) 3604{ 3605 pd_entry_t *pde; 3606 pt_entry_t *pte, tpte; 3607 struct spglist free; 3608 vm_page_t m, ml3, mt; 3609 pv_entry_t pv; 3610 struct md_page *pvh; 3611 struct pv_chunk *pc, *npc; 3612 struct rwlock *lock; 3613 int64_t bit; 3614 uint64_t inuse, bitmask; 3615 int allfree, field, freed, idx, lvl; 3616 vm_paddr_t pa; 3617 3618 lock = NULL; 3619 3620 SLIST_INIT(&free); 3621 PMAP_LOCK(pmap); 3622 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3623 allfree = 1; 3624 freed = 0; 3625 for (field = 0; field < _NPCM; field++) { 3626 inuse = ~pc->pc_map[field] & pc_freemask[field]; 3627 while (inuse != 0) { 3628 bit = ffsl(inuse) - 1; 3629 bitmask = 1UL << bit; 3630 idx = field * 64 + bit; 3631 pv = &pc->pc_pventry[idx]; 3632 inuse &= ~bitmask; 3633 3634 pde = pmap_pde(pmap, pv->pv_va, &lvl); 3635 KASSERT(pde != NULL, 3636 ("Attempting to remove an unmapped page")); 3637 3638 switch(lvl) { 3639 case 1: 3640 pte = pmap_l1_to_l2(pde, pv->pv_va); 3641 tpte = pmap_load(pte); 3642 KASSERT((tpte & ATTR_DESCR_MASK) == 3643 L2_BLOCK, 3644 ("Attempting to remove an invalid " 3645 "block: %lx", tpte)); 3646 tpte = pmap_load(pte); 3647 break; 3648 case 2: 3649 pte = pmap_l2_to_l3(pde, pv->pv_va); 3650 tpte = pmap_load(pte); 3651 KASSERT((tpte & ATTR_DESCR_MASK) == 3652 L3_PAGE, 3653 ("Attempting to remove an invalid " 3654 "page: %lx", tpte)); 3655 break; 3656 default: 3657 panic( 3658 "Invalid page directory level: %d", 3659 lvl); 3660 } 3661 3662/* 3663 * We cannot remove wired pages from a process' mapping at this time 3664 */ 3665 if (tpte & ATTR_SW_WIRED) { 3666 allfree = 0; 3667 continue; 3668 } 3669 3670 pa = tpte & ~ATTR_MASK; 3671 3672 m = PHYS_TO_VM_PAGE(pa); 3673 KASSERT(m->phys_addr == pa, 3674 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3675 m, (uintmax_t)m->phys_addr, 3676 (uintmax_t)tpte)); 3677 3678 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 3679 m < &vm_page_array[vm_page_array_size], 3680 ("pmap_remove_pages: bad pte %#jx", 3681 (uintmax_t)tpte)); 3682 3683 if (pmap_is_current(pmap)) { 3684 if (lvl == 2 && 3685 pmap_l3_valid_cacheable(tpte)) { 3686 cpu_dcache_wb_range(pv->pv_va, 3687 L3_SIZE); 3688 } else if (lvl == 1 && 3689 pmap_pte_valid_cacheable(tpte)) { 3690 cpu_dcache_wb_range(pv->pv_va, 3691 L2_SIZE); 3692 } 3693 } 3694 pmap_load_clear(pte); 3695 PTE_SYNC(pte); 3696 pmap_invalidate_page(pmap, pv->pv_va); 3697 3698 /* 3699 * Update the vm_page_t clean/reference bits. 3700 */ 3701 if ((tpte & ATTR_AP_RW_BIT) == 3702 ATTR_AP(ATTR_AP_RW)) { 3703 switch (lvl) { 3704 case 1: 3705 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 3706 vm_page_dirty(m); 3707 break; 3708 case 2: 3709 vm_page_dirty(m); 3710 break; 3711 } 3712 } 3713 3714 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m); 3715 3716 /* Mark free */ 3717 pc->pc_map[field] |= bitmask; 3718 switch (lvl) { 3719 case 1: 3720 pmap_resident_count_dec(pmap, 3721 L2_SIZE / PAGE_SIZE); 3722 pvh = pa_to_pvh(tpte & ~ATTR_MASK); 3723 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next); 3724 pvh->pv_gen++; 3725 if (TAILQ_EMPTY(&pvh->pv_list)) { 3726 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 3727 if ((mt->aflags & PGA_WRITEABLE) != 0 && 3728 TAILQ_EMPTY(&mt->md.pv_list)) 3729 vm_page_aflag_clear(mt, PGA_WRITEABLE); 3730 } 3731 ml3 = pmap_remove_pt_page(pmap, 3732 pv->pv_va); 3733 if (ml3 != NULL) { 3734 pmap_resident_count_dec(pmap,1); 3735 KASSERT(ml3->wire_count == NL3PG, 3736 ("pmap_remove_pages: l3 page wire count error")); 3737 ml3->wire_count = 0; 3738 pmap_add_delayed_free_list(ml3, 3739 &free, FALSE); 3740 atomic_subtract_int( 3741 &vm_cnt.v_wire_count, 1); 3742 } 3743 break; 3744 case 2: 3745 pmap_resident_count_dec(pmap, 1); 3746 TAILQ_REMOVE(&m->md.pv_list, pv, 3747 pv_next); 3748 m->md.pv_gen++; 3749 if ((m->aflags & PGA_WRITEABLE) != 0 && 3750 TAILQ_EMPTY(&m->md.pv_list) && 3751 (m->flags & PG_FICTITIOUS) == 0) { 3752 pvh = pa_to_pvh( 3753 VM_PAGE_TO_PHYS(m)); 3754 if (TAILQ_EMPTY(&pvh->pv_list)) 3755 vm_page_aflag_clear(m, 3756 PGA_WRITEABLE); 3757 } 3758 break; 3759 } 3760 pmap_unuse_l3(pmap, pv->pv_va, pmap_load(pde), 3761 &free); 3762 freed++; 3763 } 3764 } 3765 PV_STAT(atomic_add_long(&pv_entry_frees, freed)); 3766 PV_STAT(atomic_add_int(&pv_entry_spare, freed)); 3767 PV_STAT(atomic_subtract_long(&pv_entry_count, freed)); 3768 if (allfree) { 3769 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3770 free_pv_chunk(pc); 3771 } 3772 } 3773 pmap_invalidate_all(pmap); 3774 if (lock != NULL) 3775 rw_wunlock(lock); 3776 PMAP_UNLOCK(pmap); 3777 pmap_free_zero_pages(&free); 3778} 3779 3780/* 3781 * This is used to check if a page has been accessed or modified. As we 3782 * don't have a bit to see if it has been modified we have to assume it 3783 * has been if the page is read/write. 3784 */ 3785static boolean_t 3786pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified) 3787{ 3788 struct rwlock *lock; 3789 pv_entry_t pv; 3790 struct md_page *pvh; 3791 pt_entry_t *pte, mask, value; 3792 pmap_t pmap; 3793 int lvl, md_gen, pvh_gen; 3794 boolean_t rv; 3795 3796 rv = FALSE; 3797 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3798 rw_rlock(lock); 3799restart: 3800 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3801 pmap = PV_PMAP(pv); 3802 if (!PMAP_TRYLOCK(pmap)) { 3803 md_gen = m->md.pv_gen; 3804 rw_runlock(lock); 3805 PMAP_LOCK(pmap); 3806 rw_rlock(lock); 3807 if (md_gen != m->md.pv_gen) { 3808 PMAP_UNLOCK(pmap); 3809 goto restart; 3810 } 3811 } 3812 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3813 KASSERT(lvl == 3, 3814 ("pmap_page_test_mappings: Invalid level %d", lvl)); 3815 mask = 0; 3816 value = 0; 3817 if (modified) { 3818 mask |= ATTR_AP_RW_BIT; 3819 value |= ATTR_AP(ATTR_AP_RW); 3820 } 3821 if (accessed) { 3822 mask |= ATTR_AF | ATTR_DESCR_MASK; 3823 value |= ATTR_AF | L3_PAGE; 3824 } 3825 rv = (pmap_load(pte) & mask) == value; 3826 PMAP_UNLOCK(pmap); 3827 if (rv) 3828 goto out; 3829 } 3830 if ((m->flags & PG_FICTITIOUS) == 0) { 3831 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3832 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 3833 pmap = PV_PMAP(pv); 3834 if (!PMAP_TRYLOCK(pmap)) { 3835 md_gen = m->md.pv_gen; 3836 pvh_gen = pvh->pv_gen; 3837 rw_runlock(lock); 3838 PMAP_LOCK(pmap); 3839 rw_rlock(lock); 3840 if (md_gen != m->md.pv_gen || 3841 pvh_gen != pvh->pv_gen) { 3842 PMAP_UNLOCK(pmap); 3843 goto restart; 3844 } 3845 } 3846 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3847 KASSERT(lvl == 2, 3848 ("pmap_page_test_mappings: Invalid level %d", lvl)); 3849 mask = 0; 3850 value = 0; 3851 if (modified) { 3852 mask |= ATTR_AP_RW_BIT; 3853 value |= ATTR_AP(ATTR_AP_RW); 3854 } 3855 if (accessed) { 3856 mask |= ATTR_AF | ATTR_DESCR_MASK; 3857 value |= ATTR_AF | L2_BLOCK; 3858 } 3859 rv = (pmap_load(pte) & mask) == value; 3860 PMAP_UNLOCK(pmap); 3861 if (rv) 3862 goto out; 3863 } 3864 } 3865out: 3866 rw_runlock(lock); 3867 return (rv); 3868} 3869 3870/* 3871 * pmap_is_modified: 3872 * 3873 * Return whether or not the specified physical page was modified 3874 * in any physical maps. 3875 */ 3876boolean_t 3877pmap_is_modified(vm_page_t m) 3878{ 3879 3880 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3881 ("pmap_is_modified: page %p is not managed", m)); 3882 3883 /* 3884 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3885 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3886 * is clear, no PTEs can have PG_M set. 3887 */ 3888 VM_OBJECT_ASSERT_WLOCKED(m->object); 3889 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3890 return (FALSE); 3891 return (pmap_page_test_mappings(m, FALSE, TRUE)); 3892} 3893 3894/* 3895 * pmap_is_prefaultable: 3896 * 3897 * Return whether or not the specified virtual address is eligible 3898 * for prefault. 3899 */ 3900boolean_t 3901pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3902{ 3903 pt_entry_t *pte; 3904 boolean_t rv; 3905 int lvl; 3906 3907 rv = FALSE; 3908 PMAP_LOCK(pmap); 3909 pte = pmap_pte(pmap, addr, &lvl); 3910 if (pte != NULL && pmap_load(pte) != 0) { 3911 rv = TRUE; 3912 } 3913 PMAP_UNLOCK(pmap); 3914 return (rv); 3915} 3916 3917/* 3918 * pmap_is_referenced: 3919 * 3920 * Return whether or not the specified physical page was referenced 3921 * in any physical maps. 3922 */ 3923boolean_t 3924pmap_is_referenced(vm_page_t m) 3925{ 3926 3927 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3928 ("pmap_is_referenced: page %p is not managed", m)); 3929 return (pmap_page_test_mappings(m, TRUE, FALSE)); 3930} 3931 3932/* 3933 * Clear the write and modified bits in each of the given page's mappings. 3934 */ 3935void 3936pmap_remove_write(vm_page_t m) 3937{ 3938 struct md_page *pvh; 3939 pmap_t pmap; 3940 struct rwlock *lock; 3941 pv_entry_t next_pv, pv; 3942 pt_entry_t oldpte, *pte; 3943 vm_offset_t va; 3944 int lvl, md_gen, pvh_gen; 3945 3946 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3947 ("pmap_remove_write: page %p is not managed", m)); 3948 3949 /* 3950 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3951 * set by another thread while the object is locked. Thus, 3952 * if PGA_WRITEABLE is clear, no page table entries need updating. 3953 */ 3954 VM_OBJECT_ASSERT_WLOCKED(m->object); 3955 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3956 return; 3957 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3958 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : 3959 pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3960retry_pv_loop: 3961 rw_wlock(lock); 3962 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 3963 pmap = PV_PMAP(pv); 3964 if (!PMAP_TRYLOCK(pmap)) { 3965 pvh_gen = pvh->pv_gen; 3966 rw_wunlock(lock); 3967 PMAP_LOCK(pmap); 3968 rw_wlock(lock); 3969 if (pvh_gen != pvh->pv_gen) { 3970 PMAP_UNLOCK(pmap); 3971 rw_wunlock(lock); 3972 goto retry_pv_loop; 3973 } 3974 } 3975 va = pv->pv_va; 3976 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3977 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) 3978 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET, 3979 &lock); 3980 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 3981 ("inconsistent pv lock %p %p for page %p", 3982 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 3983 PMAP_UNLOCK(pmap); 3984 } 3985 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3986 pmap = PV_PMAP(pv); 3987 if (!PMAP_TRYLOCK(pmap)) { 3988 pvh_gen = pvh->pv_gen; 3989 md_gen = m->md.pv_gen; 3990 rw_wunlock(lock); 3991 PMAP_LOCK(pmap); 3992 rw_wlock(lock); 3993 if (pvh_gen != pvh->pv_gen || 3994 md_gen != m->md.pv_gen) { 3995 PMAP_UNLOCK(pmap); 3996 rw_wunlock(lock); 3997 goto retry_pv_loop; 3998 } 3999 } 4000 pte = pmap_pte(pmap, pv->pv_va, &lvl); 4001retry: 4002 oldpte = pmap_load(pte); 4003 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) { 4004 if (!atomic_cmpset_long(pte, oldpte, 4005 oldpte | ATTR_AP(ATTR_AP_RO))) 4006 goto retry; 4007 if ((oldpte & ATTR_AF) != 0) 4008 vm_page_dirty(m); 4009 pmap_invalidate_page(pmap, pv->pv_va); 4010 } 4011 PMAP_UNLOCK(pmap); 4012 } 4013 rw_wunlock(lock); 4014 vm_page_aflag_clear(m, PGA_WRITEABLE); 4015} 4016 4017static __inline boolean_t 4018safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte) 4019{ 4020 4021 return (FALSE); 4022} 4023 4024/* 4025 * pmap_ts_referenced: 4026 * 4027 * Return a count of reference bits for a page, clearing those bits. 4028 * It is not necessary for every reference bit to be cleared, but it 4029 * is necessary that 0 only be returned when there are truly no 4030 * reference bits set. 4031 * 4032 * As an optimization, update the page's dirty field if a modified bit is 4033 * found while counting reference bits. This opportunistic update can be 4034 * performed at low cost and can eliminate the need for some future calls 4035 * to pmap_is_modified(). However, since this function stops after 4036 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 4037 * dirty pages. Those dirty pages will only be detected by a future call 4038 * to pmap_is_modified(). 4039 */ 4040int 4041pmap_ts_referenced(vm_page_t m) 4042{ 4043 struct md_page *pvh; 4044 pv_entry_t pv, pvf; 4045 pmap_t pmap; 4046 struct rwlock *lock; 4047 pd_entry_t *pde, tpde; 4048 pt_entry_t *pte, tpte; 4049 pt_entry_t *l3; 4050 vm_offset_t va; 4051 vm_paddr_t pa; 4052 int cleared, md_gen, not_cleared, lvl, pvh_gen; 4053 struct spglist free; 4054 bool demoted; 4055 4056 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4057 ("pmap_ts_referenced: page %p is not managed", m)); 4058 SLIST_INIT(&free); 4059 cleared = 0; 4060 pa = VM_PAGE_TO_PHYS(m); 4061 lock = PHYS_TO_PV_LIST_LOCK(pa); 4062 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa); 4063 rw_wlock(lock); 4064retry: 4065 not_cleared = 0; 4066 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 4067 goto small_mappings; 4068 pv = pvf; 4069 do { 4070 if (pvf == NULL) 4071 pvf = pv; 4072 pmap = PV_PMAP(pv); 4073 if (!PMAP_TRYLOCK(pmap)) { 4074 pvh_gen = pvh->pv_gen; 4075 rw_wunlock(lock); 4076 PMAP_LOCK(pmap); 4077 rw_wlock(lock); 4078 if (pvh_gen != pvh->pv_gen) { 4079 PMAP_UNLOCK(pmap); 4080 goto retry; 4081 } 4082 } 4083 va = pv->pv_va; 4084 pde = pmap_pde(pmap, pv->pv_va, &lvl); 4085 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found")); 4086 KASSERT(lvl == 1, 4087 ("pmap_ts_referenced: invalid pde level %d", lvl)); 4088 tpde = pmap_load(pde); 4089 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE, 4090 ("pmap_ts_referenced: found an invalid l1 table")); 4091 pte = pmap_l1_to_l2(pde, pv->pv_va); 4092 tpte = pmap_load(pte); 4093 if (pmap_page_dirty(tpte)) { 4094 /* 4095 * Although "tpte" is mapping a 2MB page, because 4096 * this function is called at a 4KB page granularity, 4097 * we only update the 4KB page under test. 4098 */ 4099 vm_page_dirty(m); 4100 } 4101 if ((tpte & ATTR_AF) != 0) { 4102 /* 4103 * Since this reference bit is shared by 512 4KB 4104 * pages, it should not be cleared every time it is 4105 * tested. Apply a simple "hash" function on the 4106 * physical page number, the virtual superpage number, 4107 * and the pmap address to select one 4KB page out of 4108 * the 512 on which testing the reference bit will 4109 * result in clearing that reference bit. This 4110 * function is designed to avoid the selection of the 4111 * same 4KB page for every 2MB page mapping. 4112 * 4113 * On demotion, a mapping that hasn't been referenced 4114 * is simply destroyed. To avoid the possibility of a 4115 * subsequent page fault on a demoted wired mapping, 4116 * always leave its reference bit set. Moreover, 4117 * since the superpage is wired, the current state of 4118 * its reference bit won't affect page replacement. 4119 */ 4120 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^ 4121 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 && 4122 (tpte & ATTR_SW_WIRED) == 0) { 4123 if (safe_to_clear_referenced(pmap, tpte)) { 4124 /* 4125 * TODO: We don't handle the access 4126 * flag at all. We need to be able 4127 * to set it in the exception handler. 4128 */ 4129 panic("ARM64TODO: " 4130 "safe_to_clear_referenced\n"); 4131 } else if (pmap_demote_l2_locked(pmap, pte, 4132 pv->pv_va, &lock) != NULL) { 4133 demoted = true; 4134 va += VM_PAGE_TO_PHYS(m) - 4135 (tpte & ~ATTR_MASK); 4136 l3 = pmap_l2_to_l3(pte, va); 4137 pmap_remove_l3(pmap, l3, va, 4138 pmap_load(pte), NULL, &lock); 4139 } else 4140 demoted = true; 4141 4142 if (demoted) { 4143 /* 4144 * The superpage mapping was removed 4145 * entirely and therefore 'pv' is no 4146 * longer valid. 4147 */ 4148 if (pvf == pv) 4149 pvf = NULL; 4150 pv = NULL; 4151 } 4152 cleared++; 4153 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 4154 ("inconsistent pv lock %p %p for page %p", 4155 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 4156 } else 4157 not_cleared++; 4158 } 4159 PMAP_UNLOCK(pmap); 4160 /* Rotate the PV list if it has more than one entry. */ 4161 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) { 4162 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4163 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 4164 pvh->pv_gen++; 4165 } 4166 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX) 4167 goto out; 4168 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 4169small_mappings: 4170 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 4171 goto out; 4172 pv = pvf; 4173 do { 4174 if (pvf == NULL) 4175 pvf = pv; 4176 pmap = PV_PMAP(pv); 4177 if (!PMAP_TRYLOCK(pmap)) { 4178 pvh_gen = pvh->pv_gen; 4179 md_gen = m->md.pv_gen; 4180 rw_wunlock(lock); 4181 PMAP_LOCK(pmap); 4182 rw_wlock(lock); 4183 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 4184 PMAP_UNLOCK(pmap); 4185 goto retry; 4186 } 4187 } 4188 pde = pmap_pde(pmap, pv->pv_va, &lvl); 4189 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found")); 4190 KASSERT(lvl == 2, 4191 ("pmap_ts_referenced: invalid pde level %d", lvl)); 4192 tpde = pmap_load(pde); 4193 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE, 4194 ("pmap_ts_referenced: found an invalid l2 table")); 4195 pte = pmap_l2_to_l3(pde, pv->pv_va); 4196 tpte = pmap_load(pte); 4197 if (pmap_page_dirty(tpte)) 4198 vm_page_dirty(m); 4199 if ((tpte & ATTR_AF) != 0) { 4200 if (safe_to_clear_referenced(pmap, tpte)) { 4201 /* 4202 * TODO: We don't handle the access flag 4203 * at all. We need to be able to set it in 4204 * the exception handler. 4205 */ 4206 panic("ARM64TODO: safe_to_clear_referenced\n"); 4207 } else if ((tpte & ATTR_SW_WIRED) == 0) { 4208 /* 4209 * Wired pages cannot be paged out so 4210 * doing accessed bit emulation for 4211 * them is wasted effort. We do the 4212 * hard work for unwired pages only. 4213 */ 4214 pmap_remove_l3(pmap, pte, pv->pv_va, tpde, 4215 &free, &lock); 4216 pmap_invalidate_page(pmap, pv->pv_va); 4217 cleared++; 4218 if (pvf == pv) 4219 pvf = NULL; 4220 pv = NULL; 4221 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 4222 ("inconsistent pv lock %p %p for page %p", 4223 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 4224 } else 4225 not_cleared++; 4226 } 4227 PMAP_UNLOCK(pmap); 4228 /* Rotate the PV list if it has more than one entry. */ 4229 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) { 4230 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4231 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 4232 m->md.pv_gen++; 4233 } 4234 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared + 4235 not_cleared < PMAP_TS_REFERENCED_MAX); 4236out: 4237 rw_wunlock(lock); 4238 pmap_free_zero_pages(&free); 4239 return (cleared + not_cleared); 4240} 4241 4242/* 4243 * Apply the given advice to the specified range of addresses within the 4244 * given pmap. Depending on the advice, clear the referenced and/or 4245 * modified flags in each mapping and set the mapped page's dirty field. 4246 */ 4247void 4248pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4249{ 4250} 4251 4252/* 4253 * Clear the modify bits on the specified physical page. 4254 */ 4255void 4256pmap_clear_modify(vm_page_t m) 4257{ 4258 4259 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4260 ("pmap_clear_modify: page %p is not managed", m)); 4261 VM_OBJECT_ASSERT_WLOCKED(m->object); 4262 KASSERT(!vm_page_xbusied(m), 4263 ("pmap_clear_modify: page %p is exclusive busied", m)); 4264 4265 /* 4266 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 4267 * If the object containing the page is locked and the page is not 4268 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4269 */ 4270 if ((m->aflags & PGA_WRITEABLE) == 0) 4271 return; 4272 4273 /* ARM64TODO: We lack support for tracking if a page is modified */ 4274} 4275 4276void * 4277pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4278{ 4279 4280 return ((void *)PHYS_TO_DMAP(pa)); 4281} 4282 4283void 4284pmap_unmapbios(vm_paddr_t pa, vm_size_t size) 4285{ 4286} 4287 4288/* 4289 * Sets the memory attribute for the specified page. 4290 */ 4291void 4292pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4293{ 4294 4295 m->md.pv_memattr = ma; 4296 4297 /* 4298 * If "m" is a normal page, update its direct mapping. This update 4299 * can be relied upon to perform any cache operations that are 4300 * required for data coherence. 4301 */ 4302 if ((m->flags & PG_FICTITIOUS) == 0 && 4303 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE, 4304 m->md.pv_memattr) != 0) 4305 panic("memory attribute change on the direct map failed"); 4306} 4307 4308/* 4309 * Changes the specified virtual address range's memory type to that given by 4310 * the parameter "mode". The specified virtual address range must be 4311 * completely contained within either the direct map or the kernel map. If 4312 * the virtual address range is contained within the kernel map, then the 4313 * memory type for each of the corresponding ranges of the direct map is also 4314 * changed. (The corresponding ranges of the direct map are those ranges that 4315 * map the same physical pages as the specified virtual address range.) These 4316 * changes to the direct map are necessary because Intel describes the 4317 * behavior of their processors as "undefined" if two or more mappings to the 4318 * same physical page have different memory types. 4319 * 4320 * Returns zero if the change completed successfully, and either EINVAL or 4321 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4322 * of the virtual address range was not mapped, and ENOMEM is returned if 4323 * there was insufficient memory available to complete the change. In the 4324 * latter case, the memory type may have been changed on some part of the 4325 * virtual address range or the direct map. 4326 */ 4327static int 4328pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4329{ 4330 int error; 4331 4332 PMAP_LOCK(kernel_pmap); 4333 error = pmap_change_attr_locked(va, size, mode); 4334 PMAP_UNLOCK(kernel_pmap); 4335 return (error); 4336} 4337 4338static int 4339pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode) 4340{ 4341 vm_offset_t base, offset, tmpva; 4342 pt_entry_t l3, *pte, *newpte; 4343 int lvl; 4344 4345 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED); 4346 base = trunc_page(va); 4347 offset = va & PAGE_MASK; 4348 size = round_page(offset + size); 4349 4350 if (!VIRT_IN_DMAP(base)) 4351 return (EINVAL); 4352 4353 for (tmpva = base; tmpva < base + size; ) { 4354 pte = pmap_pte(kernel_pmap, va, &lvl); 4355 if (pte == NULL) 4356 return (EINVAL); 4357 4358 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) { 4359 /* 4360 * We already have the correct attribute, 4361 * ignore this entry. 4362 */ 4363 switch (lvl) { 4364 default: 4365 panic("Invalid DMAP table level: %d\n", lvl); 4366 case 1: 4367 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE; 4368 break; 4369 case 2: 4370 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE; 4371 break; 4372 case 3: 4373 tmpva += PAGE_SIZE; 4374 break; 4375 } 4376 } else { 4377 /* 4378 * Split the entry to an level 3 table, then 4379 * set the new attribute. 4380 */ 4381 switch (lvl) { 4382 default: 4383 panic("Invalid DMAP table level: %d\n", lvl); 4384 case 1: 4385 newpte = pmap_demote_l1(kernel_pmap, pte, 4386 tmpva & ~L1_OFFSET); 4387 if (newpte == NULL) 4388 return (EINVAL); 4389 pte = pmap_l1_to_l2(pte, tmpva); 4390 case 2: 4391 newpte = pmap_demote_l2(kernel_pmap, pte, 4392 tmpva & ~L2_OFFSET); 4393 if (newpte == NULL) 4394 return (EINVAL); 4395 pte = pmap_l2_to_l3(pte, tmpva); 4396 case 3: 4397 /* Update the entry */ 4398 l3 = pmap_load(pte); 4399 l3 &= ~ATTR_IDX_MASK; 4400 l3 |= ATTR_IDX(mode); 4401 if (mode == DEVICE_MEMORY) 4402 l3 |= ATTR_XN; 4403 4404 pmap_update_entry(kernel_pmap, pte, l3, tmpva, 4405 PAGE_SIZE); 4406 4407 /* 4408 * If moving to a non-cacheable entry flush 4409 * the cache. 4410 */ 4411 if (mode == VM_MEMATTR_UNCACHEABLE) 4412 cpu_dcache_wbinv_range(tmpva, L3_SIZE); 4413 4414 break; 4415 } 4416 tmpva += PAGE_SIZE; 4417 } 4418 } 4419 4420 return (0); 4421} 4422 4423/* 4424 * Create an L2 table to map all addresses within an L1 mapping. 4425 */ 4426static pt_entry_t * 4427pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va) 4428{ 4429 pt_entry_t *l2, newl2, oldl1; 4430 vm_offset_t tmpl1; 4431 vm_paddr_t l2phys, phys; 4432 vm_page_t ml2; 4433 int i; 4434 4435 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4436 oldl1 = pmap_load(l1); 4437 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK, 4438 ("pmap_demote_l1: Demoting a non-block entry")); 4439 KASSERT((va & L1_OFFSET) == 0, 4440 ("pmap_demote_l1: Invalid virtual address %#lx", va)); 4441 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0, 4442 ("pmap_demote_l1: Level 1 table shouldn't be managed")); 4443 4444 tmpl1 = 0; 4445 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) { 4446 tmpl1 = kva_alloc(PAGE_SIZE); 4447 if (tmpl1 == 0) 4448 return (NULL); 4449 } 4450 4451 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT | 4452 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 4453 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx" 4454 " in pmap %p", va, pmap); 4455 return (NULL); 4456 } 4457 4458 l2phys = VM_PAGE_TO_PHYS(ml2); 4459 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys); 4460 4461 /* Address the range points at */ 4462 phys = oldl1 & ~ATTR_MASK; 4463 /* The attributed from the old l1 table to be copied */ 4464 newl2 = oldl1 & ATTR_MASK; 4465 4466 /* Create the new entries */ 4467 for (i = 0; i < Ln_ENTRIES; i++) { 4468 l2[i] = newl2 | phys; 4469 phys += L2_SIZE; 4470 } 4471 cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE); 4472 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK), 4473 ("Invalid l2 page (%lx != %lx)", l2[0], 4474 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK)); 4475 4476 if (tmpl1 != 0) { 4477 pmap_kenter(tmpl1, PAGE_SIZE, 4478 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY); 4479 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK)); 4480 } 4481 4482 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE); 4483 4484 if (tmpl1 != 0) { 4485 pmap_kremove(tmpl1); 4486 kva_free(tmpl1, PAGE_SIZE); 4487 } 4488 4489 return (l2); 4490} 4491 4492/* 4493 * Create an L3 table to map all addresses within an L2 mapping. 4494 */ 4495static pt_entry_t * 4496pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va, 4497 struct rwlock **lockp) 4498{ 4499 pt_entry_t *l3, newl3, oldl2; 4500 vm_offset_t tmpl2; 4501 vm_paddr_t l3phys, phys; 4502 vm_page_t ml3; 4503 int i; 4504 4505 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4506 l3 = NULL; 4507 oldl2 = pmap_load(l2); 4508 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK, 4509 ("pmap_demote_l2: Demoting a non-block entry")); 4510 KASSERT((va & L2_OFFSET) == 0, 4511 ("pmap_demote_l2: Invalid virtual address %#lx", va)); 4512 4513 tmpl2 = 0; 4514 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) { 4515 tmpl2 = kva_alloc(PAGE_SIZE); 4516 if (tmpl2 == 0) 4517 return (NULL); 4518 } 4519 4520 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) { 4521 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va), 4522 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) | 4523 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 4524 if (ml3 == NULL) { 4525 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx" 4526 " in pmap %p", va, pmap); 4527 goto fail; 4528 } 4529 if (va < VM_MAXUSER_ADDRESS) 4530 pmap_resident_count_inc(pmap, 1); 4531 } 4532 4533 l3phys = VM_PAGE_TO_PHYS(ml3); 4534 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys); 4535 4536 /* Address the range points at */ 4537 phys = oldl2 & ~ATTR_MASK; 4538 /* The attributed from the old l2 table to be copied */ 4539 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE; 4540 4541 /* 4542 * If the page table page is new, initialize it. 4543 */ 4544 if (ml3->wire_count == 1) { 4545 for (i = 0; i < Ln_ENTRIES; i++) { 4546 l3[i] = newl3 | phys; 4547 phys += L3_SIZE; 4548 } 4549 cpu_dcache_wb_range((vm_offset_t)l3, PAGE_SIZE); 4550 } 4551 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE), 4552 ("Invalid l3 page (%lx != %lx)", l3[0], 4553 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE)); 4554 4555 /* 4556 * Map the temporary page so we don't lose access to the l2 table. 4557 */ 4558 if (tmpl2 != 0) { 4559 pmap_kenter(tmpl2, PAGE_SIZE, 4560 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY); 4561 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK)); 4562 } 4563 4564 /* 4565 * The spare PV entries must be reserved prior to demoting the 4566 * mapping, that is, prior to changing the PDE. Otherwise, the state 4567 * of the L2 and the PV lists will be inconsistent, which can result 4568 * in reclaim_pv_chunk() attempting to remove a PV entry from the 4569 * wrong PV list and pmap_pv_demote_l2() failing to find the expected 4570 * PV entry for the 2MB page mapping that is being demoted. 4571 */ 4572 if ((oldl2 & ATTR_SW_MANAGED) != 0) 4573 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp); 4574 4575 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE); 4576 4577 /* 4578 * Demote the PV entry. 4579 */ 4580 if ((oldl2 & ATTR_SW_MANAGED) != 0) 4581 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp); 4582 4583 atomic_add_long(&pmap_l2_demotions, 1); 4584 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx" 4585 " in pmap %p %lx", va, pmap, l3[0]); 4586 4587fail: 4588 if (tmpl2 != 0) { 4589 pmap_kremove(tmpl2); 4590 kva_free(tmpl2, PAGE_SIZE); 4591 } 4592 4593 return (l3); 4594 4595} 4596 4597static pt_entry_t * 4598pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va) 4599{ 4600 struct rwlock *lock; 4601 pt_entry_t *l3; 4602 4603 lock = NULL; 4604 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock); 4605 if (lock != NULL) 4606 rw_wunlock(lock); 4607 return (l3); 4608} 4609 4610/* 4611 * perform the pmap work for mincore 4612 */ 4613int 4614pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4615{ 4616 pd_entry_t *l1p, l1; 4617 pd_entry_t *l2p, l2; 4618 pt_entry_t *l3p, l3; 4619 vm_paddr_t pa; 4620 bool managed; 4621 int val; 4622 4623 PMAP_LOCK(pmap); 4624retry: 4625 pa = 0; 4626 val = 0; 4627 managed = false; 4628 4629 l1p = pmap_l1(pmap, addr); 4630 if (l1p == NULL) /* No l1 */ 4631 goto done; 4632 4633 l1 = pmap_load(l1p); 4634 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL) 4635 goto done; 4636 4637 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) { 4638 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET); 4639 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED; 4640 val = MINCORE_SUPER | MINCORE_INCORE; 4641 if (pmap_page_dirty(l1)) 4642 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4643 if ((l1 & ATTR_AF) == ATTR_AF) 4644 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4645 goto done; 4646 } 4647 4648 l2p = pmap_l1_to_l2(l1p, addr); 4649 if (l2p == NULL) /* No l2 */ 4650 goto done; 4651 4652 l2 = pmap_load(l2p); 4653 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL) 4654 goto done; 4655 4656 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) { 4657 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET); 4658 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED; 4659 val = MINCORE_SUPER | MINCORE_INCORE; 4660 if (pmap_page_dirty(l2)) 4661 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4662 if ((l2 & ATTR_AF) == ATTR_AF) 4663 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4664 goto done; 4665 } 4666 4667 l3p = pmap_l2_to_l3(l2p, addr); 4668 if (l3p == NULL) /* No l3 */ 4669 goto done; 4670 4671 l3 = pmap_load(l2p); 4672 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL) 4673 goto done; 4674 4675 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) { 4676 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET); 4677 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED; 4678 val = MINCORE_INCORE; 4679 if (pmap_page_dirty(l3)) 4680 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4681 if ((l3 & ATTR_AF) == ATTR_AF) 4682 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4683 } 4684 4685done: 4686 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4687 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 4688 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4689 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4690 goto retry; 4691 } else 4692 PA_UNLOCK_COND(*locked_pa); 4693 PMAP_UNLOCK(pmap); 4694 4695 return (val); 4696} 4697 4698void 4699pmap_activate(struct thread *td) 4700{ 4701 pmap_t pmap; 4702 4703 critical_enter(); 4704 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4705 td->td_pcb->pcb_l0addr = vtophys(pmap->pm_l0); 4706 __asm __volatile("msr ttbr0_el1, %0" : : "r"(td->td_pcb->pcb_l0addr)); 4707 pmap_invalidate_all(pmap); 4708 critical_exit(); 4709} 4710 4711void 4712pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz) 4713{ 4714 4715 if (va >= VM_MIN_KERNEL_ADDRESS) { 4716 cpu_icache_sync_range(va, sz); 4717 } else { 4718 u_int len, offset; 4719 vm_paddr_t pa; 4720 4721 /* Find the length of data in this page to flush */ 4722 offset = va & PAGE_MASK; 4723 len = imin(PAGE_SIZE - offset, sz); 4724 4725 while (sz != 0) { 4726 /* Extract the physical address & find it in the DMAP */ 4727 pa = pmap_extract(pmap, va); 4728 if (pa != 0) 4729 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len); 4730 4731 /* Move to the next page */ 4732 sz -= len; 4733 va += len; 4734 /* Set the length for the next iteration */ 4735 len = imin(PAGE_SIZE, sz); 4736 } 4737 } 4738} 4739 4740int 4741pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far) 4742{ 4743#ifdef SMP 4744 uint64_t par; 4745#endif 4746 4747 switch (ESR_ELx_EXCEPTION(esr)) { 4748 case EXCP_DATA_ABORT_L: 4749 case EXCP_DATA_ABORT: 4750 break; 4751 default: 4752 return (KERN_FAILURE); 4753 } 4754 4755#ifdef SMP 4756 PMAP_LOCK(pmap); 4757 switch (esr & ISS_DATA_DFSC_MASK) { 4758 case ISS_DATA_DFSC_TF_L0: 4759 case ISS_DATA_DFSC_TF_L1: 4760 case ISS_DATA_DFSC_TF_L2: 4761 case ISS_DATA_DFSC_TF_L3: 4762 /* Ask the MMU to check the address */ 4763 if (pmap == kernel_pmap) 4764 par = arm64_address_translate_s1e1r(far); 4765 else 4766 par = arm64_address_translate_s1e0r(far); 4767 4768 /* 4769 * If the translation was successful the address was invalid 4770 * due to a break-before-make sequence. We can unlock and 4771 * return success to the trap handler. 4772 */ 4773 if (PAR_SUCCESS(par)) { 4774 PMAP_UNLOCK(pmap); 4775 return (KERN_SUCCESS); 4776 } 4777 break; 4778 default: 4779 break; 4780 } 4781 PMAP_UNLOCK(pmap); 4782#endif 4783 4784 return (KERN_FAILURE); 4785} 4786 4787/* 4788 * Increase the starting virtual address of the given mapping if a 4789 * different alignment might result in more superpage mappings. 4790 */ 4791void 4792pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4793 vm_offset_t *addr, vm_size_t size) 4794{ 4795 vm_offset_t superpage_offset; 4796 4797 if (size < L2_SIZE) 4798 return; 4799 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4800 offset += ptoa(object->pg_color); 4801 superpage_offset = offset & L2_OFFSET; 4802 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE || 4803 (*addr & L2_OFFSET) == superpage_offset) 4804 return; 4805 if ((*addr & L2_OFFSET) < superpage_offset) 4806 *addr = (*addr & ~L2_OFFSET) + superpage_offset; 4807 else 4808 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset; 4809} 4810 4811/** 4812 * Get the kernel virtual address of a set of physical pages. If there are 4813 * physical addresses not covered by the DMAP perform a transient mapping 4814 * that will be removed when calling pmap_unmap_io_transient. 4815 * 4816 * \param page The pages the caller wishes to obtain the virtual 4817 * address on the kernel memory map. 4818 * \param vaddr On return contains the kernel virtual memory address 4819 * of the pages passed in the page parameter. 4820 * \param count Number of pages passed in. 4821 * \param can_fault TRUE if the thread using the mapped pages can take 4822 * page faults, FALSE otherwise. 4823 * 4824 * \returns TRUE if the caller must call pmap_unmap_io_transient when 4825 * finished or FALSE otherwise. 4826 * 4827 */ 4828boolean_t 4829pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 4830 boolean_t can_fault) 4831{ 4832 vm_paddr_t paddr; 4833 boolean_t needs_mapping; 4834 int error, i; 4835 4836 /* 4837 * Allocate any KVA space that we need, this is done in a separate 4838 * loop to prevent calling vmem_alloc while pinned. 4839 */ 4840 needs_mapping = FALSE; 4841 for (i = 0; i < count; i++) { 4842 paddr = VM_PAGE_TO_PHYS(page[i]); 4843 if (__predict_false(!PHYS_IN_DMAP(paddr))) { 4844 error = vmem_alloc(kernel_arena, PAGE_SIZE, 4845 M_BESTFIT | M_WAITOK, &vaddr[i]); 4846 KASSERT(error == 0, ("vmem_alloc failed: %d", error)); 4847 needs_mapping = TRUE; 4848 } else { 4849 vaddr[i] = PHYS_TO_DMAP(paddr); 4850 } 4851 } 4852 4853 /* Exit early if everything is covered by the DMAP */ 4854 if (!needs_mapping) 4855 return (FALSE); 4856 4857 if (!can_fault) 4858 sched_pin(); 4859 for (i = 0; i < count; i++) { 4860 paddr = VM_PAGE_TO_PHYS(page[i]); 4861 if (!PHYS_IN_DMAP(paddr)) { 4862 panic( 4863 "pmap_map_io_transient: TODO: Map out of DMAP data"); 4864 } 4865 } 4866 4867 return (needs_mapping); 4868} 4869 4870void 4871pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 4872 boolean_t can_fault) 4873{ 4874 vm_paddr_t paddr; 4875 int i; 4876 4877 if (!can_fault) 4878 sched_unpin(); 4879 for (i = 0; i < count; i++) { 4880 paddr = VM_PAGE_TO_PHYS(page[i]); 4881 if (!PHYS_IN_DMAP(paddr)) { 4882 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data"); 4883 } 4884 } 4885} 4886